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"George" <george.martin@att.net> wrote in message news:e9d879fa.0401090645.6a5aa1ff@posting.google.com... > I'm designing an Altera NIOS (could be Xilinx equivalent) CPU system > with external FLASH (and RAM) memory. The Altera FPGA (probably > ACEX1K) has a JTAG port so when I get the 1st prototype I can download > a configuration using the JTAG. But how can I program the FLASH when > it's soldered on the board? > > I can't find a FLASH with a JTAG interface. I can't preprogram the > FLASH since I don't have the code before assembly and probably want to > change it even in the field. > > Any suggestions? > > Thanks > George What about using the jtag to configure the fpga (including the NIOS and a small boot program in "rom"), and then use the NIOS to download a program via a serial cable, ethernet, or other interface and burn the flash with that?Article: 64626
"jk" <z3015094NOSPAM@student.unsw.edu.au> wrote in message news:btltqp$8uu$1@tomahawk.unsw.edu.au... > Hi all, > > trying to follow the advice of one of the regulars on this forum and learn > to use the text based version of ModelSim 5.7. > > However, using the file-find facility I have not been able to find Vsim and > Vlib on my installed version of Mentor Graphics on my machine. Is this > normal? I figured there was actually meant to be files which could be > accessed via the command interface... > > - K > > They should be there somewhere! On a PC you may have to add the path to modelsim to your PATH variable. The vsim and vlib binaries are normally in c:\program files\modelsim5.7\win32 and have names like vsim.exe, vlog.exe, vcom.exe On a unix machine, they also need to be in your path. What operating system are you using? Alan -- Alan Fitch Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 64627
Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3FF9E9AB.7020401@flukenetworks.com>... > David T. wrote: > > > I would appreciate a kick in the right direction. > > > if READ1 = '1' then -- LET HOST READ THE LATCHED STATUS FLAGS > > DAT_OUT(0) <= PCK_READY; -- SET DATA TO LATCHED OUTPUTS > > What does DAT_OUT(0) get when READ1 /= '1' ? > > -- Mike Treseler I hoped it wouldn't matter... doesn't it retain the last state until it is given a new one?. Does it cause problems to leave this condition unattended?... I have to get used to the subtleties of VHDL. Thanks, David ThurlowArticle: 64628
Paul wrote:
> Some IO pins in the submodules can be considered "final" in a design,
> since they connect directly to outside the chip.
> Why rewirte them again and again and risk the chance of typos.
In VHDL lingo, you are talking about the port maps
within the top entity. Some of these are direct
port to port wires, while others require intermediate
signals.
> Why not in the language or in the tools declared them as "final", so
> that when they get included in any module -- no matter how many times,
> they have their own constaints. This would save a lot of copy and
> paste and typos.
I prefer to maintain constraints in the place and route
files rather than in the source code. For
synchronous designs, you don't need very many.
> Do some people actually enjoy aggregating the IO pins again and again?
> Instead of focusing on the design.
I expect that most people don't.
I let emacs vhdl-mode port cut/paste do this for me.
-- Mike Treseler
Article: 64629George, David's description is correct for Xilinx/MicroBlaze as well. I can tell you first hand because I've done what you've described. You can use the MDM (debug module) for JTAG and take the boot program out of the picture, or use XMDSTUB (what David describes as a small boot program) in Block RAM to connect via either JTAG or serial. XMD is a .tcl environment so you can easily use the EDK provided flash.tcl (or modify it if you need to use a different part or bus width) in order to read in your files and transfer them over to the Flash part. You could also avoid the debugger (XMD) altogether and write your own small program to live in Block RAM and move data to Flash that way (perhaps via a serial cable or ethernet). I'd be willing to wager that Nios has very similar capabilities and methods, but for obvious reasons I have only used the MicroBlaze solution for this. Best of luck. Ryan Laity Xilinx Applications David Brown wrote: > "George" <george.martin@att.net> wrote in message > news:e9d879fa.0401090645.6a5aa1ff@posting.google.com... > >>I'm designing an Altera NIOS (could be Xilinx equivalent) CPU system >>with external FLASH (and RAM) memory. The Altera FPGA (probably >>ACEX1K) has a JTAG port so when I get the 1st prototype I can download >>a configuration using the JTAG. But how can I program the FLASH when >>it's soldered on the board? >> >>I can't find a FLASH with a JTAG interface. I can't preprogram the >>FLASH since I don't have the code before assembly and probably want to >>change it even in the field. >> >>Any suggestions? >> >>Thanks >>George > > > What about using the jtag to configure the fpga (including the NIOS and a > small boot program in "rom"), and then use the NIOS to download a program > via a serial cable, ethernet, or other interface and burn the flash with > that? > > >Article: 64630
Well, I have a hard time believing Gibson would choose to "exclusively use" Spartan 3 when they can't even get them. I also seriously doubt Gibson has the raw volume necessary to justify an ASIC these days. I also think that the smallest "hard copy" Altera part is still more expensive on a per part basis than their Cyclone parts are in the same volume -- and it's even worse when you add in the NRE that A would charge for making the hard copy part. I've done that math on several projects now, and hard copy always lost out. Given that, it is certainly in Gibson's interest to have alternate sources of chips for their products. Neither vendor can shut down the production run if they decide to allocate the parts to a "more important" customer, or if a delivery schedule moves out another quarter, or two, or... There isn't anything magic about Cyclone or S3 that would preclude using one over the other. On the flip-side, supporting two different boards adds a bit more burden corporately to Gibson. I also trust that both A and X will try to "out PR" the other whenever possible. This one just seemed odd to me given that both companies either implied or outright stated a certain level of exclusivity. Whatever. PM "Austin Lesea" <austin@xilinx.com> wrote in message news:btmikt$jqt1@cliff.xsj.xilinx.com... > Jim, > > This is true. FPGA business is not usually as tough as the commodity > business model you describe, but hey, if you did the design with both > vendors, then you can bang them together until the lowest price falls out. > > I used to do that all the time when I was in the telecom business. Did > not like it, but I did it. Only because the phone companies bang the > vendors together until the lowest price falls out. > > Austin > > jim granville wrote: > >> Patrick MacGregor wrote: > >> > >>> Last year X announced a cool design win using their parts in a new > >>> Gibson > >>> guitar line. Neat stuff. > >>> > >>> Couple days ago I see that A has a press release saying they stole the > >>> business with NIOS + Cyclone. > >>> > >>> Today I see X saying S3 is the clear winner and Gibson is using it > >>> exclusively. > >>> > >>> Anyone know what is really going on? > >>> > >>> Just curious. The Gibson product is kinda cool regardless of who's > >>> part is > >>> in it. > > > > Austin Lesea wrote: > > > >> Patrick, > >> > >> We are just as puzzled as you. > >> > >> We also saw Altera's press release with Gibson, yet Gibson awarded us > >> the "supplier of the year award" at CES in Las Vegas just moments > >> ago..... > >> > >> http://biz.yahoo.com/prnews/040108/sfth127_1.html > > > > > > Of course, these two do not have to be mutually exclusive... > > > >> > >> Could be they are going to use the "hard-to-copy" program in an > >> attempt to reduce costs, or it could be that a new manager or new > >> consultant has decided that they must "take control" and "make > >> decisions." > >> > >> All very puzzling. > > > > > > Not really. One of the better ways to get improved supply and price > > is to have both brands ready to deploy, so you can > > 'wave the opposition under the rep's nose'. > > It also does no harm, if you really do intend to move to ASIC, > > and if there are questions about availability of either vendor's > > devices, this also makes sound sense. > > Where is the puzzle here ? > > > > -jg > > >Article: 64631
Chris Carlen wrote:
> Is there good modeling style info in Xilinx tools so that one can learn
> how to make synthesizable models for Xilinx tools reliably?
Use a synchronous template for all processes
to minimize synthesis problems.
> Finally, how to VHDL and Verilog compare in terms of *inherent*
> synthesizability of models, or does the same problem essentially exist
> for both?
They are the same for register level design descriptions.
VHDL allows synthesis using more complex data structures
and algorithms.
-- Mike Treseler
Article: 64632Amontec Team wrote: > > Are there any difference between "CORE" and "IP"? (thinking terminology) The terms are used interchangeably. "Core" has the advantage of not also meaning internet protocol. -- Mike TreselerArticle: 64633
Run it through the mapper. The mapper will give you a report. "Chris" <Chris@nospam.com> wrote in message news:btmpv0$5on$1@news5.svr.pol.co.uk... > Hi > > I've done a design in VHDL using the XILINX software and I was wondering, > how can I tell how much of the FPGA my design uses? I was hoping I would be > able to find out what percentage of the FPGA my design uses. > > Thanks, > >Article: 64634
Nick, Readback is performed on a frame basis. A Column, (CLB/IO/BRAM) contains many frames, and a frame covers many CLBs (or LUT RAMs if you line them up vertically). Please take a look at XAPP138/151 for more information. Regards, Wei Nick wrote: > Hi everybosy, > > I was wondering whether the distributed/block selectRAM+ readback > facility can be perfomed on a single block at a time, or does it have > to be performed on all blocks? > > Similarly, can the memory configuration read back be performed in > sections or does it have to be done on the whole memory? > > Thanks > > Nick > >Article: 64635
Because of the "down-binning," using timing relative to the fastest speed grade may be the "safe" way to go. >From an earlier communication with the fine Apps folks at Xilinx: ] To get a path minimum, a rule of thumb is to look at the fastest speed ] grade part for the given density and find the maximum specification in ] the datasheet. Then a minimum should be no less than 1/4 of the maximum ] value. ] ] Example: ] You are concerned about the clock-to-out path for a CoolRunner-II 384 ] macrocell device in a -10 speed grade. ] ] 1. Open the XC2C384 datasheet and look for Tco (clock to out) ] 2. Look up Tco for the fastest speed grade (-7 is fastest in this ] density) ] 3. Multiply this value by 0.25 to find the minimum value for Tco ] ] The reason that you must use the fastest speed grade is because a part ] may be sorted into a slow speed grade due to only one timing path not ] meeting the faster speed requirements. As a result, 99% of the device ] could be a faster speed grade so we must assume the part is the fastest ] speed grade. If 10% is a "better" number than this rule of thumb, I'd love to know.Article: 64636
jcocozza@juno.com (jc) wrote in message news:<8e698b60.0401060636.6fc1d7a8@posting.google.com>... > I have a input signal thats get registered and then outputed on > another signal (pad) One register delay. I would like the Output > register to used instead of the Input register. I am using Xilinx ISE, > VHDL and a Virtex II device. Everytime I implement the Input register > is used, how do I use the Output register. I am trying to improve the > clock to pad time. > > Thanks > John C John, Since this is a Virtex-II device and you already have IOB FFs enabled, all you need to do is add a BEL constraint to OFF1 or OFF2: INST "FF_Name" BEL = OFF1 ; IOB BEL constraints aren't supported for architectures older than Virtex-II, so for a Virtex-E design, one of the following map constraints could be used: 1. Give FF and output pad the same BLKNM constraint. 2. Give FF and output pad the same LOC constraint. 3. Apply a KEEP constraint to the FF D input net, assuming fanout of 1. Regards, BretArticle: 64637
Patrick MacGregor wrote: > > Well, I have a hard time believing Gibson would choose to "exclusively use" > Spartan 3 when they can't even get them. I also seriously doubt Gibson has > the raw volume necessary to justify an ASIC these days. I also think that > the smallest "hard copy" Altera part is still more expensive on a per part > basis than their Cyclone parts are in the same volume -- and it's even worse > when you add in the NRE that A would charge for making the hard copy part. > I've done that math on several projects now, and hard copy always lost out. > > Given that, it is certainly in Gibson's interest to have alternate sources > of chips for their products. Neither vendor can shut down the production > run if they decide to allocate the parts to a "more important" customer, or > if a delivery schedule moves out another quarter, or two, or... There isn't > anything magic about Cyclone or S3 that would preclude using one over the > other. > > On the flip-side, supporting two different boards adds a bit more burden > corporately to Gibson. > > I also trust that both A and X will try to "out PR" the other whenever > possible. This one just seemed odd to me given that both companies either > implied or outright stated a certain level of exclusivity. It is not often that a company will put two different designs into production. But they will pursue two designs far enough to let the vendors know that they *have* to compete on price. I also worked for a telecom test company who used this technique. Once you get a price from one of these vendors, they almost never raise the bar. So you can then go to production with the winning design. The downside is that to do this you have to make your HDL code generic, not using any of the special features of either family of parts. This allows you to reuse the code in the next design without a lot of porting troubles.Article: 64638
Lurking around I found 72Mbit parts. These are MCM's, of course. http://www.gsitechnology.com/72MbBurst.htm -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "Peter Alfke" <peter@xilinx.com> wrote in message news:3FFDF8A2.A649E2FA@xilinx.com... > Let's remember that the original question was for 256 Mbits = 32 MBytes. > That's several generations of Moore's Law away. > If you figure six transistors per memory bit (plus decoding), that > device would be getting close to 2 Billion transistors. Even the largest > FPGAs have a factor 4 fewer tightly-packed transistors, and they command > a price of >$ 1000. > > If you really need RANDOM access in 10 ns, this may be impossible today. > If there is some structure, predictability etc, then you might be able > to do it with DRAMs plus caching (???) > Peter Alfke > ========== > Uwe Bonnes wrote: > > > > Alex Rast <ad.rast.7@nwnotlink.nospam.com> wrote: > > ... > > : The biggest async parts (the classic SRAM, super-simple interfacing) are > > : the 16 Mbit parts from Cypress (CY7C1061AV33) and Toshiba (TC55V16100FT). > > : Sync parts (much more complex interfacing, a bit of a PITA) are the 72 Mbit > > > > At least the Cypress page doesn't sound like instant availability for the > > 16M asynchronous parts > > -- > > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 64639
I think that "25% of the max value of the fastest part" is not conservative enough. I prefer 10%. This difference ( of perhaps a single ns!) may just indicate different degrees of conservativism ( or experience, or grey hair. I have plenty of those. ) I also like to sleep at night, with a good conscience... Peter Alfke ====================== John_H wrote: > > Because of the "down-binning," using timing relative to the fastest speed > grade may be the "safe" way to go. > > From an earlier communication with the fine Apps folks at Xilinx: > > ] To get a path minimum, a rule of thumb is to look at the fastest speed > ] grade part for the given density and find the maximum specification in > ] the datasheet. Then a minimum should be no less than 1/4 of the maximum > ] value. > ] > ] Example: > ] You are concerned about the clock-to-out path for a CoolRunner-II 384 > ] macrocell device in a -10 speed grade. > ] > ] 1. Open the XC2C384 datasheet and look for Tco (clock to out) > ] 2. Look up Tco for the fastest speed grade (-7 is fastest in this > ] density) > ] 3. Multiply this value by 0.25 to find the minimum value for Tco > ] > ] The reason that you must use the fastest speed grade is because a part > ] may be sorted into a slow speed grade due to only one timing path not > ] meeting the faster speed requirements. As a result, 99% of the device > ] could be a faster speed grade so we must assume the part is the fastest > ] speed grade. > > If 10% is a "better" number than this rule of thumb, I'd love to know.Article: 64640
"David Brown" <david@no.westcontrol.spam.com> wrote in message news:<btnb6m$63k$1@news.netpower.no>... > "George" <george.martin@att.net> wrote in message > news:e9d879fa.0401090645.6a5aa1ff@posting.google.com... > > I'm designing an Altera NIOS (could be Xilinx equivalent) CPU system > > with external FLASH (and RAM) memory. The Altera FPGA (probably > > ACEX1K) has a JTAG port so when I get the 1st prototype I can download > > a configuration using the JTAG. But how can I program the FLASH when > > it's soldered on the board? > > > > I can't find a FLASH with a JTAG interface. I can't preprogram the > > FLASH since I don't have the code before assembly and probably want to > > change it even in the field. > > > > Any suggestions? > > > > Thanks > > George > > What about using the jtag to configure the fpga (including the NIOS and a > small boot program in "rom"), and then use the NIOS to download a program > via a serial cable, ethernet, or other interface and burn the flash with > that? I think you mean "rom" is housed in the fpga. Perhaps a small boot program would fit into the the FPGA rom space. But I'm afraid a full fpga would not have enough space. I'll look into that and post a follow up message here. Any ohter suggestions.Article: 64641
On Fri, 09 Jan 2004 00:15:23 -0800, Thomas Stanka wrote: > "B. Joshua Rosen" <bjrosen@polybus.com> wrote: >> On Wed, 07 Jan 2004 10:21:46 -0800, Chris Carlen wrote: > > I would say, that's the difference between someone just learning the > HDL and an experienced HW-Designer. A good book about synthesis will > help. Experience or an experienced tutor will might be the other > solution. > As I bet there's somenone likely starting to bash on VHDL and telling > me that will never happen with Verilog, I would bet anything, the same > problem will rise when using Systemverilog (which is intended to > replace Verilog in the next years). > > bye Thomas Stanka Verilog is a very simple language so it's easier for the tools guys to get it right. Personnally I stick strictly to Verilog 95, I'm not even considering using any Verilog 2001 constructs in synthesizable code for another year. As for things like System C, that's targeted at testbenches at the moment, I do think that there are any synthesis tools that can handle it.Article: 64642
george.martin@att.net (George) wrote in message news:<e9d879fa.0401090645.6a5aa1ff@posting.google.com>... >But how can I program the FLASH when it's soldered on the board? > > I can't find a FLASH with a JTAG interface. I can't preprogram the > FLASH since I don't have the code before assembly and probably want to > change it even in the field. If all the flash pins are attached to the Altera, you can use the JTAG boundary scan capabilities of the Altera to program the flash. Google "jtag flash program" came up with many vendors of tools and software that does this. Alan Nishioka alann@accom.comArticle: 64643
Hi I've done a design in VHDL using the XILINX software and I was wondering, how can I tell how much of the FPGA my design uses? I was hoping I would be able to find out what percentage of the FPGA my design uses. Thanks,Article: 64644
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<lEgLb.1476$rt.397@newssvr29.news.prodigy.com>... > I'm trying to determine if anyone makes a large/fast static RAM part. 16M > (or more) x 16 bits (or more), 10ns. > > I can't afford the address-to-data-out latency of dynamic RAM. There are > ways around this, of course, but SRAM would be so much simpler. > > Any ideas? > > Thanks, As everyone has said, SRAM is not an option at 16.16M for many many years. Ordinarily DRAM isn't an option either at 10ns atleast not SDRAM & DDRAM. But if you can live with 20ns RAS cycle RLDRAM can do it, at 256M today. Its 8 way banked and has separate IO for brutal bandwidth at 400MHz by 8,16,32. look at Infineon and Micron sites. Xilinx has docs on it as well in their memory section. Avnet IIRC has an eval board with a slightly slower version. There are also other faster DRAMs from the other guys, but not quite as fast as I can tell. IBM makes DRAM that cycles in 5ns or so for internal cache (EET article), but I don't think there will be any external product at that speed till the DRAM guys get demand from... Hope that helps johnjaksonATusaDOTcomArticle: 64645
specifically, check the file with the suffix .mrp in your synthesis directory. -- Regards, John Retta email : jretta@rtc-inc.com web : www.rtc-inc.com "Brannon King" <bking@starbridgesystems.com> wrote in message news:btmrm8$jhv@dispatch.concentric.net... > Run it through the mapper. The mapper will give you a report. > > "Chris" <Chris@nospam.com> wrote in message > news:btmpv0$5on$1@news5.svr.pol.co.uk... > > Hi > > > > I've done a design in VHDL using the XILINX software and I was wondering, > > how can I tell how much of the FPGA my design uses? I was hoping I would > be > > able to find out what percentage of the FPGA my design uses. > > > > Thanks, > > > > > >Article: 64646
>The downside is that to do this you have to make your HDL code generic, >not using any of the special features of either family of parts. This >allows you to reuse the code in the next design without a lot of porting >troubles. Plan 1 is that you write your code so it runs on several vendors, and then you play them against eachother for a low price. Plan 2 would be to write your code to take advantage of a the features on a specific vendor (and part) so you get denser/faster results, maybe working in a smaller or slower and hence cheaper part. Anybody have estimates of how much each approach would save? Or how much manpower each approch takes? The first approach might be better if you have a good purchasing dept that likes playing that type of game - offload some of the work to somebody else. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 64647
John_H wrote: > Because of the "down-binning," using timing relative to the fastest speed > grade may be the "safe" way to go. > > From an earlier communication with the fine Apps folks at Xilinx: > > ] To get a path minimum, a rule of thumb is to look at the fastest speed > ] grade part for the given density and find the maximum specification in > ] the datasheet. Then a minimum should be no less than 1/4 of the maximum > ] value. > ] > ] Example: > ] You are concerned about the clock-to-out path for a CoolRunner-II 384 > ] macrocell device in a -10 speed grade. > ] > ] 1. Open the XC2C384 datasheet and look for Tco (clock to out) > ] 2. Look up Tco for the fastest speed grade (-7 is fastest in this > ] density) > ] 3. Multiply this value by 0.25 to find the minimum value for Tco > ] > ] The reason that you must use the fastest speed grade is because a part > ] may be sorted into a slow speed grade due to only one timing path not > ] meeting the faster speed requirements. As a result, 99% of the device > ] could be a faster speed grade so we must assume the part is the fastest > ] speed grade. This sounds a little skewed in the non digital logic sense ? Speed skew across a die has to be negligable, and whilst one path MAY just miss a notch as they say (even by 100ps), it will not cause a 'bump in speed' grade on other paths. A far more realistic reason is that all devices come from the same wafer, and fast/slow is largely a marketing/labeling [Price] exercise, the more so away from the very, very fastest speed grade. We've tested CPLD's with different 'speed labels', using ring osc test patterns, and found < 1% variation in supposedly widely different speed grades. If the data sheet suggests a different process/recipe, then it can get more interesting : IIRC, there is a recent coolrunner 'spin' that has worse Iq specs, in order to get faster Tpd specs A failure on that selection, can not quite be tagged slower, as that would violate Iq's. -jgArticle: 64648
Peter Alfke wrote: > Let's remember that the original question was for 256 Mbits = 32 MBytes. > That's several generations of Moore's Law away. > If you figure six transistors per memory bit (plus decoding), that > device would be getting close to 2 Billion transistors. Even the largest > FPGAs have a factor 4 fewer tightly-packed transistors, and they command > a price of >$ 1000. > > If you really need RANDOM access in 10 ns, this may be impossible today. > If there is some structure, predictability etc, then you might be able > to do it with DRAMs plus caching (???) You may also be able to throw more pins at the problem, and use multiple RAM banks to get some more bandwidth (and thus lower nett access times). Not nice to add pins, but sometimes the design dictates it ... -jgArticle: 64649
Hal Murray wrote: > > >The downside is that to do this you have to make your HDL code generic, > >not using any of the special features of either family of parts. This > >allows you to reuse the code in the next design without a lot of porting > >troubles. > > Plan 1 is that you write your code so it runs on several vendors, > and then you play them against eachother for a low price. > > Plan 2 would be to write your code to take advantage of a the > features on a specific vendor (and part) so you get denser/faster > results, maybe working in a smaller or slower and hence cheaper > part. > > Anybody have estimates of how much each approach would save? Or > how much manpower each approch takes? The first approach might > be better if you have a good purchasing dept that likes playing > that type of game - offload some of the work to somebody else. The second approach only works if you use your code in a single design. Most designers code for reuse since they often work on multiple projects with similar functions. In our case, they had many products that used the same designs, often with additions. So if the original unit used a chip from X and the next generation used a chip from A, they did not want to have to recode the optimizations. On the other hand, they often did have to code for the given chip when they added features to fielded units and needed to push the capacity.
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