Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Thank you Freidin! By the way, what is the name of the PDF document from Xilinx which explains how to use these Xilins-specific components, e.g. DCM, LUT, DLL, etc? I only know the simulation source codes from ***/src/unisims & src/simprims can provide some limited information. BesT Regards, Kelvin Philip Freidin <philip@fliptronics.com> wrote in message news:e1kvvvsr6d7h5su60k9ieika662t6fgcot@4ax.com... > On Thu, 8 Jan 2004 23:44:16 +0800, "Kelvin @ SG" <kelvin8157@hotmail.com> wrote: > >Thanks for any response...I fixed this error with "// synthesis attribute > >INIT of lut_gnd is 00" to replace defparameter. > > > >However, I don't understand why this INIT used a "8000"? How do I derive > >this 8000? > > > >Best Regards, > >Kelvin > > > >Verilog Syntax: > > > >module top (O, I0, I1, I2, I3); > >input I0, I1, I2, I3; > >output O; > > > >LUT4 U1 (.O(O), .I0(I0), .I1(I1), .I2(I2), .I3(I3)); > >// synthesis attribute INIT of U1 is "8000" > >endmodule > > The LUT is a 16 bit memory. The "8000" is a 16 bit constant. > > The 8000 is the initialization value for the 16 bit memory, > > The MSB (the bit that makes it 8000 not 0000) of the memory > is addressed by I0, I1, I2, I3 having the value 1,1,1,1 > > I.E. this constant implements a 4 input AND gate. > > The value FFFE implements a 4 input OR gate > > There are 65536 possible init values, many are interesting. > > http://www.fpga-faq.com/archives/23500.html#23505 > > > > > =================== > Philip Freidin > philip@fliptronics.com > Host for WWW.FPGA-FAQ.COMArticle: 64751
after spending a bit of time on this problem...I turned out that I had in fact not installed ModelSim from the seperate CD. Installed it and it works like a charm cheers - Kwaj "Alan Fitch" <alan.fitch@doulos.com> wrote in message news:btmjpp$3tk$1$830fa79f@news.demon.co.uk... > > "jk" <z3015094NOSPAM@student.unsw.edu.au> wrote in message > news:btltqp$8uu$1@tomahawk.unsw.edu.au... > > Hi all, > > > > trying to follow the advice of one of the regulars on this forum and > learn > > to use the text based version of ModelSim 5.7. > > > > However, using the file-find facility I have not been able to find > Vsim and > > Vlib on my installed version of Mentor Graphics on my machine. Is > this > > normal? I figured there was actually meant to be files which could > be > > accessed via the command interface... > > > > - K > > > > > > They should be there somewhere! On a PC you may have to add the path > to modelsim to your PATH variable. The vsim and vlib binaries are > normally in > > c:\program files\modelsim5.7\win32 > > and have names like vsim.exe, vlog.exe, vcom.exe > > On a unix machine, they also need to be in your path. > > What operating system are you using? > > Alan > > > -- > Alan Fitch > Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project > Services > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 > 1AW, UK > Tel: +44 (0)1425 471223 mail: > alan.fitch@doulos.com > Fax: +44 (0)1425 471573 Web: > http://www.doulos.com > > The contents of this message may contain personal views which are not > the > views of Doulos Ltd., unless specifically stated. >Article: 64752
Hi, I am sort of new to VHDL and still trying to get around the optimisation considerations associated with the language as opposed to using C. A have written a function which uses a variable 'ppos' to hold the current position in a vector. I have defined it as an INTEGER but I am beginning to think that it might be more efficient implemented in binary. Is this a real consideration in VHDL coding? Would using a binary vector in place of an integer wherever possible resort in a more efficient implementation in the long run? cheers - KingsleyArticle: 64753
Hello Adarsh, as you're new to designing with the Rocket-IOs I see why you're overwhelmed by all the attributes (I'm still 8o)...). The easiest way to get around all this is to use the Architecture Wizard (arwz.exe) that comes with the ISE-software. In this you can relatively easily specify what you want and you get a instantiation of your transceiver. As you're using Active-HDL I assume you only need VHDL instead of some binary file which is generated by the Wizard. So after running the wizard and getting the *.xaw-file let the tools generate the instantiation template and you'll get the VHDL you can instantiate into your bigger design. One thing you need to be aware: even though you're only using the transceiver as an input you still need to feed the TX-pins to the top-level. This means that you need to put "data" onto the internal parallel TX-data-pins at the MGT (can all be 0s). Also be aware that you need to supply all five clocks, even the two TX-clocks as some of the logic needed on the RX-side is clocked by TXUSRCLK and TXUSRCLK2. But you can just use RXUSRCLK(2) for those. Hope that helps. Cheers, Martin Adarsh Kumar Jain wrote: > Hi, > I am trying to use the Rocket IO transceiver as a receiver only (no clock > correction, no channel bonding, no CRC). I do need to do 8b/10b decoding. > Looking at the macro available, and from the Transceiver User Guide, there > are so many parameters and ports which need to be configured. I am new to > the Transceiver Designs and hence am not able to make out what all I need to > do. > I tried to do a simulation of a very basic design using these RocketIOs but > all i get out is XXXXs. > I am using ISE6.1SP3 and Active HDL 6.1 SP2 > Any help will be appreciated. > Thanks in advance, > Adarsh > > >Article: 64754
On Tue, 13 Jan 2004 13:49:28 +0800, "Kelvin @ SG" <kelvin8157@hotmail.com> wrote: >Thank you Freidin! You can call me Philip. >By the way, what is the name of the PDF document from Xilinx which >explains how to use these Xilins-specific components, e.g. DCM, LUT, DLL, >etc? All the primitives are documented in the Libraries Guide. Get it from: http://www.xilinx.com/support/sw_manuals/xilinx6/download/ You should also read the data sheet for the product you are using as it will give a application view of the function, whereas the the Libraries Guide is mor of a usage view. You should also look at the application notes section for in-depth info. http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=Application+Notes >I only know the simulation source codes from ***/src/unisims & src/simprims >can provide some limited information. The simulation models often can give you info that neither the data sheet or libraries guide give you, BUT, the simulation models do not tell you how the function is actually implemented. Sometimes the simulation models are incorrect (not the basic stuff, but the really complex functions). >BesT Regards, >Kelvin Enjoy, Philip =================== Philip Freidin philip@fliptronics.com Host for WWW.FPGA-FAQ.COMArticle: 64755
Hello all We have released a new version of the SPARK C-to-VHDL tool that is available on the Windows, Solaris, Linux platform and produces VHDL that is synthesizable by Xilinx XST. SPARK can be downloaded from: http://www.ics.uci.edu/~spark/download.shtml Sumit Gupta sumitg@cecs.uci.edu http://www.ics.uci.edu/~sumitgArticle: 64756
Hi @ all, I am designing an USB2.0 application and I would like to simulate the interface to an USB2.0 Transceiver. Are there simulation models available for USB2.0 Transceivers? (Cypress, SMSC...) Thank you very much. Best regards Andrés V. G&DArticle: 64757
I've published a 4-steps "recipe" on how to send traffic. The experiment should be easy to follow through. You need: 1. Any FPGA development board, with 2 free IOs and a 20 MHz clock. 2. A PC with an Ethernet card, and the TCP-IP stack installed. 3. Optionally, a network hub or switch. No Ethernet interface chip required. The Verilog source code (about 150 lines) is published here http://www.fpga4fun.com/10BASE-T0.html I'd be happy to hear how that works. The code has been tested in two different networks, with different FPGA boards from different vendors. I think the applications possible are pretty cool. Have fun! JeanArticle: 64758
Hi all, Sorry if this question is a bit too Xilinx-specific :) In the Xilinx datasheets there is a term, called the "universal delay" (tUDA) for which I cannot find a description anywhere. The problem with this one is that in the timing model there are two paths that go from the 'combinatorial logic' block to the output buffer, one directly and one traversing the tUDA block, but it doesn't seem to be documented which path is used in each particular case. When I look at the timing report produced by the ISE tools, I see that this factor has been added in the calculation of certain pad to pad propagation delays, but not for all of them. I cannot find a pattern on when is this tUDA factor added. Does someone know what is this tUDA thing and when is it used? Thanks, Guillermo RodriguezArticle: 64759
On Tue, 13 Jan 2004 08:08:22 GMT, "Jean Nicolle" <j.nicolle@sbcglobal.net> wrote: >I've published a 4-steps "recipe" on how to send traffic. The experiment >should be easy to follow through. > >You need: >1. Any FPGA development board, with 2 free IOs and a 20 MHz clock. >2. A PC with an Ethernet card, and the TCP-IP stack installed. >3. Optionally, a network hub or switch. >No Ethernet interface chip required. > >The Verilog source code (about 150 lines) is published here >http://www.fpga4fun.com/10BASE-T0.html > >I'd be happy to hear how that works. >The code has been tested in two different networks, with different FPGA >boards from different vendors. > >I think the applications possible are pretty cool. >Have fun! >Jean Hi Jean, Some suggestions: 1. This web page http://www.fpga4fun.com/10BASE-T1.html mentions that the Ethernet standard is "IEEE 802.3ae-2002". That's the 10Gbps standard! I suggest you change this to "IEEE 802.3-2002 -- Section One". Here is the direct URL: http://standards.ieee.org/getieee802/download/802.3-2002_part1.pdf Chapter 14 (10Base-T) is the relevant part of that document. 2. There is no way your circuit will meet many of the Ethernet electrical requirements (section 14.3 in the spec). Whilst it may pass data, and be of great educational value, I think you really should have a statement on your website saying that this isn't Ethernet compliant, otherwise newbies will think that it really is Ethernet and start designing it into their own products. 3. You probably do need the transformers, otherwise the section 14.3.1.1 isolation requirements of 2400V (yes, that's 2.4 kV) are a little difficult to meet. The 1kV common mode surge requirments in 14.3.1.2.7 (transmit) and 14.3.1.3.6 (receive) may also be difficult to meet without a transformer. 4. The receiver may work better with a 120ohm (or so) resistor between the RD- and RD+ pins. This should give the receiver a better return loss (which is meant to be 15dB minimum, according to 14.3.1.3.4), and might improve the performance on long cables. BTW, what error rate did you get over 100m of cable? Regards, Allan.Article: 64760
>> I don't think anyone publishes a *max* current for FPGAs. This depends >> greatly on the design and the clock speed. It even depends on the >> loading on the IO lines. But one way you can set a ceiling is to figure >> out the maximum dissipation the package can provide and assume that can >> come from either of the two supplies. The may be very conservative, but >> it will give you a *maximum*. Does that really get you a max? Suppose heat is the limiting factor on the FPGA, but I run it in a pulse mode. It's active 10% of the time, but working real hard when it's active. The length of the active burst can be long enough to cause trouble for the power supply if it's only beefy enough for the average. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 64761
Kjetil Eriksen Vistnes <kjetiler@ifi.uio.no> wrote in message news:<Pine.GSO.4.58.0401121727170.28477@geirrod.ifi.uio.no>... > I'm using the Fifo in Xilinx application note xapp258,and > the following problem occurs during Behavioral simulation: > > The last value in the queue doesn't read out. The same thing happens > if I'm > writing only one value to the queue, and sets "read_enable_in" high for > one clock cycle: No data > out. A burst read on eg. the last elements in the Fifo reads out perfectly > fine. The last element is beeing read out. > > Is it something I'm doing wrong in simulation? > Have anyone had this problem with this Fifo or know a solution to it? > > Kjetil Vistnes Not sure what the problem with the Xilinx FIFOs is, but check out the free FIFOs available on OpenCores, they are also technology independent and can be used with Altera, Xilinx and any Std. Cell process: http://www.opencores.org/projects/generic_fifos/ Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ <- FREE EDA ToolsArticle: 64762
Hi, there: I am using the bus macro for partial reconfiguration synthesis, and found this set of warnings in the maping report. Could anybody explain to me what is this type of warning and how may I correct it? Best Regards, Kelvin WARNING:MapLib:596 - Bad port net PORTTYPE, sig bus0_bm(15) WARNING:MapLib:596 - Bad port net PORTTYPE, sig bus0_bm(14) WARNING:MapLib:596 - Bad port net PORTTYPE, sig bus0_bm(13) WARNING:MapLib:596 - Bad port net PORTTYPE, sig bus0_bm(12) WARNING:MapLib:596 - Bad port net PORTTYPE, sig bus0_bm(11) WARNING:MapLib:596 - Bad port net PORTTYPE, sig bus0_bm(10) WARNING:MapLib:596 - Bad port net PORTTYPE, sig bus0_bm(9) WARNING:MapLib:596 - Bad port net PORTTYPE, sig bus0_bm(8) WARNING:MapLib:596 - Bad port net PORTTYPE, sig bus0_bm(7) WARNING:MapLib:596 - Bad port net PORTTYPE, sig bus0_bm(6) WARNING:MapLib:596 - Bad port net PORTTYPE, sig bus0_bm(5) WARNING:MapLib:596 - Bad port net PORTTYPE, sig bus0_bm(4) WARNING:MapLib:596 - Bad port net PORTTYPE, sig bus0_wire(2) WARNING:MapLib:596 - Bad port net PORTTYPE, sig bus0_wire(1) WARNING:MapLib:596 - Bad port net PORTTYPE, sig bus0_wire(0)Article: 64763
Peter Alfke <peter@xilinx.com> wrote in message news:<4002D411.A6AA3B10@xilinx.com>... > The most automatic way to design a fast multiplier is to just use the > one that exists as a hard macro ( i.e. dedicated logic) in the newer FPGAs. > I bet you cannot beat its speed... > Peter Alfke > ================== > Sleep Mode wrote: > > > > Hi all, > > > > I am trying to design a 16-bit integer multiplier in VHDL and I want to use > > a Carry-Save-Adder (CSA) tree for generating the interim subproducts > > and -then- with an additional CPA (or other) adder to add them to the final > > 32-bit product; i.e. I want to build a full-tree multiplier. > > > > My question is whether there is some automatic (core) generator for the > > CSA-tree interconnections since it is rather complicated to do it by hand... > > If not, is there any fast method of drawing it manually (pen-and-paper) so > > that I can translate it to VHDL later on? > > > > Thanks in advance guys, > > Chris Depending on your requirements (area/speed), I would build a booth 2 or booth 3 multiplier and just use '+' for addition. That would allow the synthesis tool to choose the best adder for your requirement. Of course a '*' should do almost the same, except I don't think many synthesis tools support booth 3 architectures. Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ <- FREE EDA ToolsArticle: 64764
Sleep Mode <karagiozhs@hotmail.com> wrote: : Hi all, : I am trying to design a 16-bit integer multiplier in VHDL and I want to use : a Carry-Save-Adder (CSA) tree for generating the interim subproducts : and -then- with an additional CPA (or other) adder to add them to the final : 32-bit product; i.e. I want to build a full-tree multiplier. : My question is whether there is some automatic (core) generator for the : CSA-tree interconnections since it is rather complicated to do it by hand... : If not, is there any fast method of drawing it manually (pen-and-paper) so : that I can translate it to VHDL later on? For example, XST infers a quite fast multiplier for the verilog statement assign ab = a*b; when no hardware multipliers are available or LUT style is choosen. So you don't need to care for the inner workings. Regarding Peter's proposal about using parts with hardware multipliers: They either give headaches for the Test boards, as the parts only come as fine pitch BGAs (VirtexII) or they will give you headache with getting them, as they are not yet released (Spartan III). And both Virtex II and Spatan III are no longer 5 Volt tolerant, often giving additional headache with interfacing other parts. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 64765
The timing comment was general and I did not say slower. Timing changes with process, temperature, voltage, humidity, packaging etc. The variances might be small but you are unlikely to get exactly the same timing between 2 device on 2 boards even if they come from the same batch. If you are in the area of race conditions then all these factors can make one board work and another not. As usual check the minimum and maximum timings and ensure that there are sufficient timing margin. If 10% of CPLD maximum works as a reliable minimum then timing stability can be assessed however the source device variance also needs to be checked. John Adair Enterpoint Ltd. This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Peter Alfke" <peter@xilinx.com> wrote in message news:4002D330.6747ABB4@xilinx.com... > > > guille wrote: > > Uh? That's the first time I heard about timing changing due to age > > > And hopefully you will nrvrt hear this kind of nonsense again. > Different from humans, silicon does not get slower with age, or more > tired. Doesn't get any smarter either. ;-) > It just stays the way it is, unless somebody overstresses it (mainly in > the I/O) > Peter Alfke, Xilinx > >Article: 64766
Hi, I have some troubles simulating a clkdll primitive with modelsim. I included a clkdll mapping in my VHDL project to do a clk2x and clk4x. After synthesis, all is working fine about frequency value (I have a 40 - 80 - 160 MHz). But now I have to simulate all of this with the main design. BUT how can I simulate CLKDLL without body description of the unisim library. For now, I just did a new VHDL architecture for my CLKDLL. But are there a better solution for simulation! Best Regards, Laurent Gauch ------------ And now a word from our sponsor ------------------ Do your users want the best web-email gateway? Don't let your customers drift off to free webmail services install your own web gateway! -- See http://netwinsite.com/sponsor/sponsor_webmail.htm ----Article: 64767
Hi there!
I'm getting the following error when I'm simulating with Modelsim:
# ** Error: (vsim-3341) Cannot open file "outDataFile.txt". File is
already open.
# Time: 4993405 ns Iteration: 1 Instance: /testbench/dut
Simulating the same design with NCSim works out fine. The file
"outDataFile.txt" is correctly written. But why is Modelsim refusing
this?
The following part is the code for the file I/O:
file_open (outDataFile,"outDataFile.txt" , write_mode);
for i in memory_matrix'range loop
data_file:=memory_matrix(i);
hwrite (outline,data_file);
writeline (outDataFile, outline);
end loop;
file_close (outDataFile);
I have set a breakpoint at the first line. It appears that the error
occurs already at the very first time this statement is invoked. There
is no other file_open command in the model. Why does Modelsim think
this file already open?
Thanks in advance for your help.
Henning
Article: 64768For those that are interested. A not yet finished synthesizable vhdl ARM model can be downloaded at: http://www.tamaki.de/data/vhdl.tar.gz Implemented as a Integer Unit in Gaisler Research's Leon-Soc. Note: Because I do not really know the licensing situation, download at your own risk.Article: 64769
dreamguy007@hotmail.com (Jack) wrote in message news:<b7c82826.0401111930.7714227d@posting.google.com>... > hi. i am going through software dev. tutorial that came with nios dev. > kt for cyclone and whenever i tried to run insight debugger with > byteblaster II, it always said "failed to connect. > here is the command line: > > nios-debug lcd_demo1.srec > > # [nios-gdb-server] accepting gdb connection > # [nios-gdb-server] connecting to OCI, ocibase 0x00920800 > # [nios-gdb-server] ...using byteblaster (altLPT1) > # [nios-gdb-server] mdi error: found 0 devices instead of 1 > # [nios-gdb-server] failed to connect > > I made sure the jtag cable and serial cable are connected to the right > places. > I also set the parallel port as EPP > Anyone knows what's going on? -- Hi, Looks like you probably don't have the OCI core enabled when you are compiling the NIOS core, the GDB is looking for the core and not finding it hence 'found 0 devices instead of 1'. Go to the 'Debug' tab in the NIOS CPU page of SOPC builder and ensure the OCI Debug box is ticked. Rich.Article: 64770
Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<400081BD.7090104@flukenetworks.com>... > Rene Tschaggelar wrote: > > I started reading some documents about the configuration > > devices EPCS1 & EPCS4. They appear to be programmed with a > > new download cable, the Byteblaster2. > > The Byteblaster2 claims compatibility with the previous models, > > the Byteblaster and the ByteblasterMV. Unfortunately, there > > is no schematics included in the Byteblaster2 datasheet. > > Is the 74HC244 being changed to a 74LV244 this time ? > > Byteblaster2 is a superset of MV -- more than a buffer. > But I expect that the MV can program an EPCS1. > > -- Mike Treseler -- Hi BB2 MUST be used to configure both EPCS1 and EPCS4 using the AS scheme. Cheers, Rich.Article: 64771
I use the Spartan-IIE from Xilinx BUFG ist not available for this device. What can I use instead? And how do I have to implement it in the ucf-file or in the source file (vhd-file)? Tobias.Article: 64773
Rudolf Usselmann wrote:
> Of course a '*' should do almost the same,
Yes I agree. Chris, try it and see.
> except I don't
> think many synthesis tools support booth 3 architectures.
True, but that may be a "Home Related Requirement" (HRR).
-- Mike Treseler
Article: 64774
Henning Bahr wrote:
> Hi there!
> I'm getting the following error when I'm simulating with Modelsim:
>
> # ** Error: (vsim-3341) Cannot open file "outDataFile.txt". File is
> already open.
> # Time: 4993405 ns Iteration: 1 Instance: /testbench/dut
>
> Simulating the same design with NCSim works out fine. The file
> "outDataFile.txt" is correctly written. But why is Modelsim refusing
> this?
Maybe your file declaration says "open".
-- Mike Treseler
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z