Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
check your init_b and prog_b pin. make sure they are not pulled down. "Mois?s" <m_perez_gutierre@hotmail.com> ??????:97f0ebf9.0401071711.1c536775@posting.google.com... > Hi everybody, I have been trying to configurate the Microblaze > processor in several boards, I use iMPACT and a JTAG cable to download > the bistream to the boards, but the process fails. The following is > the result message : > > --------------------------------------------------------------------- > // *** BATCH CMD : Program -p 2 > PROGRESS_START - Starting Operation. > Validating chain... > Boundary-scan chain validated successfully. > Validating chain... > Boundary-scan chain validated successfully. > '2':Programming device... > done. > INFO:iMPACT:579 - '2': Completed downloading bit file to device. > INFO:iMPACT:580 - '2':Checking done pin ....done. > '2': Programming terminated, Done did not go high. > PROGRESS_END - End Operation. > Elapsed time = 5 sec. > --------------------------------------------------------------------- > > > Somebody has experimented this error? > > or > > Somebody know what are the common causes of this? > > > Thanks in advanceArticle: 64576
When you generate a module with CoreGen, you should instantiate it(not infer it) in your code to tell the ISE you want to use it. "Tobias Möglich" <Tobias.Moeglich@gmx.net> ??????:3FFC4BC2.F86BCF11@gmx.net... > Hello, > I'm using Xilinx ISE 6.1. > I'm using the CoreGenerator for designing a dual port RAM (block RAM). > Is there an example in VHDL how to access the RAM and read the RAM? > How can I say ISE to use the generated core and not for example > distributed single port RAM or what ever he want's? > > And since I use the CoreGenerator I can say how wide port A and how wide > port B should be. (I.e : port A: 8 bit; port B: 16 bit). > ISE doesn't know at all (I suppose) that I want to use my generated core > where I already defined the width of port A and port B. > He criticizes it . > > Can someone help me? > > Tobias Möglich >Article: 64577
What does this mean in detail ??? Tobias Jay wrote: > When you generate a module with CoreGen, you should instantiate it(not infer > it) in your code to tell the ISE you want to use it. > > "Tobias Möglich" <Tobias.Moeglich@gmx.net> > ??????:3FFC4BC2.F86BCF11@gmx.net... > > Hello, > > I'm using Xilinx ISE 6.1. > > I'm using the CoreGenerator for designing a dual port RAM (block RAM). > > Is there an example in VHDL how to access the RAM and read the RAM? > > How can I say ISE to use the generated core and not for example > > distributed single port RAM or what ever he want's? > > > > And since I use the CoreGenerator I can say how wide port A and how wide > > port B should be. (I.e : port A: 8 bit; port B: 16 bit). > > ISE doesn't know at all (I suppose) that I want to use my generated core > > where I already defined the width of port A and port B. > > He criticizes it . > > > > Can someone help me? > > > > Tobias Möglich > >Article: 64578
Hello. Does anyone no where to find the older (Sept-Dez 2003) articles of this newsgroup ??? Greetings TobiasArticle: 64579
Tobias Möglich a écrit: > Hello. > > Does anyone no where to find the older (Sept-Dez 2003) articles of this > newsgroup ??? http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&group=comp.arch.fpga (with english wrapping) http://groups.google.com/groups?hl=de&lr=&ie=UTF-8&group=comp.arch.fpga (with german wrapping) -- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/Article: 64580
Anjan <anjanr@yahoo.com> wrote: : Hi : Has anybody received spartan 3? The loc distributor claims that it : hasnt been shipped. Any idea on the availability Look at the latest Spartan III datasheets (ds099-1.pdf). All devices are still marked as not released yet. From this group I expect that in the next weeks a batch of engineering samples (probaly S50/200/400/1000 ?) with get out to the distributors. Only the S50J is available (without BRAM/Multipliers). Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 64581
Hi Someone has posted this question earlier but received no response. But I will try again. Because I think this is an important issue. People must have either solved this problem by other means. Or they just enjoy copy and paste the IO pins again and again--as they get included in the upper modules. Some IO pins in the submodules can be considered "final" in a design, since they connect directly to outside the chip. Why rewirte them again and again and risk the chance of typos. Why not in the language or in the tools declared them as "final", so that when they get included in any module -- no matter how many times, they have their own constaints. This would save a lot of copy and paste and typos. Is there any reasons that this shouldn't be done? Do some people actually enjoy aggregating the IO pins again and again? Instead of focusing on the design.Article: 64582
Hi all, I have a signal that originates at a given device with known timing with respect to the rising edge of a clock: 2 ns min, 8 ns typ, 20 ns max. This signal goes through a Xilinx XCR3256XL-10 CPLD and is delayed by the internal CPLD logic. So the timing after going through the CPLD relative to clock (clock does not go through the CPLD) would be like this: tmin = 2 + min(CPLD prop. delay) ttyp = 8 + typ(CPLD prop. delay) tmax = 20 + max(CPLD prop. delay) The Xilinx datasheet specifies propagation delay in this case and for this device to be 10 ns maximum in total, including input and output buffer delays. However no minimum or typical times are given. I do understand typical times are of limited usefulness but minimum I'd need to know. Right now I can only take 0 ns as minimum but I assume there must be a better way. Does anyone know whether this data is available in any of Xilinx's white papers or ANs (haven't found anything so far) or available on demand, or can anyone suggest what's the best way to handle this case? Thanks, Guillermo RodriguezArticle: 64583
i am designing viterbi decoder. i have one problem. i am doing 3bit quantiser for quantizing the received symbols(noise addedsymbols). but my problem is from which number to which number i have to take as quantization level. either from 0 to 7 or -3 to 4. depending on those the branch metric is varying. which will give minimum metric as best metric. i am planning to calculate hamming distance. if any body have the idea on this please mail me. thank u. byeArticle: 64584
Generally you won't get minimum times. I have seen many customers fall over this aspect of CPLDs with their designs failing in the field after years of product production. Usually the timing of CPLDs change due to ageing, silicon process changes (usually faster) etc etc. Best to register signals using a high speed clock to set minimum delays use rising or falling edges as best suits your design. Alternatively you can positively skew signal timing by altering pcb trace lengths.This usually gives a fairly stable result once you have got it sorted but can be a bit of fiddle as speed down traces depends on loading. John Adair Enterpoint Ltd. This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "guille" <guillerodriguez@terra.es> wrote in message news:5d891e95.0401080116.646d069a@posting.google.com... > Hi all, > > I have a signal that originates at a given device with known timing > with respect to the rising edge of a clock: 2 ns min, 8 ns typ, 20 > ns max. > > This signal goes through a Xilinx XCR3256XL-10 CPLD and is delayed > by the internal CPLD logic. So the timing after going through the > CPLD relative to clock (clock does not go through the CPLD) would > be like this: > > tmin = 2 + min(CPLD prop. delay) > ttyp = 8 + typ(CPLD prop. delay) > tmax = 20 + max(CPLD prop. delay) > > The Xilinx datasheet specifies propagation delay in this case and > for this device to be 10 ns maximum in total, including input and > output buffer delays. However no minimum or typical times are given. > > I do understand typical times are of limited usefulness but minimum > I'd need to know. Right now I can only take 0 ns as minimum but I > assume there must be a better way. > > Does anyone know whether this data is available in any of Xilinx's > white papers or ANs (haven't found anything so far) or available on > demand, or can anyone suggest what's the best way to handle this > case? > > Thanks, > Guillermo RodriguezArticle: 64585
Hi, there: In the dynamic partial reconfiguration, what is the use of a local constant (local FAKE_VCC & FAKE_GND) in a module? Best Regards, KelvinArticle: 64586
Peter Alfke <peter@xilinx.com> wrote in message news:<3FFB529B.2EA53AE8@xilinx.com>... > Chi, we could not get through to your e-mail address. > Here is what I have been asked to forward to you through the newsgroup: > > "Chi, > Peter Alfke forwarded your request for help on CoolRunner > programming through JTAG. Can you tell me more about what > you are trying to do ( which parts, what software, cables, etc. > that you have). I run the CPLD applications group and either > someone on my team, the Configurations Solutions team, or the > hotline can give you a hand. Tell me more and I can direct the > solution. > Jesse Jenkins, Xilinx > jesse@xilinx.com " > > I need to program XCR3256XL and XC2C64 CPLDs'using an embedded controller through JTAG Test Access Port. In XAPP058 application note I have seen CoolRunner Programming Algorithm, but i need more details like how to initialize the device, how to set the device in ISP mode etc., regards, ChiArticle: 64587
chi wrote: > Peter Alfke <peter@xilinx.com> wrote in message news:<3FFB529B.2EA53AE8@xilinx.com>... > >>Chi, we could not get through to your e-mail address. >>Here is what I have been asked to forward to you through the newsgroup: >> >>"Chi, >>Peter Alfke forwarded your request for help on CoolRunner >>programming through JTAG. Can you tell me more about what >>you are trying to do ( which parts, what software, cables, etc. >>that you have). I run the CPLD applications group and either >>someone on my team, the Configurations Solutions team, or the >>hotline can give you a hand. Tell me more and I can direct the >>solution. >>Jesse Jenkins, Xilinx >>jesse@xilinx.com " >> >> > > > I need to program XCR3256XL and XC2C64 CPLDs'using an embedded > controller through JTAG Test Access Port. In XAPP058 application note > I have seen CoolRunner Programming Algorithm, but i need more details > like how to initialize the device, how to set the device in ISP mode > etc., > > regards, > Chi ISP mode is enabled by the pin called PORT_EN, just read datasheet. Laurent ------------ And now a word from our sponsor --------------------- For a secure high performance FTP using SSL/TLS encryption upgrade to SurgeFTP ---- See http://netwinsite.com/sponsor/sponsor_surgeftp.htm ----Article: 64588
Hi, group: What does this error mean? How may I fix it? I am using a Virtex-2 chip. And i am mimicing the local constant tricks the XAPP290 was doing, but somehow it doesn't work. ERROR:HDLCompilers:200 - ../../../src/iq_gen.v line 35 Target of defparam 'lut_vdd.init' does not exist ERROR:HDLCompilers:200 - ../../../src/iq_gen.v line 37 Target of defparam 'lut_gnd.init' does not exist Best Regards, Kelvin In file ../../../src/iq_gen.v wire vcc_iq, gnd_iq; LUT1 lut_vdd( .O( gnd_iq ), .I0( vcc_iq ) ); defparam lut_vdd.init = 2'b00; LUT1 lut_gnd( .O( vcc_iq ), .I0( gnd_iq ) ); defparam lut_gnd.init = 2'b11;Article: 64589
On Wed, 07 Jan 2004 10:21:46 -0800, Chris Carlen wrote: > Greetings: > > I am reading J Bhasker's "Verilog HDL Synthesis" along with "A Verilog > Primer" in order to learn not only Verilog, but how to make sure I can > model designs in a way that is synthesizable. > > What I have just learned is that the synthesis system (such as if I am > using Xilinx ISE Webpack and it's associated synthesis tools) dictates > what style must be followed, because one system might be able to > synthesize model 'A' and not 'B', whereas another system might be able > to synthesize 'B' and not 'A', even though models 'A' and 'B' are > functionally equivalent. > > Thus, this leads to the question of how to I learn about what modeling > style will be synthesizable for my particular tools? > > The text won't be able to teach me this, since it is just dealing with > the problem in general. Obviously this must be in the tooll > documentation, so I would ask: > > Is there good modeling style info in Xilinx tools so that one can learn > how to make synthesizable models for Xilinx tools reliably? > > Finally, how to VHDL and Verilog compare in terms of *inherent* > synthesizability of models, or does the same problem essentially exist > for both? > > Thanks for input. > > Good day! I've never run into anything that synthesized with Synplify and not with Precision or vice-versa. Synthesis directives are not standardized so they aren't generally portable although Precision secretly supports a small subset of Synplify directives. XST is a different story, there are lot's of things that didn't work the last time I tried it (I haven't tried the latest rev so it may have improved). Synplify has a good user's guide. If you follow it's rules you won't have any problems with any decent synthesis tool.Article: 64590
When I put some constraints of sub-modules into the top-level UCF file, (same file as the one previously I used to synthesize a full fixed chip), the ISE6.1.03 will complain for errors in NGDBuild...It is better if the software could take care of this instead of painstakingly modifying the UCF file in each subdirectory... KelvinArticle: 64591
Thanks for any response...I fixed this error with "// synthesis attribute INIT of lut_gnd is 00" to replace defparameter. However, I don't understand why this INIT used a "8000"? How do I derive this 8000? Best Regards, Kelvin Solution 1: For general information on how LUTs are initialized, please see the information regarding LUTs in the Libraries Guide at: http://support.xilinx.com/support/library.htm Verilog Syntax: module top (O, I0, I1, I2, I3); input I0, I1, I2, I3; output O; LUT4 U1 (.O(O), .I0(I0), .I1(I1), .I2(I2), .I3(I3)); // synthesis attribute INIT of U1 is "8000" endmodule "Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:btjnkq$ice$1@mawar.singnet.com.sg... > Hi, group: > > What does this error mean? How may I fix it? I am using a Virtex-2 chip. And > i am mimicing the local > constant tricks the XAPP290 was doing, but somehow it doesn't work. > > ERROR:HDLCompilers:200 - ../../../src/iq_gen.v line 35 Target of defparam > 'lut_vdd.init' does not exist > ERROR:HDLCompilers:200 - ../../../src/iq_gen.v line 37 Target of defparam > 'lut_gnd.init' does not exist > > Best Regards, > Kelvin > > > > > In file ../../../src/iq_gen.v > wire vcc_iq, gnd_iq; > > LUT1 lut_vdd( .O( gnd_iq ), .I0( vcc_iq ) ); > defparam lut_vdd.init = 2'b00; > LUT1 lut_gnd( .O( vcc_iq ), .I0( gnd_iq ) ); > defparam lut_gnd.init = 2'b11; > > >Article: 64592
Hello I'm using the core generator from Xilinx for installing a true dual port RAM But I wonder how I can handle it in the VHDL code ??? Could someone give me an advice?? This is what Iknow already: Of course I put a component in the archticture (as I did it in the example below) architecture Behavioral of dpram is component dpram port ( addra: IN std_logic_VECTOR(8 downto 0); addrb: IN std_logic_VECTOR(7 downto 0); clka: IN std_logic; clkb: IN std_logic; dina: IN std_logic_VECTOR(7 downto 0); dinb: INOUT std_logic_VECTOR(15 downto 0); douta: OUT std_logic_VECTOR(7 downto 0); doutb: OUT std_logic_VECTOR(15 downto 0); ena: IN std_logic; enb: IN std_logic; wea: IN std_logic; web: IN std_logic ); end component; begin -- Verwendung des cores (instantiation of the core) dpram_block_1 : dpram -- dpram ist der component_name; dpram_block_1 ist die Instanz port map ( addra => addra, addrb => addrb, clka => clka, clkb => clkb, dina => dina, dinb => dinb, douta => douta, doutb => doutb, ena => ena, enb => enb, wea => wea, web => web ); But how can I say where to store the values in the RAM ??? There must be something possible as described below: But if I would use this code, I would not know where in the RAM the values are stored. WRITE : process(clkb) -- Daten schreiben ins RAM (data -> ram) begin if rising_edge(clkb) then if (cs_DSP = '0' and IORW_DSP = '1') then -- Polarität prüfen -- ram(conv_integer(addrb)) <= data_b; -- von dinb in den Speicher (hoffentlich blockRAM !!) dinb <= data_b;-- after 5 ns; -- von dinb in den Speicher (hoffentlich blockRAM !!) else dinb <= (others=>'Z'); --after 3 ns; end if; end if; end process; Do you have any example code?? It would be nice if you could send it to me just to get ahead. MfG, Tobias Möglich.Article: 64593
Hi Mohan!
Thank you for your answer. It was very helpful. But I have not solved
the problem. I have written int_handler.c code to test the interrupt.
This code is placed in BRAM and there is no XMK. I have also added the
interrupt handler in my .MSS file. Now I can see both timer given
interrupt and interrupt controller given interrupt in Logic Analyzer.
The main function of the int_handler is the same as what I have added
in XMK main.c file. But when I tried to run XMK in SRAM, there is no
interrupt from timer or interrupt controller.
Available BRAM size is so small that XMK do not fit in there. I have
to try somehow to debug what goes wrong...
Any ideas?
Thanks,
Jari
mohan <mohan@xilinx.com> wrote in message news:<3FFC5AE3.DA700D8B@xilinx.com>...
> Jari,
> Your code looks mostly fine so this could be a hardware problem. Check your MHS file to see if the interrupt pin of MicroBlaze is hooked up to the interrupt controller, and the interrupt controller
> is hooked up to the timer.
> Once you begin to see the interrupts, there are a few small issues
> that should be fixed before everything works.
> 1) MAX_PROCS should be set to at least 1 more than the number of procs you specify in the table because
> there is a default system idle process that needs to be created.
> 2) you don't need to specify the interrupt handler in the MSS file. XMK always goes to the timer interupt handler
> in timer_intr.S when an interrupt occurs. After the call to the process_scheduler in that code, you will need to add code to
> ack/clear the timer interrupt. If you want to avoid assembly language programming, the simplest thing to do is to write
> all this new code as a C function and use a single assembly instruction brlid to call this C function. If you want
> to handle additional interrupts, you could replace timer_intr.S with your own code to handle the other interrupts and
> call the process scheduler as appropriate.
> All of this has been automated in the upcoming release of our software if you would rather wait for it.
> 3) if you want to modify source code for XMK, please remember to copy the entire directory from $EDK/sw/ProcessorIPLib/sw_services/xilkernel* to your project directory/sw_services/xilkernel* and do
> not modify the sources
> in your project directory/<proc_name>/libsrc/xilkernel*
> 4) The value of 100 in the timer setup code could result in too many interrupts. You might want to increase the number of cycles before an interrupt to something bigger, like 0xffff.
>
> You could also try to run everything from BRAM and see if things work correctly.
>
> Best wishes,
> Mohan
>
>
>
> Jari wrote:
> >
> > Hi!
> >
> > My question is long, but bare with me. I am using EDK 3.2 and trying
> > to get Microblaze XMK working from external memory. I have bootloader
> > in BRAM, which copies the context of FLASH memory to SRAM memory and
> > then jumps to SRAM. This context includes Xilkernel.elf and two
> > processes: Shell.elf (This is from test/arch/microblaze/Shell.c) and
> > Print.elf, which is simple "Hello World". Here is a snippet of my .MSS
> > file
> >
> > BEGIN LIBRARY
> > PARAMETER LIBRARY_NAME = xilkernel
> > PARAMETER LIBRARY_VER = 1.00.a
> > PARAMETER MAX_PROCS = 2
> > PARAMETER CONFIG_PROCESS = true
> > PARAMETER CONFIG_PROCESS_EXIT = true
> > PARAMETER CONFIG_PROCESS_KILL = true
> > PARAMETER CONFIG_PROCESS_SLEEP = true
> > PARAMETER CONFIG_PROCESS_YIELD = true
> > PARAMETER THREAD_STACK_SIZE = 0x400
> > PARAMETER PROCESS_TABLE = ( (0x80806000, 1), (0x8080A000, 2))
> > PARAMETER SCHED_TYPE = 2
> > PARAMETER CONFIG_MUTEX = true
> > PARAMETER CONFIG_SEMA = true
> > PARAMETER CONFIG_MSGQ = true
> > PARAMETER CONFIG_THREAD_SUPPORT = true
> > PARAMETER MSGQ_TABLE = ( (10, 10), (15, 15) )
> > END
> >
> > Bootloader works correctly and I have 3 .ELF files in SRAM memory. My
> > problem is how to generate the first interrupt to get the first
> > process scheduled. Like said in xilkernel_v1_00_a/src/src/sys/main.c
> > file
> >
> > * @file main.c
> > *
> > * The main routine, that starts the kernel.
> > *
> > * Enables the Interrupts and starts the timer Interrupt.
> > * Initialises the system by calling sys_init() and loops. On first
> > timer
> > * interrupt the first process gets scheduled.
> >
> > From MB_XILKERNEL part the code seems to be incomplete so I have tried
> > to add following lines to main.c file
> >
> > #ifdef MB_XILKERNEL
> > /* Enable microblaze interrupts */
> > microblaze_enable_interrupts();
> >
> > /* Start the interrupt controller */
> > XIntc_mMasterEnable(XPAR_MY_OPB_INTC_BASEADDR);
> >
> > /* Set the number of cycles the timer counts before interrupting
> > */
> > XTmrCtr_mSetLoadReg(XPAR_MY_OPB_TIMER_BASEADDR, 0, 100);
> >
> > /* Reset the timer and clear interrupts */
> > XTmrCtr_mSetControlStatusReg(XPAR_MY_OPB_TIMER_BASEADDR, 0,
> > XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK);
> >
> > /* Enable timer interrupt in the interrupt controller */
> > XIntc_mEnableIntr(XPAR_MY_OPB_INTC_BASEADDR,
> > XPAR_MY_OPB_TIMER_INTERRUPT_MASK);
> >
> > /* Start the timer */
> > XTmrCtr_mSetControlStatusReg(XPAR_MY_OPB_TIMER_BASEADDR, 0,
> > XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK |
> > XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK);
> > #endif
> >
> > I was hoping to set timer to count and give interrupt so I can get the
> > first interrupt. But I am stuck in here, end of main.c file, waiting
> > interrupt to occur.
> >
> > while(1) { /* Keep looping....*/
> > print("Hi!\r\n") ;
> > }
> > return 0 ;
> >
> > I have checked every value of these XPAR_... and XTC_... variables and
> > they are ok. I am guessing that I am missing Interrupt routine, like
> > timer_int_handler or something like that. In the same folder where
> > main.c is located there is also timer_intr.S file. If I have
> > understood correctly this should be Microblaze Xilkernel
> > timer_intr_handler? Why it is not working? What am I missing? Am I
> > trying in a wrong way to get an interrupt to occur? Should there be
> > line
> >
> > PARAMETER INT_HANDLER = timer_intr_handler, INT_PORT = Interrupt
> >
> > in my .MSS file?
> >
> > Thanks,
> > Jari
Article: 64594Hi everybosy, I was wondering whether the distributed/block selectRAM+ readback facility can be perfomed on a single block at a time, or does it have to be performed on all blocks? Similarly, can the memory configuration read back be performed in sections or does it have to be done on the whole memory? Thanks NickArticle: 64595
Existing silicon does NOT get slower due to ageing, but newer processes tend to be faster than old ones. So it is not age that matters, but rather "date of birth". Do NOT worry that your existing board might loose its speed over time... Peter Alfke, Xilinx =============== John Adair wrote: > > Generally you won't get minimum times. I have seen many customers fall over > this aspect of CPLDs with their designs failing in the field after years of > product production. Usually the timing of CPLDs change due to ageing, > silicon process changes (usually faster) etc etc. > > Best to register signals using a high speed clock to set minimum delays use > rising or falling edges as best suits your design. Alternatively you can > positively skew signal timing by altering pcb trace lengths.This usually > gives a fairly stable result once you have got it sorted but can be a bit of > fiddle as speed down traces depends on loading. > > John Adair > Enterpoint Ltd. > > This message is the personal opinion of the sender and not that necessarily > that of Enterpoint Ltd.. Readers should make their own evaluation of the > facts. No responsibility for error or inaccuracy is accepted. > > "guille" <guillerodriguez@terra.es> wrote in message > news:5d891e95.0401080116.646d069a@posting.google.com... > > Hi all, > > > > I have a signal that originates at a given device with known timing > > with respect to the rising edge of a clock: 2 ns min, 8 ns typ, 20 > > ns max. > > > > This signal goes through a Xilinx XCR3256XL-10 CPLD and is delayed > > by the internal CPLD logic. So the timing after going through the > > CPLD relative to clock (clock does not go through the CPLD) would > > be like this: > > > > tmin = 2 + min(CPLD prop. delay) > > ttyp = 8 + typ(CPLD prop. delay) > > tmax = 20 + max(CPLD prop. delay) > > > > The Xilinx datasheet specifies propagation delay in this case and > > for this device to be 10 ns maximum in total, including input and > > output buffer delays. However no minimum or typical times are given. > > > > I do understand typical times are of limited usefulness but minimum > > I'd need to know. Right now I can only take 0 ns as minimum but I > > assume there must be a better way. > > > > Does anyone know whether this data is available in any of Xilinx's > > white papers or ANs (haven't found anything so far) or available on > > demand, or can anyone suggest what's the best way to handle this > > case? > > > > Thanks, > > Guillermo RodriguezArticle: 64598
Guille, your source promises a min delay that is 10% of its max delay. You are safe in assuming a similar ratio for the CPLD. That means max 10 ns, min 1.0 ns. This seemingly ridiculously loose specification is the result of many factors: Processing tolerances including "down-binning" where the manufacturer marks a faster ( and more valuable) part as a slower speed grade, because therehappens to be more demand for that grade. Then temperature ( cold is faster) and Vcc tolerances ( high is faster). Plus additional guardband, since the min parameter is not actually tested ( the max value is ), plus a lot of tester guardband if it were tested. But 10% is a safe value, as long as you do not retrofit five years from now, when you might get surprised by a much faster part... It is always safer to design in sucha way that min delays values do not matter. You can always be sure that the min delay will never be less than zero. Peter Alfke, Xilinx guille wrote: > > Hi all, > > I have a signal that originates at a given device with known timing > with respect to the rising edge of a clock: 2 ns min, 8 ns typ, 20 > ns max. > > This signal goes through a Xilinx XCR3256XL-10 CPLD and is delayed > by the internal CPLD logic. So the timing after going through the > CPLD relative to clock (clock does not go through the CPLD) would > be like this: > > tmin = 2 + min(CPLD prop. delay) > ttyp = 8 + typ(CPLD prop. delay) > tmax = 20 + max(CPLD prop. delay) > > The Xilinx datasheet specifies propagation delay in this case and > for this device to be 10 ns maximum in total, including input and > output buffer delays. However no minimum or typical times are given. > > I do understand typical times are of limited usefulness but minimum > I'd need to know. Right now I can only take 0 ns as minimum but I > assume there must be a better way. > > Does anyone know whether this data is available in any of Xilinx's > white papers or ANs (haven't found anything so far) or available on > demand, or can anyone suggest what's the best way to handle this > case? > > Thanks, > Guillermo RodriguezArticle: 64599
I'm trying to determine if anyone makes a large/fast static RAM part. 16M (or more) x 16 bits (or more), 10ns. I can't afford the address-to-data-out latency of dynamic RAM. There are ways around this, of course, but SRAM would be so much simpler. Any ideas? Thanks, -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z