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Xilinx puts out XCell, and Altera puts out News & Views.
Xcell has a better focus on applications. There are also a
number of FPGA conferences including FPGA, FCCM, FPL and
MAPLD. The proceedings from any of these have some
worthwhile info.
Joe wrote:
> ... Thanks in advance ...
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin
Franklin, 1759
Article: 53326
Hello..
I was wondering if somone here can shed some light on an
issue with
the Xilinx ISE tools..
We have some designes that are synthisised in leonardo, and then
placed&routed with the Xilinx tools. We need to produce
post-placeandroute
timing simulation models to allow us to do some analysis on
them.. however
things do not go well..
This is the error message..
We are targeting VirtexII-1000, and using 5.1 patched to the
latest service pack..
Have tried Xilinx support but they didnt seem to keen to
talk to me...Anyone
got any ideas???
-----------------------------------------------------------------------------------------------------------------
Started process "Generate Post-Place & Route Simulation Model".
Release 5.1.03i - ngdanno F.26
Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
Command Line : E:/Xilinx/bin/nt/ngdanno.exe -quiet -s -6
-o fod_chip.nga -p
fod_chip.pcf fod_chip.ncd fod_chip.ngm
Loading device database for application ngdanno from file
"fod_chip.ncd".
"fod_chip" is an NCD, version 2.37, device xc2v1000,
package bg575, speed -6
Loading device for application ngdanno from file
'2v1000.nph' in environment
E:/Xilinx.
The STEPPING level for this design is 0.
Loading constraints from file "fod_chip.pcf"...
This application has requested the Runtime to terminate it
in an unusual way
Please contact the application's support team for more
information.
ERROR: ngdanno failed
Reason:
Completed process "Generate Post-Place & Route Simulation
Model".
-------------------------------------------------------------------------------------------------
Thanks in advance..
--
/\/\arc Kelly - mpkelly@slac.stanford.edu Tel:650-926-3761
e-Science Research Student from Bristol on LTA at SLAC.
MS 41, 2575 Sand Hill Road, Menlo Park, CA 94025
Article: 53327This posting is a bit old and still no one has replied. But in case you still need an answer, let me reply. Jens Niemann wrote: > > Hi folks, > I have a big problem with a design based on a Spartan2 FPGA. > I want to write data that is coming from a host via a USB-controller into a > SDRAM via input-FIFOS and an SDRAM-controller from Altera. > I have written a state-machine that initializes the SDRAM-controller and > waits for the Send-command from the host. > The input FIFOs are based on a model from Xilinx and use Dual Port Block-Ram > memory. > Is it right that I need 3 clocks after asserting the read-command (pop) > until data can be assigned to the input of the SDRAM-controller? > How can I handle this delay with my state machine. You need to confirm the amount of delay in the data sheet for your SDRAM. The delay depends on the speed grade of your chip and the clock speed you are running. I recommend that you go to the web sites of several SDRAM manufacturers and find all the data sheets and app notes you can. Several years ago I found a lot of info at Micron that helped me understand how this all works. There are a lot of timing issues in these parts and it can be hard to make sure you meet them all. To add delay to your state machine just add one or two "dummy" states as needed before you latch the data. Read State --> Dummy1 --> Dummy2 --> Latch Data... > The problem is that the SDRAM controller acknowledges my Write-request with > a dedicated signal and needs the FIFO-Data then 2 clocks later. > > if acknowledge='1' then > read_fifo<='1'; > nextstate<=sendstate; > else > nextstate<=currentstate > end if; > > I think something like this doesn't work. > > Any hints and tips? I can't tell for sure, but I think the acknowledge signal is from the SDRAM controller FSM and won't be generated until the data has been read from the SDRAM, no? So that should work fine. I am not sure why you are using a FIFO. If it is just to match async clocks, then you should have no problem. If you are trying to buffer a burst before sending it to the host, then you need to generate the acknowledge when all the data in the burst has been read. I designed a very similar FSM for a quad buffer a couple of years ago. If you need help let me know. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 53328
Peter, how would you do this in the following case- I have an application in which I get external clock which has to be either used as is, or divided by 2 before being used by my logic. I can use DLL to divide it, but there does not seem to be any way in Spartan 2 to change divider on a particular output of a DLL. So I still end up having to multiplex the clock, which is probably not a good idea. I suppose I can try using a jumper on external clock generator to do that instead.. Peter Alfke wrote: > > The classical well-behaved method is to use only one (global) clock, and > use a derived clock enable signal to make sure that the other part only > operates on every fourth clock cycle. > The price is slightly higher clock power consumption (provided you could > lay out the circuit such that you don't run the fast clock all over the > place). > > If you use a derived clock, then you end up with two slightly staggered > time domains, which can bite you whenever there is data exchange between > the two domains. ( The obvious loss of performance due to a late-clokced > register driving data into an early-clocked one. The more devious case > is the early-clocked register driving data into the late-clocked > register, violating hold time requirements, and creating a > race-condition mess.) > > Single clock synchronous is best in 99% of the cases... > > Peter Alfke, Xilinx Applications > =========================== > David wrote: >> >> Hi, >> I have a system divided in two parts. One is running at 256Fs and the >> other one at 64 Fs. Is it good practice to use feed the 256Fs clock into >> a counter and use the 2nd lsb to clock the second part of the circuit? In >> my digital system design class, we have always been told to NEVER clock >> components with anything else than the master clock, and use some logic >> to enable/disable those components to lower the clock rate. However, >> after searching in the newsgroup for clock divider, it seems everyone is >> using a counter as a clock divider. What is the best way to do it? >> Thanks >> DavidArticle: 53329
> > Nowadays, passive components are little flecks of ceramic with solder > > pads at each end, small ICs come in tiny flat-packs with centipede > > fringes of legs around, and the interesting ones come either in large > > flat-packs with centipede fringes, or in BGA form. And I presume the > > signal-integrity requirements are such that bread-board, and even the > > two-layer PCB, are Right Out. The BBC Micro and the ISA slot have > > gone the way of the dinosaur; the parallel port is dying out. Um, folks? Just because some components are available in these forms, doesn't force you to use them! Even if there are elitists in this group that threaten to call you names if you don't! Components are still available in the old forms, if you're doing a project like people used to, there's no crime in using components that are easier to handle !! -StanArticle: 53330
You want to read Xilnx's XAPP174 (http://www.xilinx.com/xapp/xapp174.pdf) and then you will want to download the source code for it at (ftp://ftp.com.xilinx/pub/applications/xapp/xapp174.zip). I think there is enough there to get the div by 4 done. Alex :) "David" <gretzteam@hotmail.com> wrote in message news:0D8ba.24041$_P4.351901@wagner.videotron.net... > Hi, > I am using a SpartanIIE device (300k gates). There are 4 DLLs inside the > chip and it really seems to do what I want. However, I can't find a way to > use them. I'm using the ISE webpack, and the architecture wizard only > generates vhdl code for virtex device. I only need a 'divide by 4' DLL but > there is no tutorial anywhere on how to use them.Article: 53331
Hi guys, We are running into more problems with digikey's d2e board and microblaze combination. We are trying to put microblaze on Digilent's spartan 2e board (with XPS EDK3.1) but are running into problems. Everything compiled (with basic stuff, uBlaze CPU, block ram+ctrler and uart) and we got it to download to the board. But nothing happened afterwards, We think it may be that the uart is not configured properly. We flipped through everything we can find on the web regarding what could've gone wrong. But the literature on that is rather slim. Do any of you out there have any previous experience with this? Where can we find a tutorial that actually works, we are beginners in FPGA based CPU core implementations, so please bear with us. Thanks, Junyi Ling, jling@cs.tamu.eduArticle: 53332
Who has used one of these and what are your experiences? Yours Bram ================================================== Bram van de Kerkhof OCE-Technologies BV Building 3N38 St. Urbanusweg 43, Venlo, The Netherlands P.O. Box 101, 5900 MA Venlo ================================================== Direct dial : +31-77-359 2148 Fax : +31-77-359 5473 ================================================== e-mail : mailto:bvdk@oce.nl ================================================== www : http://www.oce.nl/ ==================================================Article: 53333
hi,
I am now trying to generate three clock to activate the CODEC IC (AK4520A)
in Xilinx FPGA board (XV800). Because I can only have one external clock and
I need to create three other clocks, I use the following way.
1. Set a 8-bit counter
2. make mclk=clk, sclk=counter[1], and lrck=counter[7];
3. pass these three device to Audio IC.
I have a simple controller to feed the data to Audio IC by using BRAM. The
flow is as follow:
Controller-->BRAM-->Audio IC
In BRAM, I use two clocks, which are mclk and sclk respectively. mclk is
used for receiving, while sclk is used for transmit. All the above three
clocks are also fed to Audio IC.
In timing-simulation, everything is ok. However, when I try to download it
and use logic analyzer to trace the signal, sclk is kept in "0" forever.
Although mclk is activated, it doesn't activate the controller such that the
controller is always kept in the initial state.
Should I put buffer for both of them? I try to put BUFG or BUFGP for sclk,
but it cannot be downloaded to the FPGA board because sclk is locally
generated.
Do you guys have any idea about how to implement it?
Thanks,
Mike
Article: 53334Padraig FitzGerald wrote: > > Hi, > > I was wondering if anybody had come accross this problem when using Xilinx > FPGA's and if so do they know how to solve it. > > I have just recieved a PCB design back from FAB and We are having an issue > with a short between the VCC and GND planes. This however only occurs when the > Xilinx Spartan XL XCS30 is populated on the board, ie the short is finding > it's way through the silicon of the FPGA. Hi We had a similar problem with a BGA package. It seems that it was a solder bridge somewhere under the chip. NicolasArticle: 53335
Hi, I have been looking through the articles and are interested if anyone has tried from the opensource systemc to fpga using all opensource software. I personally am interested and can't afford a big layout just for fun. I use linux at home and work so would be looking for linux software preferably. Although I can get access to Windows. Any help would be appreciateArticle: 53336
Hello Thorsten,
> Xilinx provides a nice app note which describes you problem (Power on
surge)
> and gives an advices how to deal with it.
> Xilinx app notes 450 (Power-On requirements for the Spartan II and Spartan
> IIe famlies)
> and 451 (Power Assist circuits for the Spartan II and Spartan IIe
families)
>
Thanks for the information. These app notes describe the problem in detail.
Would be nice if these information is available for the Altera FPGAs.
Just Power Assist circuits look for me like a little work around. I've found
a solution ('work around') for my board: Adding some 'charge' from the 3.3V
over two diodes to the 1.5V to help the drop-down regulator to start up.
If there is interest in some oscilloscop pictures about the problem and an
equivilant circuit to test your power supply for Cyclone devices I can write
a summary on my web site.
Martin
> "Martin Schoeberl" <martin.schoeberl@chello.at> schrieb im Newsbeitrag
> news:TP5aa.79536$AV5.998926@news.chello.at...
> > I've built a board with the Cyclone from Altera. First board was ok, but
> on
> > some of the following there was a problem with startup of the Cyclon.
> >
> > For the core voltage (1.5V) I use a drop-down regulator from Linear
> > Technology (LTC3405) as described in the app. note (AN257). But the core
> > voltage did not reach the 1.5V. The regulator stopped at 0.5 - 0.8 V. I
> > examined the problem by building an extern regulator.
> >
> > Starting the regulator without load and than attaching the VCCINT pins
> from
> > the FPGA leads to a successfull start. The output capacitor (4u7)
supplies
> > enough initial current.
> >
> > Measuring the current during startup yields to following results:
> > First few us the Cyclone needs about 0.7A! Falling down to 200 mA and
> > staying there for about 15 us (I think for internal startup). After that
> it
> > dropps to a few mA.
> > The LCT3405 is a 300 mA regulator with a peak current of about 650 mA.
It
> > can not deliver this peak current during it's own start.
> >
> > Just wanted to tell this story (of hidden problems of a new family) for
> > others who want to work with this new (still exciting) FPGAs to not run
> into
> > the same troubles.
> >
> > Martin Schoeberl
> >
> >
>
>
Article: 53337Martin Schoeberl <martin.schoeberl@chello.at> wrote: > Hello Thorsten, > If there is interest in some oscilloscop pictures about the problem and an > equivilant circuit to test your power supply for Cyclone devices I can write > a summary on my web site. Of course there is interest :-) We are planning to use Cyclones in new designs Roman > MartinArticle: 53338
Hello Mr. Kevin, I am very greatful for your feedback. I actually have to give a seminar about PCI specification to my BOSS, so those question. Sir i need your support in design my PCI target core. I am starting configuration code from tomorrow.I have one more doubt A buffer is required in the target PCI which i am design. If prefetching is used how many byte should i prefetch ? Is it length of my buffer? Should i prefetch during burst read? Thanking in advance waiting for your reply praveenArticle: 53339
Also, don't forget that if you are going to simply truncate, you should add one half of the LSB (after truncation) to the value before truncation. Otherwise, you will obtain what is called truncation error where the average of your output will be shifted one half LSB of your truncated value. noddy > Ken Chapman <chapman@xilinx.com> wrote in message news:<3E64B9D9.5B894EC6@xilinx.com>... > > Dear Basuki, > > > > The safe answer is just to keep the most significant bits. However, you may well be wasting dynamic range by doing this. > > > > The best is to calculate the output saturation level. This is the maximum level the output can reach based on the actual coefficients you have used, many of which will relatively small numbers. In this way you can often discard one or more of the MSBs which are not really used and maintain higher precision by keeping some LSBs. > > > > Needless to say this is covered on the Xilinx DSP Techniques Course which I authored :-) > > > > Yours sincerely, > > > > Ken Chapman > > > Dear Basuki, > I use: > clip_and_amplify : process( s ) > begin > case s( s'high downto s'high - 3 ) is > when B"0000" | B"1111" => > s_out <= s( s'high - 2 downto s'high - 2 - 15 ) ; > when others => > s_out <= ( s( s'high ), others => not s( s'high ) ) ; > end case ; > end process ; > to clip and amplify a signal s of arbitrary width to an output s_out > of 16 bits. Both signals are signed signals. > > Henk van Kampen > www.mediatronix.comArticle: 53340
ray & jim thank you for the helpful information, in fact Maxim has a part which will work great in a tiny micro sop package which will be surface mounted on the back of the board under the max part CB On Mon, 10 Mar 2003 20:33:59 GMT, charleybrant@hotmail.com (CB) wrote: >I'm sure this is a real newbie question, I am using an altera >max7032A and I need a real cheap, very tiny clock to run some internal >counters, it does need to be reasonably freq stable since I am >counting time, KHz to low MHz is fine > >what is the easiest way , i would prefer not use use an external >clock chip as it is big and almost as much as the 7032, can I just >hang an external crystal, perhaps one of the tiny 32khz jobbies across >two pins and build a little osc out of an internal inverting funtions, > >please explain how to do this, sorry if this question is dumb but I >can't find any examples on the net > >CB > > >Article: 53341
Nicholas C. Weaver wrote: > FCCM: (IEEE Symposium on Field-Programmable Custom Computing Machines) > > FPL: (International Conference on Field Programmable Logic and > Applications) Still on the research front: IEEE Design and Test has had some useful papers in recent years, too. I think I've read a range from a tutorial on FPGA structure (CLBs, LUTs etc) to papers on dynamically reconfigurable processing. Obviously, from the title, it's not strictly related to FPGAs per se. (Thinking of reconfigurable processing, there are papers from the Reconfigurable Architectures Workshops (part of IPDPS) that are worth looking at: http://www.ece.lsu.edu/vaidy/raw03/, look for the archives link on http://www.ipdps.org/index.html ) MartinArticle: 53342
Hi, we are using Xilinx DDR registers for clock forwarding. Works nice. Hakon Lislebo "Bram van de Kerkhof" <bvdk@oce.nl> wrote in message news:1047367580.628422@news-ext.oce.nl... > Who has used one of these and what are your experiences? > > Yours Bram > > > ================================================== > Bram van de Kerkhof > > OCE-Technologies BV > Building 3N38 > > St. Urbanusweg 43, > Venlo, The Netherlands > P.O. Box 101, 5900 MA Venlo > ================================================== > Direct dial : +31-77-359 2148 > Fax : +31-77-359 5473 > ================================================== > e-mail : mailto:bvdk@oce.nl > ================================================== > www : http://www.oce.nl/ > ================================================== > > >Article: 53343
Martin,
Although xapp450 and 451 apply to Spartan II and IIE (and to Virtex and Virtex
E) and have been tested with them, I would caution anyone from assuming that any
other FPGA has a similar power up profile and has a similar solution......as you
would have to exactly copy it to get the same behavior.
We can check that a corner lot of extreme process variations will operate
properly over voltage and temperature, wheras trying one of these circuits out
with one part (or even one whole lot of identical parts) is a recipe for
disaster.
Since we have eliminated the power on current in all subsequent designs, (Virtex
II, II Pro, ....) we are not as concerned with solutions to this problem.
But since you mention the diode feed forward solution, I would like to see the
scope shots, as it is quite clever. It might be something we consider adding to
xapp451.
austin@xilinx.com
Austin
Martin Schoeberl wrote:
> Hello Thorsten,
>
> > Xilinx provides a nice app note which describes you problem (Power on
> surge)
> > and gives an advices how to deal with it.
> > Xilinx app notes 450 (Power-On requirements for the Spartan II and Spartan
> > IIe famlies)
> > and 451 (Power Assist circuits for the Spartan II and Spartan IIe
> families)
> >
> Thanks for the information. These app notes describe the problem in detail.
> Would be nice if these information is available for the Altera FPGAs.
>
> Just Power Assist circuits look for me like a little work around. I've found
> a solution ('work around') for my board: Adding some 'charge' from the 3.3V
> over two diodes to the 1.5V to help the drop-down regulator to start up.
>
> If there is interest in some oscilloscop pictures about the problem and an
> equivilant circuit to test your power supply for Cyclone devices I can write
> a summary on my web site.
>
> Martin
>
> > "Martin Schoeberl" <martin.schoeberl@chello.at> schrieb im Newsbeitrag
> > news:TP5aa.79536$AV5.998926@news.chello.at...
> > > I've built a board with the Cyclone from Altera. First board was ok, but
> > on
> > > some of the following there was a problem with startup of the Cyclon.
> > >
> > > For the core voltage (1.5V) I use a drop-down regulator from Linear
> > > Technology (LTC3405) as described in the app. note (AN257). But the core
> > > voltage did not reach the 1.5V. The regulator stopped at 0.5 - 0.8 V. I
> > > examined the problem by building an extern regulator.
> > >
> > > Starting the regulator without load and than attaching the VCCINT pins
> > from
> > > the FPGA leads to a successfull start. The output capacitor (4u7)
> supplies
> > > enough initial current.
> > >
> > > Measuring the current during startup yields to following results:
> > > First few us the Cyclone needs about 0.7A! Falling down to 200 mA and
> > > staying there for about 15 us (I think for internal startup). After that
> > it
> > > dropps to a few mA.
> > > The LCT3405 is a 300 mA regulator with a peak current of about 650 mA.
> It
> > > can not deliver this peak current during it's own start.
> > >
> > > Just wanted to tell this story (of hidden problems of a new family) for
> > > others who want to work with this new (still exciting) FPGAs to not run
> > into
> > > the same troubles.
> > >
> > > Martin Schoeberl
> > >
> > >
> >
> >
Article: 53344Igor Orlovich wrote: > how would you do this in the following case- I have an application in which > I get external clock which has to be either used as is, or divided by 2 > before being used by my logic. Consider using the fast clock and a clock enable signal for all your logic. In one case, ce is active. In the other case the ce toggles at the divided by 2 rate. -- Mike TreselerArticle: 53345
Hi all, Could people recommend a good text that meets these requirements, please: 1) Describes doing arithmetic in logic, 2) with HDL examples, preferably, 3) that describes varying levels of optimisation (e.g. divider area/speed trade offs, and the various types of adder optimisations) and, more difficult, 4) how these functions could/should be realised for given types of technology (e.g. how carry chains are done in FPGAs (typically), and why carry saves wont help). 5) comments on combining hardware in an ALU to get more functions in less area (a Steve Furber book describes separating a single ALU (ARM2) into separate units for logic and arithmetic (later ARM)). I have a decent Comp Sci degree, and have read some amount of logic design texts, so ideally something that wont waste my time with the truth table for a NAND gate. :o) There's a web based arithmetic generator (hiding somewhere in my bookmarks, hmm, can't find) - I'd like to be able to understand the options to this too (Wallace trees, and the like). A little on asynchronous arithmetic a bonus (though I'm not very fussed about this at the moment). Sorry if this looks a bit 'please do my homework', but I really don't know where to start with this. Cheers Martin Ellis PS. Brownie points for HDL models of an ARM-style barrel shifter *with an explanation* :o)Article: 53346
Do a chip level simulation of your design and see if the follwing are happening: OPB bus reset signal is valid for 16 clock cycles, soon after time zero. MicroBlaze program counter is counting. If neither of the above are happening, you probably have a problem with the way the reset signals are connected (i.e. polarity, destination) in the MHS file. The reset signal can not be connected to VCC or GND internal to the MHS, and a power on pulse generator is required to properly reset the processor and OPB bus, if power up reset is required without an IO pin (Xilinx may have fixed this). A good forum for getting answers to MicroBlaze questions is on the Xilinx web site: http://toolbox.xilinx.com/cgi-bin/forum?14@@/Embedded%20Processors Regards, Erik Widding. --- Birger Engineering, Inc. -------------------------------- 617.695.9233 100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.com "Gaga" <blah@blah.org> wrote in message news:b4jvqn$u0$1@news.tamu.edu... > Hi guys, > > We are running into more problems with digikey's d2e board and microblaze > combination. We are trying to put microblaze on Digilent's spartan 2e board > (with XPS EDK3.1) but are running into problems. Everything compiled (with > basic stuff, uBlaze CPU, block ram+ctrler and uart) and we got it to > download to the board. But nothing happened afterwards, We think it may be > that the uart is not configured properly. We flipped through everything we > can find on the web regarding what could've gone wrong. But the literature > on that is rather slim. Do any of you out there have any previous experience > with this? Where can we find a tutorial that actually works, we are > beginners in FPGA based CPU core implementations, so please bear with us. > Thanks, > > Junyi Ling, > jling@cs.tamu.edu > >Article: 53347
Ray Andraka's web page has a very good list of hardware oriented math texts: http://www.andraka.com (we own many of these books, and thank Ray greatly for making us aware of them) Regards, Erik Widding. --- Birger Engineering, Inc. -------------------------------- 617.695.9233 100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.com <m a ellis> wrote in message news:b4l7kc$hdp$1@ucsnew1.ncl.ac.uk... > > Hi all, > > Could people recommend a good text that meets these requirements, please: > > 1) Describes doing arithmetic in logic, > 2) with HDL examples, preferably, > 3) that describes varying levels of optimisation (e.g. divider area/speed > trade offs, and the various types of adder optimisations) > > and, more difficult, > > 4) how these functions could/should be realised for given types of > technology (e.g. how carry chains are done in FPGAs (typically), and why > carry saves wont help). > 5) comments on combining hardware in an ALU to get more functions in less > area (a Steve Furber book describes separating a single ALU (ARM2) into > separate units for logic and arithmetic (later ARM)). > > I have a decent Comp Sci degree, and have read some amount of logic design > texts, so ideally something that wont waste my time with the truth table > for a NAND gate. :o) > > There's a web based arithmetic generator (hiding somewhere in my bookmarks, > hmm, can't find) - I'd like to be able to understand the options to this > too (Wallace trees, and the like). > > A little on asynchronous arithmetic a bonus (though I'm not very fussed > about this at the moment). > > Sorry if this looks a bit 'please do my homework', but I really don't know > where to start with this. > > > Cheers > Martin Ellis > > > > PS. Brownie points for HDL models of an ARM-style barrel shifter *with an > explanation* :o) >Article: 53348
Brian, > The message does not give me enough to go on to tell you what the > problem is but I can give you some suggestions to help debug the > problem. First take a look at the ngdanno report file. Doing this on the original I just get the same message that the Project Navigator shows.. I actually found this file by accident the other day in the hope it would hold more info. > ngdanno.exe -o fod_chip.nga fod_chip.ncd fod_chip.ngm Trying this it still loads the pcf file, resulting in the same failure, I have renamed the pcf file, and it no longer loads it.. However the same error occours and things die.. > If that does not work, try omitting the ngm file: This has worked, and nga2vhdl successfully wrote out the vhdl. Disabling the flag in the project navigator also works, and things get written. Thanks for that... Presumably there is some issue with the hierarchy in the design? What sort of impact does this have? We are currently setting preserve hierarchy to make it easier to compare to the pre-synthisised simulation, and to make things more modular.. -- /\/\arc Kelly - mpkelly@slac.stanford.edu Tel:650-926-3761 e-Science Research Student from Bristol on LTA at SLAC. MS 41, 2575 Sand Hill Road, Menlo Park, CA 94025Article: 53349
jlade@avant.com.tw (Jason Lade) wrote in message news:<cee8de0c.0303110123.65692e00@posting.google.com>... > Hi, > > I have been looking through the articles and are interested if anyone > has tried from the opensource systemc to fpga using all opensource > software. I personally am interested and can't afford a big layout > just for fun. > > I use linux at home and work so would be looking for linux software > preferably. Although I can get access to Windows. > > Any help would be appreciate Haven't seen much SystemC here either, its not really for FPGAs although it could be used to model but not implement them. AFAIK SystemC simulation tools may be free, but you would still need to PAY big $ for synthesis. If you are really a SystemC fan, you wouldn't be so concerned about final target details. SystemC has been popular with the big Telcos. Also there are a few SystemC groups, check systemc.org & Synopsys.com sites. Look for CoCentric, note that it synthesizes to Verilog or VHDL, so now you need 2 big $ tools. It is a Behavioral Synthesis tool, this market has been slow to take of in ASICs because the EEs don't buy into it. The Behavioral Synthesis tools are really for CS programmers and "in a hurry" system EEs. See also HandelC, also not free. A google on "FPGA systemc" produces little to suggest anyone uses systemc for FPGA If you want to work on or program FPGAs, you are better off with Verilog, VHDL, or even schematics and quite a bit of it is free if your demands are entry level upto say 100K system gates. SystemC is part of the "lets throw away all the HDL tools away that we know & replace with free C tools" mantra. Only the new C tools are not free either and quite clumsy. This may be ok for system modelling where the HDLs were not well suited in the 1st place, but SystemC is not well suited to detailed HW design. Look to see how many C companies have survived the disinterest of ASIC designer, almost none. My own preference is to write in RTL Verilog and compile back to C for simulation purposes, one source gives both fast simulation C code for SW modelling & straightforward synthesis to HW. This is the opposite view of starting in C, been there done that. Others will model in C and link through the Verilog PLI interface. Can't say about VHDL-C.
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