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Hi, I am learning WebPACK ISE 4.2i on a WinME OS. Several problems cannot resolved. The first one: When I try exec ModelSim Simulator for the test vector jc_tb.vhd, for the "Simulate Behavioral VHDL Model", the following warning output. # WARNING[10]: jc_tb.vhd(23): Using 1076-1987 syntax for file declaration. 21: -- If you get a compiler error on the following line, 22: -- from the menu do Options->Configuration select VHDL 93 23: FILE RESULTS: TEXT IS OUT "results.txt"; I don't know where "the menu do Options" is. It means Project Navigator? This warning should be cared, or not? The second problem: When I continue to run the"Simulate Post-Place & Route VHDL Model", the following errors encountered. # ERROR: jc.vhd(28): Subprogram "=" is ambiguous. Suitable definitions exist in package 'std_logic_1164' and 'std_logic_unsigned'. # ERROR: jc.vhd(28): (Use the '-explicit' option to disable the previous error check) # ERROR: jc.vhd(62): VHDL Compiler exiting # ERROR: D:/MODELTECH_XE/WIN32XOEM/vcom failed. How to resolve it? Thanks in advance WebPACK Tutorial: Spartan-II/VHDL: jc2_vhd_f\jc_vhd.npl-[jc_tb]Article: 51001
Hi all, If you are interested in getting lot of free hardware designs and design tools visit http://www.opencores.org/OIPC/projects/OpenTech/ Regards, Jamil Khatib Opencores.orgArticle: 51002
Lyndon Amsdon wrote: > Hi Rene, > > >>Quartus is the successor of MaxPlus2.Future development is put into >>Quartus. It is also somewhat more intuitive in most aspects. >>So if possible use Quartus. > > > Thanks, I read somewhere else that this was true, means I don't have > to download again as 100 megabytes on a 56k modem is a fair amount! I'd assume the local Altera distributor will send you a CD with the latest Web edition on it. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 51003
Hi all, I asked this before but received no reply. This is another attempt... I was wondering if anyone has successfully implemented a IEEE1394 LLC in a FPGA? I would like to know how much work it is and how much resources does it require from the FPGA? I will appreciate any input on this matter. Thanks, /Mikhail P.S. Should you want to respond to me directly, please delete the spam block from my email address. ---Outgoing mail is certified Virus Free.Checked by AVG anti-virus system (http://www.grisoft.com).Version: 6.0.431 / Virus Database: 242 - Release Date: 17/12/2002Article: 51004
Lyndon Amsdon ha scritto nel messaggio <1a7d6495.0212241531.4a7bb7bb@posting.google.com>... >Hi, > >I have just bought some EPM7064LC84-7 and made a JTAG lead also. >Which software is better? Lyndon, I use both Quartus and Max+Plus, and for small CPLD projects I prefer MAX+Plus. However I'm afraid you can't program EPM7064LC84-7 with JTAG cable because it is not in system programmable. If I remember exactly, the in system programmable feature is present only in MAX7000AE, B and S series. But the MAX7000 serie requires an dedicated programmer. Check the data sheets. Regards. Luigi FunesArticle: 51005
On Tue, 24 Dec 2002 21:20:43 -0500, "Theron Hicks (Terry)" <hicksthe@egr.msu.edu> wrote: >In this case, I am pretty sure the problem is the EMI, as when I mechanically remove >the fan from the system by damping it's vibrations out with my hand, the noise level >did not change. I would expect a similar level of acoustic "buzz" with the fan stopped, but not identical and with a different spectrum. So if it didn't change at all, that's fairly conclusive. >> Or maybe this will help! >> http://users.moscow.com/oiseming/lc_ant_p/pic_Prj1.htm >> :-) >> >> - Brian > >Humm... run the cooling fan of from the excess heat generated via the electrical >load. (For those who weren't familiar with this link, it discusses a Stirling engine >powered fan.) I suspect it is not practical but it would make a slick solution. I seriously doubt you could use the waste heat ... but a non-electrical power source would be one solution. Or remotely power it, either belt drive or ducting. >Are you a member of that particular antique engine club? No, but Stirling engines have intriguing possibilities. I built one that would sit on the central heating radiator and run happily on ice cubes. Not very impressive as they go (a good one will run from the heat of your hand) but that was before I had machine tools... Merry Christmas! - BrianArticle: 51006
Hai, I would like to know any free FGPA(lut based) cores available on net!! (any architecure!) (VHDL/Verilog RTL/Netlist) Also,I would like to know some comparision of Varicore with any of the xilinx Xc4000/vertex device in performance? http://www.actel.com/varicore/index3.html Thanks, Dasari.Article: 51007
Matthew Campbell wrote:
>
> I recently picked up a altera FlexEPF 10k100 pci card for about $20 at
> an auction so I wanted to get into fpga dev, is there any freeware or
> cheap software to program the fpga and what are some good books to get
> started with fpgas for someone with a programming background ?
Matthew,
The difficulty of getting your Altera device-based PCI card to work will
depend on how the card is set up.
Does the PCI card have a PCI bridge chip made by PLX or AMCC in between
FLEX10K?
If so, then all you have to worry about is the protocol of the bridge
chip local bus.
Download datasheets from them, and study the local bus protocol.
However, if FLEX10K is directly connected to the PCI, now you have to
obtain a PCI IP (Intellectual Property) core (Consider a PCI IP core as
a black box between the PCI interface and your backend logic you are
going to implement.) from somewhere or develop your own PCI IP core.
From my experience of developing a PCI IP core, and porting my PCI IP
core to Xilinx and Altera, it is a lot harder to get the PCI IP core
working with Altera than with Xilinx.
Another thing to consider is the type of chip you got.
Is the FLEX10K you are talking about FLEX10K, FLEX10KA, or FLEX10KE?
If the chip you are dealing with is not FLEX10KE (EPF10K100E), I believe
you need to pay $2,000 for a paid version of Altera software.
If the chip you got is FLEX10KE, than you can use free Quartus II Web
Edition, but the free tool's simulation environment is pretty miserable
(Waveform simulator only and no free "crippled" HDL simulator like
Xilinx.).
To do anything useful with an FPGA, you need to learn HDL
(Hardware Description Language) like Verilog or VHDL.
If you are new to HDL, I recommend that you learn Verilog because the
language is simpler than VHDL.
However, the problem is that almost all HDL books I have seen so far do
a very job of explaining how to design anything useful with HDL.
Especially books sold at major booksellers like Borders or Barnes &
Noble are really bad.
I am pretty sure that there are many many people (Probably in the
thousands.) who have purchased HDL books from those booksellers hoping
to develop something useful using HDL, but quit because books the books
never really explained how to do it in detail.
I almost became one of those people who quit (In fact, I gave up
studying Verilog at one point because a Verilog book I bought was so
poorly written. By the way, this book is still sold at Borders.), but I
was fortunate enough not to become one of them.
Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)
Article: 51008"Jeff" <dsfdsaf@hotmail.com> wrote in message news:<zPoO9.3378$%R6.178581@news20.bellglobal.com>... > Hi, > I am learning WebPACK ISE 4.2i on a WinME OS. Several problems cannot > resolved. > > The first one: > When I try exec ModelSim Simulator for the test vector jc_tb.vhd, for the > "Simulate Behavioral VHDL Model", the following warning output. > # WARNING[10]: jc_tb.vhd(23): Using 1076-1987 syntax for file declaration. > > 21: -- If you get a compiler error on the following line, > 22: -- from the menu do Options->Configuration select VHDL 93 > 23: FILE RESULTS: TEXT IS OUT "results.txt"; > > I don't know where "the menu do Options" is. It means Project Navigator? > This warning should be cared, or not? There is a simpler way out buddy.. In your compile macro(.do file) where you cmopile all the files just add a -93 switch option to the vcom command. Or type this command directly at the modelsim prompt. e.g. vcom -93 jc_tb.vhd With this you are making sure your design is compiled with the 1993 language syntax. 83 does not support the file i/o in the form you wrote in the file. Or for a more elgant solution if you code in 93 styntax would be to set the default syntax to 93.. For that go to Options->Compile-> in the popup window check "Use 1993 syntax for compiling". > > The second problem: > When I continue to run the"Simulate Post-Place & Route VHDL Model", the > following errors encountered. > > # ERROR: jc.vhd(28): Subprogram "=" is ambiguous. Suitable definitions exist > in package 'std_logic_1164' and 'std_logic_unsigned'. > # ERROR: jc.vhd(28): (Use the '-explicit' option to disable the previous > error check) > # ERROR: jc.vhd(62): VHDL Compiler exiting > # ERROR: D:/MODELTECH_XE/WIN32XOEM/vcom failed. > > How to resolve it? this too is kindaa same.. in your compilation macro add the following line or directly type:- vcom -explicit jc.vhd that should take care of the problem. regards, Nachiket Kapre Design Engineer Paxonet Communications Inc.Article: 51009
[How to connect FPGA to system] > .... As Kevin mentioned, PCI IP is a lot more complicated than the >good old ISA days. When I asked something about PCI a week or two ago, several people suggested chips by PLX. They go PCI to xxx where xxx is a lot easier to interface to. Some versions probably have a few GPIO pins that could be used to load the config bits into the FPGA, thus avoiding the ROM. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 51010
hi, is there a non-FLI based mechanism of probing the interal state of a Modlesim simulation? Since the msim kernel is implemented using TCL, can we do it through Tcl? regards Nachiket Kapre Design Engineer Paxonet Communications Inc.Article: 51011
dasariware@yahoo.com (dasari) wrote in message news:<e1df9052.0212251805.10648805@posting.google.com>... > Hai, > > I would like to know any free FGPA(lut based) cores available on net!! > (any architecure!) (VHDL/Verilog RTL/Netlist) > > Also,I would like to know some comparision of Varicore with any of the > xilinx Xc4000/vertex device in performance? > http://www.actel.com/varicore/index3.html > > > > Thanks, > Dasari. Try www.opencores.org - this is probably the largest and best selection of free soft IP cores around. My company has also a reference page of the free IP cores we have contributed to opencores: www.asics.ws. And of course the FPGA manufacturers (e.g. XILINX and Altera) have a large collection of examples that include soft IP cores. There are many, many more, do a search ... Cheers, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - NEW ! 4 New Free IP Cores this months (so far :*) FREE IP Cores --> http://www.asics.ws/ <--- ----- ALL SPAM forwarded to: UCE@FTC.GOV -----Article: 51012
i agree , epm7064 is made of rom,Not ram, it is not in system programmble. But you can put up the circuit to programme it. as to Software , i prefer maxplus ,too,It is easy to use . Quartus is powerful , just owing to what you do here > I use both Quartus and Max+Plus, and for small CPLD projects > I prefer MAX+Plus. > However I'm afraid you can't program EPM7064LC84-7 with JTAG > cable because it is not in system programmable. > If I remember exactly, the in system programmable feature is present > only in MAX7000AE, B and S series. But the MAX7000 serie requires > an dedicated programmer. Check the data sheets. > Regards. > > Luigi FunesArticle: 51013
Hi Luigi, > However I'm afraid you can't program EPM7064LC84-7 with JTAG > cable because it is not in system programmable. > If I remember exactly, the in system programmable feature is present > only in MAX7000AE, B and S series. But the MAX7000 serie requires > an dedicated programmer. Hi, you're right. I orignally thought before I bought them that if it was 5v device then it would be S series, but it is just plain MAX7000. This hobby is so expensive, would the scheamtics of a programmer be available or is it quite complicated? Thanks, LyndonArticle: 51014
Hi, Is it possible to use the .ncf file generated from the ISE5.1i FloorPlanner, in ISE4.1i ? Here i tried, but i got up with some errors? Any one experienced? Thanks and Regards, MuthuArticle: 51015
Hi all,
I am interested in participating in any ongoing FPGA design
projects online. Can anyone of you direct me to such projects.
Thanks in advance.
Wishing you all a happy new year 2003
Regards,
R. Sriram.
Article: 51016http://zxgate.sourceforge.net "R.Sriram" wrote: > Hi all, > I am interested in participating in any ongoing FPGA design > projects online. Can anyone of you direct me to such projects. > Thanks in advance. > Wishing you all a happy new year 2003 > Regards, > R. Sriram.Article: 51017
Lyndon Amsdon ha scritto nel messaggio <1a7d6495.0212260407.1e158d7c@posting.google.com>... > >Hi, you're right. I orignally thought before I bought them that if it >was 5v device then it would be S series, but it is just plain MAX7000. > This hobby is so expensive, would the scheamtics of a programmer be >available or is it quite complicated? Sorry, I don't know schematics of such programmers, ad I belive there are none around because Altera don't releases programming specifications for those devices. The only solution is buying a programmer, but it's unreasonable. I think is better you buy some other device that you can program with Byteblaster interface. LuigiArticle: 51018
johnjakson@yahoo.com (john jakson) writes: > I don't believe distributed ASIC/FPGA simulation is best done by > chopping up blocks & distributing across a pool of cpus. The bandwidth > needed to send signals between the blocks would slow down the overall > result considerably. On the other hand if you want to run many smaller Automatic partition in order to minimize communication overhead is of course difficult. The designer could of course partition the design manually to reduce the communication overhead. An adaptive algorithm could also be incorporated to migrate the process to a different host to reduce the communication. Many signals could be regenerated at each host, e.g. if each clock is generated using something like initial clk = 0; always #10 clk = ~clk; then it could be regenerated at each host instead of transmitting the signal over the interconnect. One big problem is that the license cost is linear, while the performance increase is usually not. Personally I would think it would be great if could throw 16 $3,000 PC's at the problem and get an 8x increase in performance. However, a simulation license usually costs 10-15 times as much as a PC. If a vendor was selling a distributed simulator for less than linear cost this could be worthwhile. Speculative simulation could also be explored. Several nodes could use some statistical information from previous runs an speculatively execute cycles. If the guess was the right one it could simply pass the result to the master node or whatever. Does anybody know any distributed simulator vendors besides Provis (www.provis.com)? Nothing wrong with Provis, but I'm a little surprised that so few vendors don't have parallel simulators, synthesis engines, static timing analyzers, and place & route tools. > sims of lots of different test cases, then that usually just means > separate license 1 per simulator and some workload SW like Compaq? > has. Simulation farms are quite common. > If a very fast cycle C model is available that can run atleast say > 10-1000x faster than HDL simulation, then you could run a C sim for > the no of cycles desired and collect full state say every 1M cycles. > Then a single HDL sim can be split into time chunks of 1M cycles each > per cpu, now there is no communication between cpus save for > collecting the desired detail results. This was (is) a common method to collect vectors to apply to gate level simulations. > Of course if you had a HDL->C compiler, then your C model comes for > free & I assume it would run 10.. faster too but less detailed. Not all C models are free since most of them will embed license checks in the generated C or Asm code. > I personally wouldn't do any project without a V2C compiler. C sims > for most of the work, Verilog for detailed checks. Of course this is > really meant for simpler clock schemes that have predicable time > flows. Do you know any free Verilog to C tools? The optimization methods you have described are not mutually exclusive. They could all be applied to each node in a cluster. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 51019
Hi, In a FIFO design, the full and empty flags will be made Low in the reset condition. But, if you see the Xilinx's core-gen models the full status is made High in reset condition and it will be relesed in the very first clock after releasing RESET. why is this so? Thanks and Regards, MuthuArticle: 51020
nachikap@yahoo.com (Nachiket Kapre) writes: > While simulating a complete ASIC (~5 million gates) consisting of > several individual blocks, is it possible to attempt a concurrent > simulation (functional or timing) in a distributed environment with a > pool of dedicated PCs simulating the individual blocks with > inter-block communication handled by PLI/FLI wrappers in Modelsim I've done something similar using PLI and a socket interface. The test benches and protocol checkers where done in C++ and were communicating with Verilog through PLI. However, the C++ test bench could also be replaced by another Verilog module on a remote host. I described this method briefly while presenting an ASIC at the Hot Interconnects in 1995. The proceedings from the conference might be available online. This was with Cadence Verilog and Chronologic VCS (now part of Synopsys), but it should be possible with any PLI compatible simulator like Modelsim (which I have never used myself). Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 51021
"Martin Schoeberl" <martin.schoeberl@chello.at> writes: > I'm tired of defining pin numbers in a gui. Is there a way to import a text > file (cvs) for the pin definition in quartus? You can do this from Tcl by cmp add_assignment "dut" "" "uclk_pad" "LOCATION" "Pin_H24"; Where dut it the top level module name. You can also save the project commands in a Tcl file (e.g. proj.tcl) and then execute: quartus_cmd -f proj.tcl Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 51022
On Wed, 25 Dec 2002 15:56:53 GMT, allan_herriman.hates.spam@agilent.com (Allan Herriman) wrote: [snip] More information: I've tried putting syn_evaleffort attributes with values of 100 on all the relevant constants, functions, architectures and entities, and it didn't make a scrap of difference - synplify still incorrectly thinks that there's an infinite loop in my code. I'm now treating this as a bug in Synplify-Pro (all versions up to 7.2.1) and have opened a case with Synplicity support. Thanks, Allan. 00097674Article: 51023
If I understand correctly what you are saying, this is not going to work, at least in general case . Unless you know that the original signal's highest frequency component was below 43.3125/2 MHz you can't do it. Also, the fact that you will be resampling with this odd frequency will add up badly to the SNR because it is equivalent to sampling with variable period, which means sampling jitter. There's been number of publications on how sampling jitter affects SNR, one of them I believe is an ADI manual on using ADC's. I don't remember the title exactly but I think you can find it on their website... If you can't let me know and I will dig it up. /Mikhail "Nagaraj" <nagaraj_c_s@yahoo.com> wrote in message news:91710219.0212222219.304a3947@posting.google.com... > Hi all, > I want to resample(at a lower rate,say 'y' Hz) an already sampled > signal(at a higher rate, say 'x' Hz). I am not talking about > "UPSAMPLING->FILERING->DOWNSAMPLING". I am talking about resampling by > deriving clock 'y' from 'x'. Let me illustrate with an example. > Say x=100MHz and y=43.3125MHz. Generate 43.3125MHz from 100MHz > using an NCO and use this clock to get samples. Assume that clock 'x' > to sample delay is more than clock 'x' to clock 'y' delay, by the > setup time requirement for sampled signal w.r.t. clock 'y' (that is no > problem in obtaining the current sample as current sample). > My question is, will there be any problem with this method > regarding spectrum of the resultatnt signal,SNR degradation etc. > Also is it true that while the "UPSAMPLING->FILERING->DOWNSAMPLING" > method only works for y/x = p/q, where p and q are integers, the above > proposed method works for any ratio? > > P.S.: Could you tell me any existing practicle system which uses this > method of resampling? > > regards, > Nagaraj CS --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.431 / Virus Database: 242 - Release Date: 17/12/2002Article: 51024
Hi, > The only solution is buying a programmer, but it's unreasonable. > I think is better you buy some other device that you can program with > Byteblaster interface. I've come to this conclusion too. I originally wanted to use Altera just because they still had support for 5v logic levels on their outputs. I'm now thinking maybe I should just use something like Xilinx CPLDs which I believe have 5v TTL tolerant inputs and set outputs open collector with a external pullup. I know the support for Xilinx is huge. Thanks
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