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Tom Hawkins wrote: > > Obviously hierarchy is essential when building and managing > any large design. But I'm curious how synthesis tools use > hierarchy during the optimization process? Just how critical > is hierarchical partitioning of a design for quality synthesis? > > I remember talking to a Mentor rep a few years ago. At > the time he said the major advantage of Leonardo over > Synplicity was Leo's use of design hierarchy > compared to Synplify which just optimizes a flattened design. > If this was true, is it still the case? If you want the unvarnished truth, download an eval and try it yourself. I would be surprised if brand S can't also enforce a hierarchy. Brands S & M are roughly equivalent, so consider buying based on service and price. You can also do hierarchy yourself by black-boxing multiple .edf files. Hierarchy is handy for browsing your netlist interfaces for clues if something goes wrong. I know of no synthesis efficiency advantage. It seems more likely that you would save gates by optimizing the boundaries. If everything sims, routes, times and works in the system, I don't care if it is flattened or rolled into a ball because I don't have to look at it. On the other hand, it can come in handy. -- Mike Treseler.Article: 50351
Laurent Gauch, Amontec wrote: > > You can assign pin in the VHDL via attributes, but this is not a good idea. > I agree. It is much less trouble to do pins with the place & route tools. Use the GUI or write a tcl script. -- Mike TreselerArticle: 50352
John Jacob wrote: > > > > > So you think their engineering time oughta be ignored? And one chip > > does not a design make. > > > Absolutely not. But when undertaking a development program, one costs out > the development time over the life of the product and adds it to the product > cost over the units to be sold. After a certain point, this engineering time > is completely allocated and the product becomes a manufacturing exercise. At > least, that is how we cost out our engineering time and tooling molds for > our gimbal designs. > > I will also add that I have a lot more respect for a PCB populated with a > number of high-performance ASIC chips throughout the surface. High frequency > design requires a great deal of skill and technique. There was an > interesting paper on a TigerSHARC cluster at > http://www.analog.com/library/applicationNotes/dsp/applicationNotes.html > that discussed the importance of good board design and layout. The pdf link > is located at the bottom of the page with the description "ADSP-TS101S MP > System Simulation and Analysis." > > Also see some of the design notes at http://www.pericom.com/docs/apps.php > with respect to clock buffers and board layout. After reading the issues > confronting the hardware designer when dealing with high-frequency chips, > one develops a much better understanding of what is actually transpiring at > the hardware level. > > But after the development cost have been allocated out, drop the price of > the board. John, you may understand engineering and manufacturing, but you don't understand the DSP business. They are in business to make money and that is not easy to do when they are selling boards one at a time. I get a lot of requests for single quantity purchases followed by complaints on the price. What most fail to understand that the bulk of the cost of single unit sales has little to do with the costs of design or manufacturing, but rather the cost of the sale itself and support. Since Ron seems to have a board that you would like to use, you would do very well to have some discussion about your project requirements, quantities and schedules. Vendors want to work *with* you and not against you. They often have come from the same job you are doing and understand what it takes. You just have to help them help you by talking to them. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50353
Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3DF4B833.CE84362C@xilinx.com>... > On the Virtex Family (E, II, II Pro), the IO assumes the tristate condtion, > as an internal power down signal is sensed, which sets the IOs to the high > impedance state. > > When Vcco is lost, on II and II Pro, there are intrinsic diodes as part of > the IO structure that go into forward conduction as Vcco falls to 0V, and > the IO pins are above ground. About 2 mA (total) is sufficient to bias up a > bank through all of the IOs (through the diodes). As long as a number of > IOs are high, the FPGA IOs will appear to be tristate. > > Austin Austin, Can you describe the power-up sequence in the same fashion? I just discovered that it appears as if, during power-up (as the voltage rails are coming online), the Virtex II brings the I/O voltage up at the same time the power rail is coming up. I'm not saying that the FPGA is necessarily driving it ... maybe this is before the I/O goes tri-state during configuration - or maybe since the bus isn't being driven, the power-up voltage is "leaking" through? A particular vendor memory I have hanging off the FPGA appears to be sensitive to transitions on control lines during power-up. Thank you, MarcArticle: 50354
Marc, In ES material, the IO could be asserted while Vcco was applied, if Vccint was not applied. It was recommended that Vccint, Vccaux, and Vcco all come up together for ES marked parts. Now that was two years ago. All production material comes up tristate in all power sequences. You still have to remember that the intrinsic diodes are present, and any IO may power up the Vcco back thru a forward biased diode (pull down on an exisiting high on a pin). Austin Marc Randolph wrote: > Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3DF4B833.CE84362C@xilinx.com>... > > On the Virtex Family (E, II, II Pro), the IO assumes the tristate condtion, > > as an internal power down signal is sensed, which sets the IOs to the high > > impedance state. > > > > When Vcco is lost, on II and II Pro, there are intrinsic diodes as part of > > the IO structure that go into forward conduction as Vcco falls to 0V, and > > the IO pins are above ground. About 2 mA (total) is sufficient to bias up a > > bank through all of the IOs (through the diodes). As long as a number of > > IOs are high, the FPGA IOs will appear to be tristate. > > > > Austin > > Austin, > > Can you describe the power-up sequence in the same fashion? > > I just discovered that it appears as if, during power-up (as the > voltage rails are coming online), the Virtex II brings the I/O voltage > up at the same time the power rail is coming up. I'm not saying that > the FPGA is necessarily driving it ... maybe this is before the I/O > goes tri-state during configuration - or maybe since the bus isn't > being driven, the power-up voltage is "leaking" through? A particular > vendor memory I have hanging off the FPGA appears to be sensitive to > transitions on control lines during power-up. > > Thank you, > > MarcArticle: 50355
stevetshannon@yahoo.com (Steve T Shannon) wrote in message > [snip] The few things I have found are now all targeted at much > higher speeds (622 Mbps, 1Gbps, etc). Any suggestions on easy-to-use > clock recovery ICs? > > Steve Take a look at the TRU-050 from Vectron http://www.vectron.com/products/cdr/tru050.htm it's good from 1 to 65 MHz MikeArticle: 50356
Hi,
It has been a while since my last digital signal processing class. I
have a question reguarding FFTs in an FPGA. I need a 4096 point
cross-corelation. To do so if I recall correctly one can use an FFT on both
inputs and then multiply and then do an IFFT on the result to get the time
delay in samples. If I recall corectly one of the inputs has to be reversed
in time initially. Now for the real question... I have a 32 point FFT/
IFFT core available. I would like to use this to calculate a 4096 point FFT
(or inverse FFT). If I recall correctly, a 64 point FFT requires 4 32 point
FFTs) thus a 64 point FFT would take 4 times as long using 4 32 bit FFTs as
the original 32 bit FFT. Following that logic train, the 4096 point FFT
will require 16384 times as long as the original 32 point FFT. (4^7) Is
that correct? Am I missing anything important here? I know that I could
use a real DSP, but I am already much more familiar with FPGA's than with
DSP chips. Any other comments would be appreciated. Note: speed is not
real critical to my application. If I can get a cross-correlation every 100
milliseconds that will be quite sufficient. The application requires being
able to recognize the time difference between the first and second echo from
a 220KHz ping every 100 milliseconds. Sample frequency is about 10MHz. The
echo time delay is kept within a 400 microsecond window including the
duration of the echo.
Thanks,
Theron
Article: 50357"Austin Franklin" <austin@da98rkroom.com> writes: > I'm still not quite sure if using a Spartan II, and believing you are going > to be in a 3.3V slot is a good idea. %99.99 PCs are still 5V PCI... AFAIK, the Spartan II should work just fine with either 3.3V or 5V signalling. But he wanted to use a Spartan IIE, and those aren't 5V-tolerant.Article: 50358
I forgot on how to set the programmer in Quartus2. Processing, open programmer brings up the chain form. Mode is set to JTAG and the Programming hardware shows type : No Hardware. 'Setup' brings the programming hardware setup form, where add brings the modal :An error, internal error 82, occured while accessing the JTAG server. I have Quartus 2 web Version 2.0 and the JTAG driver with the byteblasterMV works with MaxPlus2. any hints ? Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 50359
Don't forget to look at the www.opencores.org site for a pleasant surprise! There is an FFT project there - check the mailing list for some recent discussions and English translations of the documentation as well. I thought that FFT complexity was proportional to log N??? I don't think you are right as I often see people using radix 2 or radix 4 butterfly stages. You could always do the cross-correlation directly at those speeds in a MAC serial structure couldn't you? Paul "Theron Hicks" <hicksthe@egr.msu.edu> wrote in message news:at322s$201c$1@msunews.cl.msu.edu... > Hi, > It has been a while since my last digital signal processing class. I > have a question reguarding FFTs in an FPGA. I need a 4096 point > cross-corelation. To do so if I recall correctly one can use an FFT on both > inputs and then multiply and then do an IFFT on the result to get the time > delay in samples. If I recall corectly one of the inputs has to be reversed > in time initially. Now for the real question... I have a 32 point FFT/ > IFFT core available. I would like to use this to calculate a 4096 point FFT > (or inverse FFT). If I recall correctly, a 64 point FFT requires 4 32 point > FFTs) thus a 64 point FFT would take 4 times as long using 4 32 bit FFTs as > the original 32 bit FFT. Following that logic train, the 4096 point FFT > will require 16384 times as long as the original 32 point FFT. (4^7) Is > that correct? Am I missing anything important here? I know that I could > use a real DSP, but I am already much more familiar with FPGA's than with > DSP chips. Any other comments would be appreciated. Note: speed is not > real critical to my application. If I can get a cross-correlation every 100 > milliseconds that will be quite sufficient. The application requires being > able to recognize the time difference between the first and second echo from > a 220KHz ping every 100 milliseconds. Sample frequency is about 10MHz. The > echo time delay is kept within a 400 microsecond window including the > duration of the echo. > > Thanks, > Theron > >Article: 50360
Uwe Bonnes wrote: > Hal Murray <hmurray@suespammers.org> wrote: > ... > : Did 3V PCI ever take off? Can I get PC motherboards and/or > : a reasonable collection of plug in cards? That would allow > : using a Spartan-IIE (Virtex) with DLLs. > > Normal consumer PC's still are 5 V. You can however get 3.3V PCI > motherboards when looking harder. > > Bye Normal consumer PC's most certainly have 3.3V power rails on their PCI slots, and from experience I can say that most of them drive logic high to 3 Volts. The threshold level is 2.0V, so a Spartan-IIE should be able to drive a 5V backplane just fine. But pullups on the backplane of 5V systems pull the undriven signals to 5V, not to mention the 5V sources that occasionally appear in the wild, and that is out of spec for the IIE, I think. PLX chips are cheap, implement the PCI target and master stuff for you, and with a little bit of cleverness, you can do your Xilinx download from the PCI bus through the PLX chip, thus making your board much more flexible. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 50361
Hi, > Not if your downsampling filter is adapted to the final sampling frequency. > @40MHz, you sould be able to do that in a spIIe without problems. Is the downsampling filter a seperate chip, or is it just a core in the fpga? cheers, JamieArticle: 50362
Rene Tschaggelar wrote: > I forgot on how to set the programmer in Quartus2. > Processing, open programmer brings up the chain > form. Mode is set to JTAG and the Programming hardware > shows type : No Hardware. > 'Setup' brings the programming hardware setup form, where > add brings the modal :An error, internal error 82, > occured while accessing the JTAG server. > I have Quartus 2 web Version 2.0 and the JTAG driver > with the byteblasterMV works with MaxPlus2. > > any hints ? Solved - by downloading Version 2.2 ReneArticle: 50363
hmurray@suespammers.org (Hal Murray) wrote in message news:<uv7obvfao3jk22@corp.supernews.com>... > > Does that seem reasonable? Is there a better approach I've > missed? Sounds like you know what you are talking about. I am doing a 2 layer project at 25MHz PCI that is working fine so far in a lab environment (www.tech-forge.com). Hi-freq caps are on the back side of the 208 PQFP. > > Did 3V PCI ever take off? Can I get PC motherboards and/or > a reasonable collection of plug in cards? That would allow > using a Spartan-IIE (Virtex) with DLLs. I think you will find 3V PCI mainly in server boards. My last project was a 133MHZ PCI-X, unfortunately the chip only had 3.3V tolerant inputs and could not be on a bus with other 5V components (doh!) > Do people who want to use 3V PCI just use a PCI-PCI bridge chip? > Or another FPGA? I think both Altera and Xilinx offer 5V tolerant 3.3V IO devices. (They accept 5V, but drive only 3.3V max, so they are fine on all PCI) The Altera 10K30 I am using has a 2.5V core and 3.3V IO supply. Both are small linear regulators. > > > Anybody have a list of PCI-some-simple-bus type chips? > I'm only interested in ones that are cheap and reasonably > available in small quantities. I think PLX is great too, last I checked the web pricing it was $18 for a PCI-localbus interface chip. Good luck, -SteenArticle: 50364
"transformer" <compresstransform2002@hotmail.com> wrote in message news:4a96bae1.0212090345.6bab1a21@posting.google.com... > > > > > > I think I can complete the vhdl code of the multiplier. What I need is > the layout, and the required area of my design using standart > libraries. Which tool is best suited for this purpose? It should also > be freeware or low cost. > Thanks > > You need a library, synthesis tool (or hand conversion to gates), place and route tool, checking tools (LVS/DRC). Is MCNC still in business? Mosis have tools? What does your school support? Getting, installing, and learning all those tools is a pretty tough row to hoe. del cecchiArticle: 50365
>Is the downsampling filter a seperate chip, or is it just a core in the >fpga? Classic downsampling in this sort of DSP/FPGA context is a neat trick to get away with a less expensive analog filter. Suppose your signal has a bandwidth of 1 MHz, so you need to sample at 2 MHz. But you also need a filter that gets rid of everything over 1 MHz or it will get aliased back to below 1 MHz. Brick wall filters are impossible to expensive depending upon how close you get. If you build a reasonable filter, it lets stuff through up to (say) 3 MHz. So you run your A/D to 8 MHz, knowing that the filter has killed everything below 4 HMz. Then you run a digital filter that throws away everything below 1 MHz. Nyquist now tells you that you don't need that many samples, so you can just throw away the ones you don't need. In the case that started this discussion, he wanted to make a 40 MHz clock for the A/D, but he was starting with a 120 MHz clock. Seems obvious that he could just throw away 2 out of 3 samples. There may be something better to do, but I'm not smart enough to see it. Might be something like you can get rid of some noise if you run through a filter that throws away the bandwidth you don't need. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 50366
>I agree. It is much less trouble to do pins with the place & route tools. >Use the GUI or write a tcl script. It seems to me that the key step is to assign the pins in only one place for all the tools/files that need to know about them. Is there a reasonably common/simple way to get them out of the VHDL world into a form where the PCB layout tools can use them? Are other people paranoid about this sort of thing? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 50367
You generally end up needing a ucf in addition to your VHDL, even if youhave
constraints in the VHDL. I put my pin assignments in the UCF, and I think that
is fairly common in the industry.
Hal Murray wrote:
> >I agree. It is much less trouble to do pins with the place & route tools.
> >Use the GUI or write a tcl script.
>
> It seems to me that the key step is to assign the pins in only one
> place for all the tools/files that need to know about them.
>
> Is there a reasonably common/simple way to get them out of the
> VHDL world into a form where the PCB layout tools can use them?
>
> Are other people paranoid about this sort of thing?
>
> --
> The suespammers.org mail server is located in California. So are all my
> other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
> commercial e-mail to my suespammers.org address or any of my other addresses.
> These are my opinions, not necessarily my employer's. I hate spam.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50368> Did 3V PCI ever take off Thanks for all the feedback. Sorry my question wasn't clear. There are two possible meanings for 3V. One is power. The other is the signaling level. First, the power stuff: The PCI connector has power pins for 5V, and 3.3V, and also a few more pins for IO power. They are either 3 or 5, depending upon the signaling voltage, the idea being that you can wire them to the supply rail for your IO pads and make a board that supports either 3V signaling or 5V, depending upon the power the motherboard supplies on those pins. The PCI connector has a plug that matches with a cutout on the board. The plug goes in either of two positions (turn the connector around), one for 5V signaling, the other for 3V. So in theory, you can make three types of cards. The normal card in wide use is 5V signaling, though they may only drive the outputs with a 3V CMOS driver. You can also make 3V only card by putting the cutout on the other end of the card. You can also make 3V/5V cards by cutting out both slots and maybe wiring the IO pad rail on your chip to the IO supply from the PCI connector. I've never seen any 3V or dual cards. The main question I was trying to ask was if anybody had seen any 3V or dual signaling level cards. If so, I might think more about taking advantage of that. Since I didn't see many encouraging responses I'll probably but this on the back burner. Some early systems didn't actually supply any 3.3V power. You can dance around that with an on-board regulator. I plan to ignore that. (But I'll check my systems first, just in case, and listen for tales of troubles with not-so-early boards.) Now for the signaling: The 3V signaling rules overlap the 5V rules enough so that a card that drives high to 3V will work in a 5V system. The catch is that some other card driving to 5V on a system that produces worst-case reflections might generate an 11V spike. "5V tolerant" is the critical term for that. The Spartan-II is 5V tolerant but doesn't have DLLs. The -IIE has DLLs, but doesn't tolerate 5V signaling. Since 3V systems don't seem to be very popular, I probably won't build a card expecting to find a 3V only slot. Several years ago, I put a scope on a system that had the connector pegs set for 5V. I never saw anything go over 3V. Obviously that depends upon what cards are plugged in. Somebody could add an old/evil card that really does drive to 5V. For hack/research systems it might make sense to use a FPGA that wasn't 5V tolerant on a card that could be plugged into a 5V system. You would have to remember to get out the scope before adding a card that hadn't been tested yet. I'm probably not desperate enough to get the DLLs that I will do this. (But I'm still scheming.) Thanks for the PLX suggestions. Their web site expects me to register before they give me data sheets so I'll put that on the back burner. Thanks for the heads-up about using DLLs on PCI clocks. Is that a clear don't-do-that, or just another worm for the list? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 50369
In article <3DF552B6.95F53F2D@andraka.com>, Ray Andraka <ray@andraka.com> writes: >You generally end up needing a ucf in addition to your VHDL, even if youhave >constraints in the VHDL. I put my pin assignments in the UCF, and I think that >is fairly common in the industry. Thanks. How do you keep the PCB and UCF in sync? What if you make a last minute change to the board or the chip pinout? Is there a script that makes (fixes?) one from the other? Or do people just do it by hand and be (very) careful? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 50370
I have been thinking about a tiny stack based processor in verilog, much like the KPSM (Pico Blaze). It seems like a stack based machine would be more suitable for this kind of application because the instruction size is smaller, allowing more compact code, there should be less multiplexing required leading to a smaller size in a limited amouint of memory. You could program it in forth, which gives you a fairly nice language to work in and easy to develop tools. Does anyone know of any existing designs like this - or work done on any? Or is this an unfilled niche, or perhaps there is some fundamental error in my thinking on the suitability of a tiny forth processor for these kind of tasks. Thanks for any insights / ideas / pointers RalphArticle: 50371
>success. The few things I have found are now all targeted at much >higher speeds (622 Mbps, 1Gbps, etc). Any suggestions on easy-to-use >clock recovery ICs? I guess that's where the money is these days. In order to avoid the clock jitter on the A/D, I'd probably try to do the clock recovery on the other board. My straw man would be to get a clock that goes much faster than the bit rate, and build a small state machine to do the work. The state machine will spit out 3 signals: carrier (in packet), the data bit, and a data-valid pulse on for one cycle per bit. That only works if your input signal is pretty clean, you have a (roughly) 8x clock, and the rest of the processing doesn't have to be locked to the source (A/D) clock rate. The basic idea being to use clock enables where necessary, and make sure the work can get done in 7 clocks rather than 8. (or make the 8x clock into an 8.1x clock, or try 8.01x and add a small FIFO...) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 50372
hi,FB > entity FPGA is > port( > clk : in STD_LOGIC; > x : in STD_LOGIC; > y : in STD_LOGIC; > z : out STD_LOGIC > ); > -- pad locations > attribute LOC: string; > attribute LOC of clk: signal is "P1"; > attribute LOC of x: signal is "P2"; > attribute LOC of y: signal is "P3"; > attribute LOC of z: signal is "P4"; > end FPGA; What does "P1" mean here? the number of available pins of FPGA? Best regards, siriuswmxArticle: 50373
On 09 Dec 2002 08:44:48 +0000, Martin Thompson <martin.j.thompson@trw.com> wrote: >Spam Hater <spam_hater_7@email.com> writes: > >> A statement like: output <= input; will generate a 'feed >> through net warning'. All it's telling you is that there's no >> "logic". Ignore it. >> > >Unless it's a clock feeding something else later, and you use the >source clock as well... > Martin, Everything you said is true, but... He's using FPGA Express. He will get a (another) bevy of warning messages if he tries to use a net as a clock, or a clock as a net. SH7Article: 50374
Depends on the tools being used and who is doing each part. In most of my cases,
the customer is doing the board, so the changes are by hand and checked over
carefully at both ends.
Hal Murray wrote:
> In article <3DF552B6.95F53F2D@andraka.com>,
> Ray Andraka <ray@andraka.com> writes:
> >You generally end up needing a ucf in addition to your VHDL, even if youhave
> >constraints in the VHDL. I put my pin assignments in the UCF, and I think that
> >is fairly common in the industry.
>
> Thanks.
>
> How do you keep the PCB and UCF in sync? What if you make a last
> minute change to the board or the chip pinout?
>
> Is there a script that makes (fixes?) one from the other? Or do
> people just do it by hand and be (very) careful?
>
> --
> The suespammers.org mail server is located in California. So are all my
> other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
> commercial e-mail to my suespammers.org address or any of my other addresses.
> These are my opinions, not necessarily my employer's. I hate spam.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
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