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On Sun, 8 Dec 2002 13:34:03 -0700, "Pete Dudley" <pete.dudley@comcast.net> wrote: >Hello, > >We have incorporated Maxim max1617a temperature sensor chips onto a new >board we just designed. We have a 1617 for each Virtex and Virtex 2 chip on >the board. > >We are finding that the temperature measurement jumps around a lot when we >are actually processing data in the sensed Virtex 2 fpga. Does anyone know >if the max1617a is affected by switching noise or ground bounce in such a >way that it is innacurate when the sensed fpga is in heavy operation? Ours don't seem to be affected. We have temp sensors on most FPGAs, and I've never heard of unstable temperature readings. I think the most likely problem is crosstalk from a digital line onto the DXN or DXP signal. Review your pcb layout. BTW, did you remember the cap between DXN and DXP? Larger values of capacitance may reduce the noise at the expense of a steady state error. Regards, Allan.Article: 50326
Clyde R. Shappee wrote: > > Hello all, > > I am building an oscillator in a Cypress 37128 device which is the > standard inverter parallel resonant circuit. I have done this dozens of > times in other programmable logic devices, as well as discrete gates. > > The frequency of operation is 32.768kHz. > > I have a 1 Megohm resistor across the crystal to start it up, standard > load capacitors yielding the required 12.5 pF load, and a resistor in > series with the crystal to limit the power. This resistor, in a > previous job required >>> 100k <<<< which was high in my experience. I > have experimented with this resistor and the startup one, but cannot get > the oscillator to go. I have tried 0 to 100 K for the series resistor. > > Does anyone here have experience with a Pierce oscillator at this > frequency in this device? I did not expect this problem at all.... or I > would have designed in a discrete transistor oscillator that I know > works. > > Clyde It's a bit unclear - I presume this does not actually work, and thus the question ? When you say 'dozens' does that mean at 32KHz, and CPLD, or something else ? Getting even a HCU04, or a uC XTAL Buffer, to oscillate at 32.768KHz is not trivial. You need low drive currents ( hi output impedance ) to get the phase shifts needed. That's why the uC that target 32Khz, have special 'sub 100Khz' buffer stages. A transistor can oscillate OK at 32KHz, but lacks the slew rate to reliably clock a CPLD, so will need a Schmitt buffer. Low slew causes a number of problems - it can multi-clock due to ground bounce - it can give rise to transistion oscillations ( > 100MHz ) - it can have significant linear-mode thru currents (mA region) -jgArticle: 50327
Hal Murray wrote: > I'm scheming about building a hobby/hack project that > needs an FPGA on a PCI card. Volumes will be very low. > > My straw man is Spartan-II. Even with a big one, the > cost of the PCB will be more than the cost of the FPGA. > > Is it reasonable to get away with only 4 layers? I'm thinking > of using a PQ208, dedicated layers for 3.3V and GND, and filling > the top layer inside the pad ring with copper for the 2.5V core > power "plane". > > I think everything else on the board will run at 3.3V, or I > can fudge it. There won't be much routing so if the PCI works, > I should be able to get away with 2 signal layers. > > Does that seem reasonable? Is there a better approach I've > missed? > > > < snip > As far as I know, the problems with PCI are the Windows drivers. What kind of tool did you have in mind for that ? ReneArticle: 50328
I have two boards, an acquisiton board and a DSP board. They are connected by two segments of fiber, one in each direction. I'm using low-cost agilent plastic fiber here, so data rates are limited to <10 Mbps. I read the excellent xilinx app not on data recovery (different from the clock & data recovery one) and I have implemented it -- but I'm still worried, for the following reasons: I essentially have one part of my system sampling the data and the other processing it. These run on slightly different clocks, due to tolerances with the crystals. The xilinx app note details this. However, if the acquisition board clock is running slightly faster than the processing board clock, the processing board will be forced to occasionally drop a sample. Similar problems if speed differences are reversed. So I hit upon the idea of, at the very least, using clock recovery for the acquisition board. The DSP board sends its 8b/10b encoded data over the fiber (for control data and whatnot) to the acquisition board. this clock is recovered and use to guarantee that the acquisiton board never samples too fast --i.e. it delivers just enough data for the dsp board. Then i can use teh xilinx suggested data recovery code, and not lose too much sleep. The problem with this approach lies in the fact that the acquisiton board has some heavy pre-processing it needs to do, and so needs to be running at 64 MHz. I am only recovering an 8MHz clock, which is too slow to be multiplied using the on-chip DLL, and in any case couldn't go all the way to 64 MHz. So my first attempt at a solution involved sticking a 32 MHz clock on the acquisition board and simply doubling it to 64 Mhz. But then -- there's no way to synchronize it to the 8 MHz recovered clock. When i divide it down, i'm left with the exact same problem i had at the begining -- one clock at 8MHz, one at 8+epsilon, eventually dropping bytes here and there. Any thoughts? I figure this must be a common problem. My end-product budget won't let me go with more expensive higher-bandwidht fiber, so i'm relatively stuck at the non-multiplable 8 MHz. Has anyone solved similar design issues who might be willing to provide insight? Thank you so much, steveArticle: 50329
Try www.amontec.com Komodo board : the FPGA PCI platform Coming with ezPCI nt4/w2k/xp drivers and ezPCI binary core all for $980 sorry for the small documentation, we are finishing it and will publish it on our website soon. regards Laurent Gauch, Amontec Hal Murray wrote: > I'm scheming about building a hobby/hack project that > needs an FPGA on a PCI card. Volumes will be very low. > > My straw man is Spartan-II. Even with a big one, the > cost of the PCB will be more than the cost of the FPGA. > > Is it reasonable to get away with only 4 layers? I'm thinking > of using a PQ208, dedicated layers for 3.3V and GND, and filling > the top layer inside the pad ring with copper for the 2.5V core > power "plane". > > I think everything else on the board will run at 3.3V, or I > can fudge it. There won't be much routing so if the PCI works, > I should be able to get away with 2 signal layers. > > Does that seem reasonable? Is there a better approach I've > missed? > > > I'm still keeping an eye open for an existing prototype board > that I can adapt to what I need, but I haven't seen one that > looks close yet. If I have to build a daughter card to plug > into an existing card, I might as well do the whole thing and > get exactly what I want. > > > Did 3V PCI ever take off? Can I get PC motherboards and/or > a reasonable collection of plug in cards? That would allow > using a Spartan-IIE (Virtex) with DLLs. > > I'm assuming it flopped since I don't remember seeing ads > for mother boards nor do I remember seeing cards that had > the second slot. I'm assuming lots of people would build > them if there was any interest. > > Do people who want to use 3V PCI just use a PCI-PCI bridge chip? > Or another FPGA? > > > Anybody have a list of PCI-some-simple-bus type chips? > I'm only interested in ones that are cheap and reasonably > available in small quantities. >Article: 50330
Spam Hater <spam_hater_7@email.com> writes: > A statement like: output <= input; will generate a 'feed > through net warning'. All it's telling you is that there's no > "logic". Ignore it. > Unless it's a clock feeding something else later, and you use the source clock as well... If this is the case, anything else clocked by it will happen 1 delta-cycle after the rest of your design, which may cause problems. The synthesiser will replace that statement by a piece of wire, which does not have a delta-cycle delay effect when the real hardware comes along. HTH, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 50331
>As far as I know, the problems with PCI are the Windows drivers. >What kind of tool did you have in mind for that ? Linux. I admit I haven't written one, but I'm not too worried about that area. At worst I'll have to bribe some friends with beer or dinner. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 50332
Yes, this is a common problem. You can send a clock in one direction, and then run that whole board off the derived clock. This usually requires a PLL and some analog clock recovery magic. (And you have to figure out what will happen if the fiber is unpluged.) This may require a small FIFO on the receiving end to cover the unknown phase when the data gets back there. I think the standard trick is 4 slots. The other approach is to run both boards off their own clocks and somehow make sure you never drop samples, or that dropping samples is OK. Suppose your DSP side could run at 10 MHz rather than 8. It just stalls occasionally when the data sample isn't ready yet. You only have to run a bit faster if you are willing to special order the crystals - enough to cover the tolerances. But your system has to be able to tolerate gaps. That's a system level/algorithm problem. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 50333
wangmanxi@yahoo.com (siriuswmx) wrote in message news:<4528663b.0212071721.41490a4e@posting.google.com>... > Hi, everyone, > Must i turn to symbol entry window to assign the pins? > thanks a lot! Hi, it might not be good practice to specify constraints in a VHDL design file, but it can be done. In Xilinx (Webpack 5.1 for example), just do it this way: entity FPGA is port( clk : in STD_LOGIC; x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC ); -- pad locations attribute LOC: string; attribute LOC of clk: signal is "P1"; attribute LOC of x: signal is "P2"; attribute LOC of y: signal is "P3"; attribute LOC of z: signal is "P4"; end FPGA; Do that only in your top-level VHDL file that should be application specific... Yours, FBArticle: 50334
Hi !
I tried the following program in Handel-C,
but it's giving the wrong output values in
array b[][] while using the "par" construct.
It's working correctly with "far" instead of "par".
Any assistance appreciated.
Regards,
Saurabh
==========================================================
set clock = external;
static rom unsigned 4 Sub[16]=
{
0xa, 0xb, 0xc, 0xd,
0xe, 0xf, 0x1, 0x2,
0x3, 0x4, 0xf, 0xe,
0xd, 0xc, 0xb, 0xa
};
void main()
{
unsigned 2 row,col;
unsigned 4 a[3][3], b[3][3];
a[0][0] = 0x1;
a[0][1] = 0x2;
a[0][2] = 0x3;
a[1][0] = 0x4;
a[1][1] = 0x5;
a[1][2] = 0x6;
a[2][0] = 0x7;
a[2][1] = 0x8;
a[2][2] = 0x9;
par(row=0; row<=2; row++)
{
par(col=0; col<=2; col++)
{
b[row][col] = Sub[ a[row][col] ];
}
}
} // end main
==========================================================
Article: 50335Some weeks ago I announced a FPGA prototyping board (with Altera ACEX 1K50). A kind of module with RAM, Flash, watchdog and RS232 driver on board for FPGA CPUs. Now an IO expansion for this module is available. The board contains Cirrus Logic CS8900 10Base-T Ethernet Contoller, step down regulator (8V to 14V AC/DC to 5V) and EMC/ESD protected IO. Two inputs can be used as analog input with a sigma delta ADC in the FPGA. The main purpose for this board is to build a complete Internet enabled system with JOP (my Java Processor). But I'm sure it's also usefull if you need a simple solution to play around with Ethernet in your FPGA projects. More info: http://www.jopdesign.com/board.html Sources for CS8900 driver and a simple TCP/IP stack are available in Java. For analog input you can find a VHDL file for simple sigma delta ADC. Kind regards Martin Schoeberl martin.schoeberl@chello.at -- JOP - a Java Optimized Processor for FPGAs. http://www.jopdesign.comArticle: 50336
On a Virtex FPGA, if I shut down vccint but keep vcco, what level do the pads have? High impedance? Same as when vcco is down? Thanks, Matthias -- ------------------------------------------------------------- Matthias Dyer phone: +41-1-6327061 Gloriastr. 35, ETZ G-63, fax: +41-1-6321035 CH-8092 Zurich, Switzerland email: dyer@tik.ee.ethz.ch Computer Engineering and Networks Lab (TIK) Swiss Federal Institute of Technology (ETH) Zuerich -------------------------------------------------------------Article: 50337
Hal Murray <hmurray@suespammers.org> wrote: ... : Did 3V PCI ever take off? Can I get PC motherboards and/or : a reasonable collection of plug in cards? That would allow : using a Spartan-IIE (Virtex) with DLLs. Normal consumer PC's still are 5 V. You can however get 3.3V PCI motherboards when looking harder. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 50338
"Kevin Yeoh" <kevyeoh@tm.net.my> wrote in message news:<3df41ac8_2@news.tm.net.my>... > Hi, > > Do you want to write the code yourself? or do you want to generate the code > base on your vlsi design? If you just want the former, I have a software > VHDLmg developed by my university which is free of charge. There is a > tutorial for you to learn also. Basically, you create the module in the > software and it will generate the vhdl code for you itself. Mail me if you > want the software and we can arrange something about it. > > rgds > > KEv > > I think I can complete the vhdl code of the multiplier. What I need is the layout, and the required area of my design using standart libraries. Which tool is best suited for this purpose? It should also be freeware or low cost. Thanks > > > > "transformer" <compresstransform2002@hotmail.com> wrote in message > > news:4a96bae1.0212081216.60ca70bf@posting.google.com... > > > Dear All, > > > I have completed my work on a radix-4 booth multiplier. Now I have to > > > complete its vlsi layout. Unfortunately, I have only some vhdl > > > knowledge and completely new to vlsi design. Which free or low-priced > > > vhdl design software is suitable for my needs. > > > Thanks > > > >Article: 50339
On Mon, 09 Dec 2002 00:19:11 +0000, Hal Murray wrote: PCB - The two power planes, one split, sounds OK. 3V3 PCI - Would a linear reg give you 3V3 from the 5V motherboard PCI socket with will allow you to use your FPGA - which I believe has 5V tolerant IO? PTArticle: 50340
This is a multi-part message in MIME format. --------------45D656EAE4E1073F06F05ACC Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Dear Tom, Your starting point is to work out which technique to use to implement the filter. I'm assuming here that you want to implement the filter with a reasonable degree of efficiency to help keep the cost down. To do this, ask yourself what the sample rate is, and how fast you feel comfortable clocking the device. Anything less than a 100MHz clock rate is really not utilising the capability of a Xilinx devices. Then you can work out how many clock cycles you have available per sample. If you only have one clock cycle per sample, then you need a full parallel implementation. If you have loads of clock cycles (say >100) then you could use something much more like a processor structure with a multiply and accumulate engine of some kind and a block or two of memory. For something between these limits, then there are a host of multi-cycle techniques that use distributed memory. You might find it useful to look at the Xilinx Core Generator to see all these possibilities and hopefully you will be able to plug in your coefficients and generate what you need immediately. If you use MatLab, then try the direct flow with System Generator. Thinking of your application more closely, if the input is a PR square wave, then if I assume that the values are simple ones like +1 and -1, then you really don't need anything like a full filter. Your data samples are simple one bit values, you won't need a multiplier to multiply by +1 or -1, and so all you'll need to do is some additions and subtractions of coefficients. I wrote the DSP Techniques Course for Xilinx. Take a look at the web site to find out when the next one is running near you and for the course description. http://www.xilinx.com/support/education-home.htm http://www.xilinx.com/support/training/abstracts/v4/atp-dsp.htm Regards, KenArticle: 50341
> You can send a clock in one direction, and then run that whole > board off the derived clock. This usually requires a PLL and > some analog clock recovery magic. (And you have to figure out > what will happen if the fiber is unpluged.) This may require a > small FIFO on the receiving end to cover the unknown phase when > the data gets back there. I think the standard trick is 4 slots. Since I already have 8b/10b encoded data going both directions (with a guaranteed number of transitions occuring within a small time window) I should "theoretically" be able to recover my clock using your suggested analog magic and then be happy -- the fear is that I'm potentially driving my sample clock off of this, there might be jitter concerns, etc. Plus, i'm miserable at analog design work -- I've spent all morning searching for an easy-to-use clock recovery IC without success. The few things I have found are now all targeted at much higher speeds (622 Mbps, 1Gbps, etc). Any suggestions on easy-to-use clock recovery ICs? SteveArticle: 50342
In your code, Sub is a rom. You cannot access multiple indices of a rom array on the same clock cycle.Article: 50343
Matthias, On the Virtex Family (E, II, II Pro), the IO assumes the tristate condtion, as an internal power down signal is sensed, which sets the IOs to the high impedance state. When Vcco is lost, on II and II Pro, there are intrinsic diodes as part of the IO structure that go into forward conduction as Vcco falls to 0V, and the IO pins are above ground. About 2 mA (total) is sufficient to bias up a bank through all of the IOs (through the diodes). As long as a number of IOs are high, the FPGA IOs will appear to be tristate. Austin Matthias Dyer wrote: > On a Virtex FPGA, if I shut down vccint but keep vcco, what level do the > pads have? High impedance? Same as when vcco is down? > > Thanks, > > Matthias > > -- > ------------------------------------------------------------- > Matthias Dyer phone: +41-1-6327061 > Gloriastr. 35, ETZ G-63, fax: +41-1-6321035 > CH-8092 Zurich, Switzerland email: dyer@tik.ee.ethz.ch > > Computer Engineering and Networks Lab (TIK) > Swiss Federal Institute of Technology (ETH) Zuerich > -------------------------------------------------------------Article: 50344
Muthu, A few things. look at in line commnets > Hi wei, > > Here i tried to generate RLOC for a top module which has Module's > with 3 levels of Hierarchy. The notable thing here is, some of the > modules with in the hierarchy is generted from the coregen. So, that > will have the RLOC contrains. How that constrains will be treated. > will that be overwritten or the ORIGIN alone gets vary. RLOC_ORIGIN should be placed on the component with X0Y0 because RLOC_ORIGIN value adds on to the RLOC value. In your case, RLOC value inside the Coregen will add to the RLOC value you gave to the upper level logic. > And My submodule's Having the instantiation of BRAMs too. So, after > generating the .ucf from the floor planner. As of now, Floorplanner doesn't generate RLOC constraints for BRAM. BRAMs are on a different RLOC coordinate. You may want to take a look at XAPP416 if you have to RLOC BRAM. > I just tried to Re-Run the > same with the .ncf contrain. But There i am getting an translation > error that, some of the instances couldn't find. You may have run into a NGDBUILD bug if your RPM is trying to call out another instantiated EDN/EDF file. You may want to first run the RPM into one netlist file. > I didn't change any line of .ncf generated by the Floor planner.? Regards, WeiArticle: 50345
Hi Hal, > Is it reasonable to get away with only 4 layers? Yes. Most of my PCI boards are two power/ground layers and two signal layers. I split the power plane as needed. > I'm thinking > of using a PQ208, dedicated layers for 3.3V and GND, and filling > the top layer inside the pad ring with copper for the 2.5V core > power "plane". I'm still not quite sure if using a Spartan II, and believing you are going to be in a 3.3V slot is a good idea. %99.99 PCs are still 5V PCI...and the ones that are 3.3V PCI are typically in the 66MHz slots...which means if your core doesn't run at 66MHz, you will slow every other peripheral on the 66MHz bus down to 33MHz. > Did 3V PCI ever take off? Can I get PC motherboards and/or > a reasonable collection of plug in cards? There are not many 3.3V 66MHz PCI cards, as most cards just don't need the speed...they are mostly Gigabit network cards...and video cards are AGP. > That would allow > using a Spartan-IIE (Virtex) with DLLs. Be careful using DLLs for PCI clock. > Anybody have a list of PCI-some-simple-bus type chips? > I'm only interested in ones that are cheap and reasonably > available in small quantities. PLX. You can buy them directly, and they are cheaper than the FPGA...and they have a kick ass DMA, if your card is going to be a master. AustinArticle: 50346
hi all, reading the datasheet of the new Spartan-IIE devices, I find four more DLL input pins, mainly used for differential input signalling. What exactly is the enhancement? Is it now like that, that I can use the four global clock inputs and at the very same time the four DLL[0..3] named inputs for DLL feedback for example. This would be an enhancement compared to Spartan-II if the signals are single ended. markusArticle: 50347
"Jamie Morken" <jmorken@shaw.ca> wrote in news:EnQI9.180220$ka.4218852@news1.calgary.shaw.ca: > Hi, > >> As Ray explains in his comment, a better solution is an analog PLL >> with divider, in a separate component. Unless you are constrained by >> power > > Could you recommend a PLL part that would be good for this? > I saw a design where the clock was generated by a DDS ( AD9834, iirc), but that's probably a complete overkill in your case >> issues, you can also feed the ADC with 120 MHz, and do a digital down >> conversion in the FPGA. > > I like this solution the best I think. But if the sampling rate on > the ADC goes up > so does the sampling noise doesn't it? > Not if your downsampling filter is adapted to the final sampling frequency. @40MHz, you sould be able to do that in a spIIe without problems. hth Sylvain YonArticle: 50348
Hi. I am trying to debus a problem with a miss-behave DCM. In http://toolbox.xilinx.com/docsan/xilinx4/data/docs/lib/dsgnelcd50.html I see the meaning of status bits 0 and 1. I wonder if someone can reveal the meaning of status bits 7-2 ? ThankX NAHUMArticle: 50349
Steve,
since your data rate is relatively low, you could oversample at the
receive end, and generate clock enables to the rest of your logic so that
away from the recovered clock transitions you just do nothing, and at the
transitions you enable the clock for one cycle. It avoids the PLL mess,
but it does complicate your downstream data path a bit due to the clock
enables.
Steve T Shannon wrote:
> > You can send a clock in one direction, and then run that whole
> > board off the derived clock. This usually requires a PLL and
> > some analog clock recovery magic. (And you have to figure out
> > what will happen if the fiber is unpluged.) This may require a
> > small FIFO on the receiving end to cover the unknown phase when
> > the data gets back there. I think the standard trick is 4 slots.
>
> Since I already have 8b/10b encoded data going both directions (with a
> guaranteed number of transitions occuring within a small time window)
> I should "theoretically" be able to recover my clock using your
> suggested analog magic and then be happy -- the fear is that I'm
> potentially driving my sample clock off of this, there might be jitter
> concerns, etc. Plus, i'm miserable at analog design work -- I've spent
> all morning searching for an easy-to-use clock recovery IC without
> success. The few things I have found are now all targeted at much
> higher speeds (622 Mbps, 1Gbps, etc). Any suggestions on easy-to-use
> clock recovery ICs?
>
> Steve
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
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