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It is the pin number on the package. LOC is a location constraint.
siriuswmx wrote:
> hi,FB
> > entity FPGA is
> > port(
> > clk : in STD_LOGIC;
> > x : in STD_LOGIC;
> > y : in STD_LOGIC;
> > z : out STD_LOGIC
> > );
> > -- pad locations
> > attribute LOC: string;
> > attribute LOC of clk: signal is "P1";
> > attribute LOC of x: signal is "P2";
> > attribute LOC of y: signal is "P3";
> > attribute LOC of z: signal is "P4";
> > end FPGA;
> What does "P1" mean here? the number of available pins of FPGA?
>
> Best regards,
> siriuswmx
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50376Very, very carefully! I usually use a printout of the UCF (or CTL in other tools), the PCB symbol, and a highlighter... Xilinx ISE will detect that a UCF is newer than the implimentation, and prompt you to rebuild your design. Others don't. SH7 On Tue, 10 Dec 2002 03:38:55 -0000, hmurray@suespammers.org (Hal Murray) wrote: > >How do you keep the PCB and UCF in sync? What if you make a last >minute change to the board or the chip pinout? >Article: 50377
The 64 bit PCI supports 3v, and any motherboard with it will work with the 3v
cards. Some of the FPGA cards such as the ISI Osiris board require a 64 bit slot
because they are 3v boards. It is rare to find 32bit PCI motherboards with 3v
support.
Hal Murray wrote:
> > Did 3V PCI ever take off
>
> Thanks for all the feedback. Sorry my question wasn't clear.
>
> There are two possible meanings for 3V. One is power. The other
> is the signaling level.
>
> First, the power stuff:
>
> The PCI connector has power pins for 5V, and 3.3V, and also a
> few more pins for IO power. They are either 3 or 5, depending
> upon the signaling voltage, the idea being that you can wire
> them to the supply rail for your IO pads and make a board that
> supports either 3V signaling or 5V, depending upon the power the
> motherboard supplies on those pins.
>
> The PCI connector has a plug that matches with a cutout on the
> board. The plug goes in either of two positions (turn the connector
> around), one for 5V signaling, the other for 3V. So in theory,
> you can make three types of cards. The normal card in wide use
> is 5V signaling, though they may only drive the outputs with a
> 3V CMOS driver. You can also make 3V only card by putting the
> cutout on the other end of the card. You can also make 3V/5V
> cards by cutting out both slots and maybe wiring the IO pad
> rail on your chip to the IO supply from the PCI connector.
>
> I've never seen any 3V or dual cards.
>
> The main question I was trying to ask was if anybody had seen
> any 3V or dual signaling level cards. If so, I might think more
> about taking advantage of that. Since I didn't see many
> encouraging responses I'll probably but this on the back burner.
>
> Some early systems didn't actually supply any 3.3V power. You
> can dance around that with an on-board regulator. I plan to
> ignore that. (But I'll check my systems first, just in case,
> and listen for tales of troubles with not-so-early boards.)
>
> Now for the signaling:
>
> The 3V signaling rules overlap the 5V rules enough so that a
> card that drives high to 3V will work in a 5V system. The
> catch is that some other card driving to 5V on a system that
> produces worst-case reflections might generate an 11V spike.
> "5V tolerant" is the critical term for that.
>
> The Spartan-II is 5V tolerant but doesn't have DLLs. The -IIE
> has DLLs, but doesn't tolerate 5V signaling.
>
> Since 3V systems don't seem to be very popular, I probably won't
> build a card expecting to find a 3V only slot.
>
> Several years ago, I put a scope on a system that had the connector
> pegs set for 5V. I never saw anything go over 3V. Obviously that
> depends upon what cards are plugged in. Somebody could add an
> old/evil card that really does drive to 5V.
>
> For hack/research systems it might make sense to use a FPGA that
> wasn't 5V tolerant on a card that could be plugged into a 5V system.
> You would have to remember to get out the scope before adding a card
> that hadn't been tested yet. I'm probably not desperate enough
> to get the DLLs that I will do this. (But I'm still scheming.)
>
> Thanks for the PLX suggestions. Their web site expects me to
> register before they give me data sheets so I'll put that on the
> back burner.
>
> Thanks for the heads-up about using DLLs on PCI clocks. Is
> that a clear don't-do-that, or just another worm for the list?
>
> --
> The suespammers.org mail server is located in California. So are all my
> other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
> commercial e-mail to my suespammers.org address or any of my other addresses.
> These are my opinions, not necessarily my employer's. I hate spam.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50378> Does anyone know of any existing designs like this - or work done on any? See the MISC section of http://fpgacpu.org/links.html for some starting points. Jan Gray, Gray Research LLCArticle: 50379
nahum_barnea@yahoo.com (Nahum Barnea) wrote in message news:<fc23bdfc.0212090828.5ddbf097@posting.google.com>... > Hi. > I am trying to debus a problem with a miss-behave DCM. > In > http://toolbox.xilinx.com/docsan/xilinx4/data/docs/lib/dsgnelcd50.html > > I see the meaning of status bits 0 and 1. > > I wonder if someone can reveal the meaning of status bits 7-2 ? > > ThankX > NAHUM The following may be of some help - http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=10972 http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=15594 http://direct.xilinx.com/partinfo/ds031-2.pdf Vikram.Article: 50380
Hal Murray wrote: > > >Is the downsampling filter a seperate chip, or is it just a core in the > >fpga? > > Classic downsampling in this sort of DSP/FPGA context is a neat trick > to get away with a less expensive analog filter. Suppose your signal > has a bandwidth of 1 MHz, so you need to sample at 2 MHz. But you also > need a filter that gets rid of everything over 1 MHz or it will get > aliased back to below 1 MHz. Brick wall filters are impossible to > expensive depending upon how close you get. If you build a reasonable > filter, it lets stuff through up to (say) 3 MHz. So you run your > A/D to 8 MHz, knowing that the filter has killed everything below > 4 HMz. Then you run a digital filter that throws away everything > below 1 MHz. Nyquist now tells you that you don't need that many > samples, so you can just throw away the ones you don't need. > > In the case that started this discussion, he wanted to make a 40 MHz > clock for the A/D, but he was starting with a 120 MHz clock. Seems > obvious that he could just throw away 2 out of 3 samples. There > may be something better to do, but I'm not smart enough to see it. > Might be something like you can get rid of some noise if you run > through a filter that throws away the bandwidth you don't need. Actually in this case downsampling is a poor alternative to running the ADC at the correct rate with an analog filter. It is *much* more difficult to run an ADC at 120 MHz than it is at 40 MHz. The ADC will use much more power at 120 MHz as well. The original question was about using a DLL to generate a 40 MHz clock from a 120 MHz clock. You don't need a DLL for that. You can just implement a divide by three. If you need a symetrical square wave to drive the ADC you can make a circuit that runs off of both phases of the clock without using the DLL. The digital circuitry should not add significant jitter to the clock. To answer Jamie's question about noise vs. sample rate, yes, typically faster ADC operation results in poorer performance in ADCs. Not necessarily due to clock issues, but just because the ADCs create more noise at higher rates. That is why the number of bits goes down as the sample rate goes up. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50381
Ralph Mason wrote: > > I have been thinking about a tiny stack based processor in verilog, much > like the KPSM (Pico Blaze). > > It seems like a stack based machine would be more suitable for this kind of > application because the instruction size is smaller, allowing more compact > code, there should be less multiplexing required leading to a smaller size > in a limited amouint of memory. You could program it in forth, which gives > you a fairly nice language to work in and easy to develop tools. > > Does anyone know of any existing designs like this - or work done on any? > Or is this an unfilled niche, or perhaps there is some fundamental error in > my thinking on the suitability of a tiny forth processor for these kind of > tasks. > > Thanks for any insights / ideas / pointers > > Ralph Yes, there has been much work done on Forth processors, both in custom chips and in FPGAs. You can find some info on this at http://www.ece.cmu.edu/~koopman/./stack_computers/index.html and maybe http://www.taygeta.com/forth.html I am crossposting this to the forth newsgroup where you will likely get a lot better response. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50382
As another old turd I can also recommend doing it the way all us old timers did. Grab some high quality tech color pens, at least a half dozen colors say using the industry std red/green/blue/black for the dif/poly/met1/cuts layers and a few others for change. Start drawing on fine gridded paper, & get decimal paper, not the useless imperial US rubbish. There are some intro books for novice layout designers, the Addison Wesley VLSI series, also a Tanner based LEdit book, & Moto wrote one too for the pro "layerouters", but all of these are now dated as are we. The really good thing abouts pen/paper is that you can really learn to appreciate the fine art of polygon packing, get close to the max density. To do a big multiplier, you really only need to do the unique cells that must abut say a 4 by 6 array may contain all the same info that a bigger array, possibly only a dozen cells. Do not attempt this flow on Wallace trees! When you have mastered that, you are set to layout all sort of wonder chips, memories, memories, plas, roms, more memories & datapaths and so on. If you want to be lazy, there are a few layout tools at little or no cost, but most of these are no match for the mighty pen paper. If you want to save paper, H2? pencils & erasers are good too, but 1 color layout gets very tedious very quick unless you limit to just major layers and varing stipple patterns. You can only erase a few times before the paper breaks so be prepared to redo a few times. When you get really good, you won't even need the pen/paper, you can just do it in yer noggin, and when you have figured the basic placements, capture with one of the above tools. After all that you will be set for lifetime employment!Article: 50383
Some time back, a company called LogPoint was offering an alternative to floating point arithmetic, based on logarithms, and depended on a fairly efficient float to log conversion. (I had discussions with them, at least 5 years ago) I seem to remember that the LOG wizard was a guy by the name of Lester Pickett. http://www.mjourney.com/news/News_from_Greece/632.Log_Point.shtml unfortunately, this seems to be dead: www.logpoint.com Have a look at patent 5197024 at www.uspto.gov for all the details. Philip On Fri, 22 Nov 2002 12:51:19 -0000, "Tim Nicolson" <t.nicolson@signal.qinetiq.com> wrote: >hi all. > >I'm currently implementing an image processing algorithm in hardware. > > ...... > >Unfortuately, adding extra terms to the poly increases the accuracy slowly. > >So.... Does anyone know of a better way of computing the logarithm of a base2 fp number? > >Thanks very much for your time. > >Tim > > >Tim Nicolson >Reseach Engineer >QinetiQ >Malvern >UK Philip Freidin FliptronicsArticle: 50384
> It seems like a stack based machine would be more suitable for this kind of > application because the instruction size is smaller, allowing more compact Thats perfectly rigth. Things are a lot easier with a stack architecture (but also slower since you need more cycles for basic operations than on a RISC CPU). > Does anyone know of any existing designs like this - or work done on any? I haven't worked on a Forth processor, but on a Java processor. The JVM (Java Virtual Machine) is also stack based. I've found that a CPU with the basic JVM instructions implemented in 'hardware' easy fits in a medium sized FPGA (like ACEX 1K30). The advantage of Java over Forth is (in my opinion) that the language is widle used and you get a rich toolset for free. I don't know if Forth is still used for real world applications. Would like to hear about it. If there is a new wave in the Forth direction I have to change my CPU :-) Martin -- JOP - a Java Optimized Processor for FPGAs. http://www.jopdesign.comArticle: 50385
Mike Treseler <mike.treseler@flukenetworks.com> wrote: > Laurent Gauch, Amontec wrote: > > >> >> You can assign pin in the VHDL via attributes, but this is not a good idea. >> > > > I agree. It is much less trouble to do pins with the place & route tools. > Use the GUI or write a tcl script. Depends on. If you are attempting to build component modules for some already fixed hardware system (e.g. some development system with already connected external RAM or A/D converter), you want to have the constant parts already fixed, rather than always reassigning them (error prone) each time you instantiate that component. You could write a tcl script for that, but to me it looks more natural to embed such constants into the functional source. You give up portability because that core probably won't work anymore with a different synthesis system, but it is bound to a certain hardware anyway already. Holger -- Please update your tables to my new e-mail address: holger.veit$ais.fhg.de (replace the '$' with '@' -- spam-protection)Article: 50386
Spam Hater <spam_hater_7@email.com> writes: > On 09 Dec 2002 08:44:48 +0000, Martin Thompson > <martin.j.thompson@trw.com> wrote: > > >Spam Hater <spam_hater_7@email.com> writes: > > > >> A statement like: output <= input; will generate a 'feed > >> through net warning'. All it's telling you is that there's no > >> "logic". Ignore it. > >> > > > >Unless it's a clock feeding something else later, and you use the > >source clock as well... > > > > Martin, > > Everything you said is true, but... > > He's using FPGA Express. He will get a (another) bevy of warning > messages if he tries to use a net as a clock, or a clock as a net. > Ahh, I haven't used that, so I wasn't aware of those messages. Thanks! MartinArticle: 50387
hmurray@suespammers.org (Hal Murray) writes: > In article <3DF552B6.95F53F2D@andraka.com>, > Ray Andraka <ray@andraka.com> writes: > > >You generally end up needing a ucf in addition to your VHDL, even > >if youhave constraints in the VHDL. I put my pin assignments in > >the UCF, and I think that is fairly common in the industry. > > Thanks. > > How do you keep the PCB and UCF in sync? What if you make a last > minute change to the board or the chip pinout? > > Is there a script that makes (fixes?) one from the other? Or do > people just do it by hand and be (very) careful? > If you use the Mentor Expedition tools, there is an add-in which does just this for you in an automated fashion, using the output of the P&R tools from various FPGA vendors. It then rewires your schematic so that the pin names and nets match up as they used to. Otherwise it's down to care and attention or DIY scripting (which I have done also!) Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 50388
hmurray@suespammers.org (Hal Murray) wrote in message news:<uv7obvfao3jk22@corp.supernews.com>...
> I'm scheming about building a hobby/hack project that
> needs an FPGA on a PCI card. Volumes will be very low.
>
How low is the volume going to be?
Are you planning to make only one PCI card, or is it going to be more
than that?
If you only need one, buy one from Insight Elctronics for $250,
although you will need a PCI IP core (More about this later.) to use
the board.
> My straw man is Spartan-II. Even with a big one, the
> cost of the PCB will be more than the cost of the FPGA.
>
From my experience dealing with PCI, avoid Altera devices
because the lack of multiple FFs per IOE makes it hard to meet Tval
(Tco), and their floorplanner is broken compared to Xilinx.
The floorplanner issue of Altera makes it hard to meet Tsu.
> Is it reasonable to get away with only 4 layers? I'm thinking
> of using a PQ208, dedicated layers for 3.3V and GND, and filling
> the top layer inside the pad ring with copper for the 2.5V core
> power "plane".
>
Although I don't know much about PCBs, the PCI specification
expects the PCI cards to be at least a 4-layer PCB.
However, there are some very low cost PCI cards that are 2-layer PCBs
(i.e., A $10 PCI Ethernet card sold at a mom and pop computer dealer),
but that, I am told, violates the PCI specification.
Reading the specification, it says that PCI allows "split
power plane" of 5V island and 3.3V island.
You can probably add a 2.5V island for Spartan-II's core power supply.
> I think everything else on the board will run at 3.3V, or I
> can fudge it. There won't be much routing so if the PCI works,
> I should be able to get away with 2 signal layers.
>
> Does that seem reasonable? Is there a better approach I've
> missed?
I don't see why you cannot use a 4-layer PCB.
Most PC motherboards other than server/workstation class motherboards
use 4-layer PCBs for cost reasons, and they seem to be doing okay with
that.
>
>
> I'm still keeping an eye open for an existing prototype board
> that I can adapt to what I need, but I haven't seen one that
> looks close yet. If I have to build a daughter card to plug
> into an existing card, I might as well do the whole thing and
> get exactly what I want.
As I have said several times within this newsgroup, a year
ago, I purchased Insight Electronics Spartan-II 150 PCI prototype kit
from Insight Electronics to test a PCI IP core I developed.
The card had Spartan-II XC2S150-5CPQ208 with 8MB of SDRAM on it, and
sold for only $145.
That price might have been cheaper than doing your own board.
Unfortunately, that board was discontinued, but was re-released about
six months ago as Spartan-II 200 PCI prototype kit.
The new board has Spartan-II XC2S200-xCFG456 (speed grade -5C or -6C)
with 8MB of SDRAM on it, but the price was raised to $250 ($275 with a
parallel port JTAG cable.).
One of the problem of these PCI cards is that, Insight
Electronics assumes that you will be using Xilinx LogiCORE PCI which
costs $2,000 for a single project license, or $5,000 for a regular
license.
Obviously, $2,000 will be out of question for a hobby project.
Instead, you can use Opencores.org PCI IP core or develop your own PCI
IP core like what I did, but doing your own PCI IP core takes several
months.
Opencores.org PCI IP core has been available for some time, but I
haven't heard too many people actually using it.
Having seen the RTL code of it, I will say that it will be pretty hard
to understand it because the authors have really gone into
handcrafting the design (i.e., Looks more like gate level rather than
RTL).
>
>
> Did 3V PCI ever take off? Can I get PC motherboards and/or
> a reasonable collection of plug in cards? That would allow
> using a Spartan-IIE (Virtex) with DLLs.
>
> I'm assuming it flopped since I don't remember seeing ads
> for mother boards nor do I remember seeing cards that had
> the second slot. I'm assuming lots of people would build
> them if there was any interest.
>
> Do people who want to use 3V PCI just use a PCI-PCI bridge chip?
> Or another FPGA?
No, 3.3V PCI never took off because there were already so many
5V PCI cards made that adding separate 3.3V PCI bus would have added
cost for no reason.
Spartan-II has 4 global clock buffers with 4 DLLs, but in PCI, you
cannot use DLL because in 33MHz PCI, clock can be stopped, at least
according to the specification.
But for other non-PCI portions of your circuit, you can use a DLL
assuming that the input frequency is at least 25MHz, and the clock
isn't derived from PCI's clock.
>
>
> Anybody have a list of PCI-some-simple-bus type chips?
> I'm only interested in ones that are cheap and reasonably
> available in small quantities.
I believe PLX sells several prototype boards for several
hundred dollars with their chips.
Using those might be easier than dealing with a PCI IP core.
Kevin Brace (If you want to respond to what I wrote, I prefer if you
will do so within the newsgroup.)
Article: 50389richard.crewe@celoxica.com (Richard Crewe) wrote in message news:<3bbf9d7a.0212090722.39e2aebe@posting.google.com>... > In your code, Sub is a rom. > > You cannot access multiple indices of a rom array on the same clock cycle. But that's the problem only with DK1, I wonder it's working correctly with DK1.1 Does DK1.1 supports multiple access to ROM in a single clock cycle?Article: 50390
hmurray@suespammers.org (Hal Murray) wrote in message news:<uvanjpn5c2m496@corp.supernews.com>...
>
> I've never seen any 3V or dual cards.
>
> The main question I was trying to ask was if anybody had seen
> any 3V or dual signaling level cards. If so, I might think more
> about taking advantage of that. Since I didn't see many
> encouraging responses I'll probably but this on the back burner.
>
Although you will probably never see a 3.3V PCI only card at
CompUSA (Or any other computer store.) because so many people will
return the card complaining that they cannot insert the card into
their PCI slots (Of course, the customers' 5V PCI slots.), I have seen
many more universal PCI cards sold at CompUSA than a few years ago.
In fact, more than third of SCSI, USB, and FireWire PCI cards I saw
displayed at their peripherals section were universal (I was at
CompUSA yesterday.).
However, there is still significant number of 5V only PCI cards being
sold.
I heard that PCI 2.3 has banned 5V PCI only cards, and requires at
least a universal PCI card to call the PCI card "PCI 2.3 compliant."
The problem of implementing a universal PCI card with SRAM
FPGAs is that you need to detect the +VIO pin's voltage first to see
if the PCI slot is 3.3V or 5V, and load the 3.3V PCI or 5V PCI bit
stream, accordingly (Yes, you need to have two separately bit stream
images, one for 3.3V PCI and the other one for 5V PCI.).
That might add significant cost, since XC18V02 Configuration PROM
costs about $22 per chip, costing as much as a large Spartan-II.
Knowing that you need two bit stream images to do a true
universal PCI with Spartan-II, if you look at Insight Electronics
Spartan-II PCI card (150 or 200), you will see that the PCI card edge
is universal, but the card has only one Configuration PROM.
Technically that's a violation of the specification, but considering
that the card is for prototyping, and not for production, it is not a
big issue.
> Some early systems didn't actually supply any 3.3V power. You
> can dance around that with an on-board regulator. I plan to
> ignore that. (But I'll check my systems first, just in case,
> and listen for tales of troubles with not-so-early boards.)
>
>
If I were you, I will add a voltage regulator on board because
it shouldn't cost more than a few bucks.
I rather not take a chance on whether or not the PCI slot I am putting
in the card will have the 3.3V power supplied to the card.
The Insight Electronics Spartan-II 150 PCI card has the voltage
regulator with an option to ignore and use PCI slot's 3.3V power.
> Now for the signaling:
>
> The 3V signaling rules overlap the 5V rules enough so that a
> card that drives high to 3V will work in a 5V system. The
> catch is that some other card driving to 5V on a system that
> produces worst-case reflections might generate an 11V spike.
> "5V tolerant" is the critical term for that.
>
I hope Xilinx and Altera dealt with that 11V issue correctly.
> The Spartan-II is 5V tolerant but doesn't have DLLs. The -IIE
> has DLLs, but doesn't tolerate 5V signaling.
>
Yes, Spartan-II has 4 global clock buffers with 4 DLLs.
> Thanks for the PLX suggestions. Their web site expects me to
> register before they give me data sheets so I'll put that on the
> back burner.
When I registered, a local sales representative sent me an
E-mail.
Still, you should register with them, and take a look at their
datasheets.
>
> Thanks for the heads-up about using DLLs on PCI clocks. Is
> that a clear don't-do-that, or just another worm for the list?
I know some people who will say, "In 33MHz PCI, the clock can
be stopped, but it doesn't happen in practice."
Since the specification say the clock can be stopped, and the clock
can be below 25MHz, you really shouldn't use feed the DLL with PCI's
clock.
Why not follow the specification strictly, so that you might have
potentially fewer compatibility problems?
If you really have to use the DLL, why not put an independent clock
source on the PCI card, and feed that clock to the DLL?
Kevin Brace (If you want to respond to what I wrote, I prefer if you
will do so within the newsgroup.)
Article: 50391This is a multi-part message in MIME format. --------------3F8A5C29A73C268901D6004A Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Dear Ralph, Take a look at the work of DCT and their Lightfoot Processor. http://www.dctl.com/ They have certainly shown that the stack based architecture will result in significant program memory savings. As with many things, it may not yield the highest performance, but engineering is about having adequate performance and then keeping costs under control. In this case, we are interested in the total cost formed from the processor and the program memory. Lightfoot was developed with Java in mind but also supports C-code. Not sure if they support Forth directly. Ken ChapmanArticle: 50392
Hello, I have made a simple VHDL program that have three VHDL modules (WAVE_GEN, CONTROLLER, RAM512). I have in my WAVE_GEN code "wait for 40 ns;". The problem is that when I try to generate a symbol ISE tells me " Wait for statement unsupported". I also have made a "TOP" VHDL module that instantiate the three previous modules and interconnects them with signals. This "TOP" module is for conecting the waves generated by WAVE_GEN to the other VHDL modules. My problem here is that when I simulate this TOP module I don't see any signal, etc. in Modelsim window because this "TOP" module doesn't have ports. How can I see the internal signals?? Thanks a lot and regards, JaviArticle: 50393
thanx for all the answers it seems that it is a lot more complicated than I hoped it would be. we have dozens of old-fashioned isa vga cards here so I thought it is a cheap way of getting a screen output from an FPGA. are there cheap RAMDACs that can be used for this purpose? probably interfacing them is easier ThomasArticle: 50394
rickman wrote: > > Ralph Mason wrote: > > > > I have been thinking about a tiny stack based processor in verilog, much > > like the KPSM (Pico Blaze). > > > > It seems like a stack based machine would be more suitable for this kind of > > application because the instruction size is smaller, allowing more compact > > code, there should be less multiplexing required leading to a smaller size > > in a limited amouint of memory. You could program it in forth, which gives > > you a fairly nice language to work in and easy to develop tools. > > > > Does anyone know of any existing designs like this - or work done on any? > > Or is this an unfilled niche, or perhaps there is some fundamental error in > > my thinking on the suitability of a tiny forth processor for these kind of > > tasks. > > > > Thanks for any insights / ideas / pointers > > > > Ralph > > Yes, there has been much work done on Forth processors, both in custom > chips and in FPGAs. You can find some info on this at > > http://www.ece.cmu.edu/~koopman/./stack_computers/index.html > > and maybe > > http://www.taygeta.com/forth.html > > I am crossposting this to the forth newsgroup where you will likely get > a lot better response. > http://www.UltraTechnology.com/chips.htmArticle: 50395
Hello!
I want to use Synopsys MemPro (for Windows) in order to use a memory
module for my design. My ultimate goal is to download it in a Virtex and I
am not sure if it can be done. Does anyone know if it is possible? I am
using Xilinx's ISE 4.2i and I do not know if it will work. Will I need
additional libraries or something else?
Thank you very much!!!
Dimitris.
Article: 50396Thomas Buerner <buerner@lrs.eei.uni-erlangen.de> wrote: : thanx for all the answers : it seems that it is a lot more complicated than I hoped it would be. : we have dozens of old-fashioned isa vga cards here : so I thought it is a cheap way of getting a screen output : from an FPGA. : are there cheap RAMDACs that can be used for this purpose? : probably interfacing them is easier The PCI bridge team on www.opencores.com has a sample VGA application, doing 12 bit colors (4 bit for each color) with simple resistor DACs. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 50397
Hi, The syntax for the area constrains is like this. INS "sub_Module_A" = X10Y10:X20Y20; Here sumb_Module_A is instantiated with in the Module_Top. If i want to give area contrain for a top module which is has no sub-Module, then how should the instantiation name will be .???? Thanks in advance Regards, MuthuArticle: 50398
Roelf Toxopeus wrote: >> Yes, there has been much work done on Forth processors, both in custom >> chips and in FPGAs. You can find some info on this at >> >> http://www.ece.cmu.edu/~koopman/./stack_computers/index.html >> >> and maybe >> >> http://www.taygeta.com/forth.html >> >> I am crossposting this to the forth newsgroup where you will likely get >> a lot better response. >> > > http://www.UltraTechnology.com/chips.htm I made a tiny Forth processor to fit into a small FPGA, you can find it on http://www.jwdt.com/~paysan/b16.html There's also Gerber data for a demonstration board with an Altera Flex 10K30E. Today, I suggest using the new Cyclones, because the smallest one is very cheap, and the configuration devices are also not that expensive anymore. -- Bernd Paysan "If you want it done right, you have to do it yourself" http://www.jwdt.com/~paysan/Article: 50399
In comp.arch.fpga Bernd Paysan <bernd.paysan@gmx.de> wrote: : There's also Gerber data for a demonstration board with an Altera Flex : 10K30E. Today, I suggest using the new Cyclones, because the smallest one : is very cheap, and the configuration devices are also not that expensive : anymore. Are those Cyclone/Configuration parts really out in the wild? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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