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A carry save multiplier does not use a carry chain at all until the final addition. That is, each individual bit's carry-out is used as the next stage's carry-in. -Stan "Jack" <jack.liu@rmc.ca> wrote in message news:3DDA8A4C.AAB3D07E@rmc.ca... > Hello. > Trying to design multiplier using carry save adder and 4:2 compressor on > a Xilinx Virtexe. The optimized synthesis use LUT for all the functions > instead of carry chain. Is anyone know how to force the Synthesis tool > to implement the logic function using the carry chain? > > Thanks > > Jack >Article: 49726
I've released a major upgrade for HDLmaker, available from http://www.polybus.com/hdlmaker/users_guide/ HDLmaker generates hierarchical Verilog & VHDL as well as simulation and synthesis scripts, as well as Xilinx and Altera contraint files. HDLmaker is open source and free under a BSD style license. The new features are 1) Large project support, HDLmaker can now operate across multiple directories 2) Xilinx Virtex2 and Spartan2 has been added 3) Altera Stratix support has been added 4) Mixed language project support has been added Enjoy, Josh Rosen, Polybus Systems CorpArticle: 49727
The reason for doing a carry save adder is to defer the add carry to the last
adder in the tree. Normally this is done in order to permit construction of
just one fast adder. The speed of an adder tree is limited by the speed of
the propagation through any path in the tree, and the worst case paths are
from the lsb of an input to the msb of the output. In other technologies, a
ripple carry adder is slower than fancier carry look-ahead schemes, but the
fancy schemes take up considerably more logic. By deferring the carry to the
last stage, one only has to build one of these expensive adders. The rest of
the adders have the same cost as the ripple carry adder but without the ripple
propagation. So by doing this, you speed up the adder tree as if all the
adders were the more expensive fast adders.
Now enter the FPGA, with its dedicated adder carry chains (these actually do
have some carry look-ahead built in, but it is hidden from the user). In the
case of the FPGA it is very hard, impossible in many cases, to build an adder
that is faster than the built in adder function because the dedicated
resources are so much faster than the general purpose routing. Since that
ripple adder is the fastest one can build in the fpga, there is no penalty (in
fact there is an advantage) to using them through out the adder tree rather
than only at the final add. The advantage is that by doing this, all the
carry logic is put on the dedicated resources, so you essentially get the
carry half of all the 3:2 adders for free. If you decided to build an adder
without using the chains (including the Carry Save type), you need two LUTs
per full adder instead of the one because you can't take advantage of the
dedicated carry logic, so not only do you get no speed advantage in an FPGA by
using a CSA tree, but you also get soaked for twice the resources, and in fact
you get a speed degradation due to the irregular routing.
The bottom line is that carry save adder trees DO NOT MAKE SENSE for FPGAs
that have dedicated adder resources.
Stan wrote:
> A carry save multiplier does not use a carry chain at all until the final
> addition. That is, each individual bit's carry-out is used as the next
> stage's carry-in. -Stan
>
> "Jack" <jack.liu@rmc.ca> wrote in message news:3DDA8A4C.AAB3D07E@rmc.ca...
> > Hello.
> > Trying to design multiplier using carry save adder and 4:2 compressor on
> > a Xilinx Virtexe. The optimized synthesis use LUT for all the functions
> > instead of carry chain. Is anyone know how to force the Synthesis tool
> > to implement the logic function using the carry chain?
> >
> > Thanks
> >
> > Jack
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49728What curses do you find produce the most stable code? :) Tony "strut911" <strut911@hotmail.com> wrote in message news:4379d3e0.0211191611.13f45b76@posting.google.com... > Hi. > Good luck on your project. It is definitely a worthwhile investment if > you want to get a jump start on FPGAs. You may want to consider a few > things before you start, though. I am not sure about Altera's free > tools, but this should be a consideration if you are doing this out of > your own pocket. I am a Xilinx user and know that the Webpack, > although it has a few sore spots, is quite popular with the hobbyist > electronics community. The design flow will be quite important and you > will want to keep it low cost. You might also want to have an FPGA > project in mind as you design the board, because building the board is > only half the fun. The rest of the "fun" is writing the code, > simulating it, debugging it, cursing at it, and then finally seeing it > work. Good luck. > strut911Article: 49729
> > First, you need to go back and revisit the data sheet. I believe you will find a > minimum DLL input clock frequency of 25 MHz there. It will work at lower > frequencies, but is not guaranteed over voltage, temperature and process...in other > words if you put this into production I guarantee you'll have failures. > > Xilinx originally said that it was safe to go directly between the clock domains, > however experience dictates otherwise. If the DLL output jitter plus intrinsic > clock tree skew in the part are less than the minimum propagation time between the > registers, then you are OK. Since there is no minimum propagation time specified, > you already have a problem if there is *any* jitter, but practically speaking there > is a minimum prop time. For a jitter-free clock coming in, and matched clock > distribution, you can go directly between....but: The incoming clock jitter is > seldom small, and if you have single ended outputs on the same bank as the clock > you can introduce considerable jitter on the clock through threshold modulation due > to switching I/O. Also, the clock distribution is not closely matched unless you > load each very similarly in each column (you'd have to do this by hand, as the > placer won't even come close). We saw this happen soon after Virtex first came > out. > > Instead, I recommend that you be very careful about how you transfer data across > the 1x/2x clock boundaries, as the edge can fluctuate by several hundred ns > relative to the edge in the other domain...enough to cause mis-clocking. Positive > edge to negative edge should be fine > Thank you very much for your suggestion. I'll design the 2X clock domain to work on the falling edge, whereas the 1X domain work on the rising edge. > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 49730
Anup Kumar Raghavan <anup@itee.uq.edu.au> wrote in message news:<3DDA37D8.293147C4@itee.uq.edu.au>... > Hello, can someone point me to how I will be able to instantiate a > Virtex II - IOB component for implementing some logic in the IOB and > use the available registers? I use Leonardo Spectrum for Synthesis and I > know I have an option to Map registers in IOBs. But I want to be able to > do it manually in a vhdl file. > > Thanks > > Anup The foll. should help - http://support.xilinx.com/publications/products/v2/handbook/xc2v_vhdl.zip Vikram.Article: 49731
Hi,
In a state machine, since i want a RESET state (till the reset is
released,it has to be in this state)i coded as below.
//combinational portion to decide next state
case(present_state)
RESET:
begin
if(reset)
begin
next_state = state1;
end
else
begin
next_state = RESET;
end
end
.
.
.
endcase
// Sequential logic
always ....
begin
if(!rst)
begin
present_state <= RESET;
end
.
.
.
end
Is the inclusion of Asynchronous RESET signal in the combination
portion is the correct way?
Best regards,
Muthu
Article: 49732zumbita00@yahoo.es (Pepito Perez) wrote in message news:<441d2f16.0211191028.1daf4384@posting.google.com>... > Hi all !! > > This is my first post in news, i read it sometimes, but i am a > newbie. I have been looking to develop a board for Altera's APEX, and > searching the group, i only find people doing their businesses. I'm > going to take it as a project, and i think i would need some help from > the group. Also say that if the project goes on it'll become a GPL > (http://www.gpl.org) project, so every novice it this kind of stuff > could get more experienced in FPGAs (like my case). > > > Also, for that people that don't want to wait.... > ...can find a FREE development Xilinx board at > http://www.iearobotics.com/personal/juan/doctorado/jps-xpc84/jps-xpc84.html > > Thanks OpenCores, even though focusing mainly on free IP Cores, also has various FPGA proto board projects. Visit www.opencore.org for more information. It might be a good place to share your work with others. Cheers, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - NEW ! 5 New Free IP Cores this months (so far :*) FREE IP Cores --> http://www.asics.ws/ <--- ----- ALL SPAM forwarded to: UCE@FTC.GOV -----Article: 49733
On 19 Nov 2002 21:37:29 -0800, muthu_nano@yahoo.co.in (Muthu) wrote: >Hi, > >In a state machine, since i want a RESET state (till the reset is >released,it has to be in this state)i coded as below. > >//combinational portion to decide next state > >case(present_state) >RESET: >begin > >if(reset) > begin > next_state = state1; > end >else > begin > next_state = RESET; > end >end >. >. >. >endcase > >// Sequential logic > >always .... >begin > if(!rst) > begin > present_state <= RESET; > end >. >. >. >end > > >Is the inclusion of Asynchronous RESET signal in the combination >portion is the correct way? > >Best regards, >Muthu No; as this is an async reset, the flops will be reset till it is released so no next state will be loaded during reset and you don't need to check reset signal in the next state calculations. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 49734
Hello, I need to draw several schems consisting from logic gates for documentation. What is a simple and user friendly tool with trial?Article: 49735
We supply parallel port FPGA programmers compatible with Altera Byteblaster programmers at reasonable prices. We ship worldwide. All our products carry a warranty. We also supply support relating to programming of Altera devices. You can purchase these online at our website: http://www.logicblock.com We also plan to release a USB version of a general purpose JTAG programmer Mail us at sales@logicblock.com for any special requests or bulk discounts.Article: 49736
Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote: > hamish@cloud.net.au writes: >> Why wouldn't you buy the tools if using such a high-end part? > 1. Because I'm a cheap bastard. > 2. Because it's a low-end Virtex II Pro, not a high-end. IS there such a thing? Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 49737
Steve Casselman <sc@vcc.com> wrote: >> Nor is the V2Pro. It's a lateral move from the V2, >> kind of like the move from Virtex to Virtex-E > > I have to disagree the Virtex E just a different mix of the same stuff. > The V2Pro adds Gbit transceivers and hard processors I think that is a big > difference. True, but it didn't do much (anything?) for the core logic. It seems that most of the fuss is about high speed transceivers and the like. That's fine if you have the application for it, but everyone can benefit from more speed ... Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 49738
Hello, I'm trying to synthesize a DW8051 core from Synopsys for Xilinx VIRTEXE V1000EBG560 FPGA. The original VHDL source files are encrypted and I must use a Synopsys tool (it is called "CoreConsultant" or "Synopsys Reuse Tool") to configure the design for my FPGA. The configuration passed without any errors but I got about 400 different warnings (too many to describe them here). As result the CoreConsultant generates a hardware-specific VHDL netlist of the 8051. The netlist contains a lot of LUTs (over 2000), that represent a big part of the logic of the design. Unfortunately, the CoreConsultant did not insert any INIT attributes for those LUTs. So, they are all black boxes, without any contents and I'm not able to place-and-route the netlist. I'm not very experienced with that. So, I don't know, how to solve the problem on my own. If you have any hints or suggestions or if you are even experienced with the DW8051, I would be glad, if you could help me. Regards Erik FischerArticle: 49739
"no_spam" <uqpprabh@dingo.cc.uq.edu.au> schrieb im Newsbeitrag news:aregoe$h0i$1@bunyip.cc.uq.edu.au... > Hi, > > I am after storing around 1000 samples from a 12-bit ADC on the spartan-II > dual port blockram. Inorder to configure the dual port ram as a single port > block ram (256 x 16), i declare the component in vhdl as :- It may be a better approach to use 3 BRAMS in 1024x4 configuration to construct your RAM. Its more area efficient, and doesnt need MUX/Chip select logic, wich would make it slower. -- MfG FalkArticle: 49740
"Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it> schrieb im Newsbeitrag news:mwxC9.18087$Ka3.484296@twister1.libero.it... > Now all simulates nicely, but some recent discussions read on this > newsgroup gave me some thoughts. I write the block RAM in a "sequential" > way; the address is generated by a counter, clocked by the same signal > that drives the RAM write clock. > > In the ModelSim simulation, I see that the address change is almost > simultaneous to the write clock (I know very few of FPGAs yet, but I > think this is a 'magic' done by DLLs, right?). However this doesn't No, its just the behavious of a normal synchronous circuit. What you see is a zero clock to output time, which is only haapening in a plain behavioural simulation (palin VHDL) Do Post-Mapping or Post-Place&Route Simulation and you will see that is takes some ns for the counter from the clock edge to advance to the next state. > generate a timing error/warning. Is this situation correct or I'll go > into big troubles sooner or later? > > Note - if I use both clock edges, one for memory write and one for > address increment, I go far below my needed performances (by the way: > why?). This is not required. Just do a standard synchronous design on one clock edge. It will work fine. -- MfG FalkArticle: 49741
Does anyone know if Foundation 2.1i is supposed to run on Windows 2000? I'm unable to run the implementation tools after synthesis due to an error: Pcm Automation caused an exception, exit code 80010105 Pcm The server threw an exception The Xilinx answers database says that 2.1i was released before Windows 2000 and was never tested, but that's all. I'm trying to implement an XC4003E-PC84 design, which is not supported by ISE 5.1i. (Actually, it's not clear that this device is supported by Verilog synthesis in 2.1i either, but that's a separate problem.) Thanks for any replies -EwanArticle: 49742
milne@egenera.com (Ewan D. Milne) writes: > Does anyone know if Foundation 2.1i is supposed to > run on Windows 2000? I'm unable to run the implementation > tools after synthesis due to an error: > > Pcm Automation caused an exception, exit code 80010105 > Pcm The server threw an exception > > The Xilinx answers database says that 2.1i was released > before Windows 2000 and was never tested, but that's all. > > I'm trying to implement an XC4003E-PC84 design, which is > not supported by ISE 5.1i. (Actually, it's not clear that > this device is supported by Verilog synthesis in 2.1i > either, but that's a separate problem.) > > Thanks for any replies > > -Ewan IIRC, I have used Foundation 3.1i under Windows 2000 for a XC4006E. Also I remember that there were some problems with incompatible DLLs from Microsoft, MSVCRT.DLL, which were installed with MS DevStudio 6.0. But I'm not sure. Currently I'm using Foundation 3.3i, Win2k SP3, and this one still supports the XC4000E. Thomas HellerArticle: 49743
Hi, The motherboard printer port in my PC is used by some hardware, so I have to connect the Parallel Cable to another printer port on an PCI I/O card. The port is EPP etc, but - as I suppose for most PCI printer ports - does not use the original printer port addresses (378,etc.) but some other in PCI space. The Impact programmer does not locate the cable. The cable works OK when connected to standard printer port. Does anybody use the Parallel Cable with PCI printer port? Does it work at all or maybe there are some hints to make it running? TIA DziadekArticle: 49744
Vikram wrote: > > I am not sure if this will help, but try putting the following in your > UCF file for the input clock "GCK0" - > > NET "GCK0" LOC=p80; > NET "GCK0" TNM_NET="GCK0"; > TIMESPEC "TS_GCK0" = PERIOD "GCK0" 48 MHz HIGH 50 %; > INST DLL_INST LOC="DLL0"; > > Vikram. Hello, Thanks for the answer and patience. I have put these lines to the ucf-file, unfortunately it doesn't work. NET "GCK0" LOC=p80; NET "GCK0" TNM_NET="GCK0"; TIMESPEC "TS_GCK0" = PERIOD "GCK0" 48 MHz HIGH 50 %; # For CLKDLL INST XLXI_10 LOC="DLL0"; # For IBUFG INST XLXI_16 LOC="DLL0"; # For BUFG INST XLXI_11 LOC="DLL0"; If i open the ucf-file with the Constraint Editor, The GCK0 will not be detect than as Clock net. But the Connection from CLK0 (or CLK2x) to BUFG is detecting as Clocknet. I think, that it should be not so. If i add this lines: NET "xlxn_20" TNM_NET = "xlxn_20"; TIMESPEC "TS_xlxn_20" = PERIOD "xlxn_20" 48 MHz HIGH 50 %; then it doesnt work (no clk-signal) I'm using now the CLK0 output from CLKDLL. Because i will be glad, if some clocksignals exits the Output CLK0. I will be glad, if i can get more informations or answers. with kind regards StefanArticle: 49745
Hello, I need to program an Altera Flex10k under Linux (embedded LFS with very few resources). I have heard of the Bitblaster abilities for simple PS programming, but the cable is too big (and expensive). With the Byteblaster (that can be soldered directly on the board), it seems that the only solution is to use Max+2... much too heavy for a simple programmer. According to what I have read on the web, the "Jamplayer" should be a good solution... But I didn't find that soft anywhere ! If you know a free open-source software, or at least the protocol to write into the FPGA, you could help me a lot ;-) Vincent.Article: 49746
Hello, i'm beginning to pactice with xilinx device. I' ve build xilinx download cable and i'm trying to program a CPLD XC9536. When i use Impact, the application connects with the cable but don't program (don't get ID,too)the device and give me an error (Boundary scan fails at bit position '1' ....). I've check my cable but the connections seem correct. In the PCB of my CPLD, i've connected all the Vcc (+5V) and Gnd and also the 6 pin of Jtag header to XC9536, for the moment these are the only connection i made. So i've 2 questions: 1)It's normal that XC9536 becomes hot when connected to vcc (also when the download cable is not connected)? 2)what could be the problem if the download cable is built correctly? Thank you all and sorry for my English. GiovanniArticle: 49747
Many thanks to Ben, Muzaffer and Joe, What a great bunch you are, generously offering your solutions ! With your help I've solved the problem now using the ideas of Muzaffer and Joe. I'm sure yours would work too Ben although I'm a bit frightened of the tool directives. However, it would have been the only solution if I hadn't been able to use the clock-back-on period to reset the falling edge signal. Hope I can do the same for you all some day. Regards PhilArticle: 49748
Thanks Georgi, I guess this is a sort of gate-delay monostable rather like Ben's. Good idea. Regards PhilArticle: 49749
"Alderan" <renzo.busonera@tin.it> schrieb im Newsbeitrag news:t6NC9.31978$744.1182469@news1.tin.it... > I've check my cable but the connections seem correct. > In the PCB of my CPLD, i've connected all the Vcc (+5V) and Gnd and also the > 6 pin of Jtag header to XC9536, for the moment these are the only connection > i made. > So i've 2 questions: > 1)It's normal that XC9536 becomes hot when connected to vcc (also when the > download cable is not connected)? Yes, it get warm. But not so hot that you can touch it. > 2)what could be the problem if the download cable is built correctly? Ahh, you build it on your own? Hmm, many things can go wrong. Check the cable again. Check all connections. In Impact you have the possibility to do some JTAG debuging, where you can switch the signals TMS/TCK/TDI by hand. Do this and measure the signals on the board to see that the connection is working, also measurw the direction fro TDO to IMPACT. If this works OK, a very nasty problem can be glitches on TCK, cased by bad signals from the printer port using long cables. For a workaround of thisproblems, use two schmitt-trigger (74HC14) in series before the TCK signal, which comes from the LPT. Regards Falk
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