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"Stefan Kulke" <kulke@informatik.tu-cottbus.de> schrieb im Newsbeitrag news:arg4f1$ba7$1@Maust.bbone.tu-cottbus.de... > I'm using now the CLK0 output from CLKDLL. Because i will be glad, > if some clocksignals exits the Output CLK0. > > I will be glad, if i can get more informations or answers. Connect clk0 and clkx2 from the DLL to output pins to see if there are signals present. Also connect the reset and LOCKED signal to output pins. -- MfG FalkArticle: 49751
Thanks ae, Not quite sure what you mean. The rising edge detection depends on having some time dependancy (a clock) so doesn't work when the clock is stopped. But a work-around solution lies in storing the value while the clock is running and using this to detect a one off change when the clock is stopped. But I can't quite answer your question properly which was the problem I was wrestling with that led to the original post. It boils down to the fact that you can make combinational logic that will change whenever an input changes but then you can't make it return to its original state without some other event. This means you have to have a timing element and it becomes non-combinational (I think). Regards Phil <> wrote in message news:<ee7a761.0@WebX.sUN8CHnE>... > I am curious about this as well. Could you not just write a normal rising edge detector and invert the signal of interest prior to being placed on the input of the edge detector?Article: 49752
Hi Holger, You may be right but if this works I wonder what entirely combinational logic would be synthesised? Thanks for your thoughts. Regards PhilArticle: 49753
On 20 Nov 2002 10:39:27 GMT, hamish@cloud.net.au <hamish@cloud.net.au> wrote:
>Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote:
>> hamish@cloud.net.au writes:
>>> Why wouldn't you buy the tools if using such a high-end part?
>> 1. Because I'm a cheap bastard.
>> 2. Because it's a low-end Virtex II Pro, not a high-end.
>
>IS there such a thing?
The only actual price I've seen so far for a V2Pro
is $350 for a XC2VP4-6FF672CES. If anyone has more info,
please post. And no, I don't consider "$xxx for quantity
250,000 in 3Q03" an actual price. I mean in-stock on a
distributor's shelf.
- Larry
Article: 49754
1) try just the xilinx stand alone with VCC , if xilinx becomes hot you have
a problem about .
Emmanuel
"Alderan" <renzo.busonera@tin.it> wrote in message
news:t6NC9.31978$744.1182469@news1.tin.it...
> Hello, i'm beginning to pactice with xilinx device. I' ve build xilinx
> download cable and i'm trying to program a CPLD XC9536. When i use Impact,
> the application connects with the cable but don't program (don't get
> ID,too)the device and give me an error (Boundary scan fails at bit
position
> '1' ....).
> I've check my cable but the connections seem correct.
> In the PCB of my CPLD, i've connected all the Vcc (+5V) and Gnd and also
the
> 6 pin of Jtag header to XC9536, for the moment these are the only
connection
> i made.
> So i've 2 questions:
> 1)It's normal that XC9536 becomes hot when connected to vcc (also when the
> download cable is not connected)?
> 2)what could be the problem if the download cable is built correctly?
>
> Thank you all and sorry for my English.
> Giovanni
>
>
Article: 49755I have an application where I am using two CLKDLLs to generate a 4x clock - 400 Mhz from a base of 100 Mhz. The applicable Xilinx data sheet for Spartan IIe specifies a max Input clock frequency for -7 speedgrade devices of 160 Mhz for CLKDLL, and 320Mhz for CLKDLLHF. Does the max Input clock frequency refer to just the CLKIN frequency, or does it also include the CLKFB input? For the second DLL, the CLKIN is 200 Mhz, but the CLKFB is 400 Mhz. Thanks in advance. -- Regards, John Retta email : jretta@rtc-inc.com web : www.rtc-inc.comArticle: 49756
Hi there! I have a AHDL design and I'd like to convert it to a schematics(like RTL view). I use xport.exe(from xilinx) to convert AHDL to VHDL and then use ISE to view the RTL view of the VHDL file. It works not very well. some Altera specific primitives(LCELL) are not converted to VHDL. Is there any way that converts ADHL directly to a schematics? for example, within Quartus II? I know that we can convert schematics to VHDL in Quartus II. and I am new to FPGA. Could you please provide some useful web site for learning FPGA ? especially setting timing constraints.... Thanks a lot! JerryArticle: 49757
> Just drive the gray encoded read/write pointers(addresses) via FlipFlops, > sample them on the other side and reconvert them to binary to calculate the > difference between the read/write pointer. > > No RAM, simple FlipFlops are just right. > Hmm, is there a possibility to pass (registered) signals to other clock domains in Handel-C? I suggested the mpram version because I think mprams are the only structures available that can be used to pass data between two clock domains. > > We do, and its not such a big issue. Usually you use them as black boxes, > which are supplied by the FPGA/ASIC/whatever Vendor. Xilinx has some VHDL > sources for asynchronous FIFOs. Have a look at the xapps. > I have done that, but unfortunately they are all for HDLs and not Handel-C.... The thing is, I know how the fifos should look like in hardware. What I don't know is how to describe them in C. thx, BernhardArticle: 49758
HDL to schematics? Heathen!Article: 49759
Hi ! Russel, i already now http://www.opencore.org, and i like your job. I am subscribed to the list and i want to develop a board for being able to write code for www.opencore.org or similar. russelmann@hotmail.com (Rudolf Usselmann) wrote in message news:<d44097f5.0211192247.5e2ab054@posting.google.com>... > zumbita00@yahoo.es (Pepito Perez) wrote in message news:<441d2f16.0211191028.1daf4384@posting.google.com>... > > Hi all !! > > > > This is my first post in news, i read it sometimes, but i am a > > newbie. I have been looking to develop a board for Altera's APEX, and > > searching the group, i only find people doing their businesses. I'm > > going to take it as a project, and i think i would need some help from > > the group. Also say that if the project goes on it'll become a GPL > > (http://www.gpl.org) project, so every novice it this kind of stuff > > could get more experienced in FPGAs (like my case). > > > > > > Also, for that people that don't want to wait.... > > ...can find a FREE development Xilinx board at > > http://www.iearobotics.com/personal/juan/doctorado/jps-xpc84/jps-xpc84.html > > > > Thanks > > > OpenCores, even though focusing mainly on free IP Cores, also > has various FPGA proto board projects. Visit www.opencore.org > for more information. It might be a good place to share your > work with others. > > Cheers, > rudi > ------------------------------------------------ > www.asics.ws - Solutions for your ASIC needs - > NEW ! 5 New Free IP Cores this months (so far :*) > FREE IP Cores --> http://www.asics.ws/ <--- > ----- ALL SPAM forwarded to: UCE@FTC.GOV -----Article: 49760
Thanks, Stan and Ray. That explains why my multi-operands addition is always slower than "A+B" in FPGA JackArticle: 49762
I think I saw an XC2VP2 on avnet for around $120 a couple weeks ago (small
quantities), but I don't think there were any in stock.
Larry Doolittle wrote:
> On 20 Nov 2002 10:39:27 GMT, hamish@cloud.net.au <hamish@cloud.net.au> wrote:
> >Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote:
> >> hamish@cloud.net.au writes:
> >>> Why wouldn't you buy the tools if using such a high-end part?
> >> 1. Because I'm a cheap bastard.
> >> 2. Because it's a low-end Virtex II Pro, not a high-end.
> >
> >IS there such a thing?
>
> The only actual price I've seen so far for a V2Pro
> is $350 for a XC2VP4-6FF672CES. If anyone has more info,
> please post. And no, I don't consider "$xxx for quantity
> 250,000 in 3Q03" an actual price. I mean in-stock on a
> distributor's shelf.
>
> - Larry
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49763"Falk Brunner" <Falk.Brunner@gmx.de> ha scritto nel messaggio news:arg0q7$ifpj1$2@ID-84877.news.dfncis.de... > simulation (palin VHDL) Do Post-Mapping or > Post-Place&Route Simulation I did it (otherwise I wouldn't have found it strange)! > and > you will see that is takes some ns for the counter from > the clock edge to > advance to the next state. I have a zero delay with the post-place&route simulation. The others delays are realistic; do I have to suppose that (for some reason I don't know) the timings of that section of design weren't applied properly? -- LorenzoArticle: 49764
"Ewan D. Milne" <milne@egenera.com> ha scritto nel messaggio news:a9732c03.0211200444.601f7c5e@posting.google.com... > Does anyone know if Foundation 2.1i is supposed to > run on Windows 2000? Yes, it works (I used it frequently under Win2k). Note that there is a known problem with the Java Virtual Machine shipped with that version: it doesn't run with a Pentium 4 CPU. I remember I had to do some dirty tricks to install it. > Pcm Automation caused an exception, exit code 80010105 > Pcm The server threw an exception Search in the Xilinx answers database with the string "80010105", I solved a cople of problems in this way. Chances are that the problem is in FlexLM service; maybe you installed the program without admin's priviledges? -- LorenzoArticle: 49765
First of all thank's for you answer > Ahh, you build it on your own? Hmm, many things can go wrong. Check the > cable again. Check all connections. In Impact you have the possibility to do > some JTAG debuging, where you can switch the signals TMS/TCK/TDI by hand. Do > this and measure the signals on the board to see that the connection is > working, also measurw the direction fro TDO to IMPACT. I've measured the signal and when the downlaod cable isn' t connected to the system board, the signal in TMS and TDI is about 3.6 V (instead of tms_in and Din signals that are 4.9V) The TDO is 3.58V as so DONE signal. But when i connect the cable to system board the signals drops down to 0.8 V because the Tms and TDI input and of XC9536 assorb about 30 mA. It' possible that Jtag input of the device assorb all that current? Regards. GiovanniArticle: 49766
Petter Gustad wrote: > hamish@cloud.net.au writes: > > > Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote: > > > Has Xilinx said anything about future versions of WebPack being able > > > to support the 2VP4? We have no plans to include the 2VP4 in WebPACK. > It seems a shame that it doesn't support at > > > least one part that actually contains a PowerPC processor. The number > > > > Why wouldn't you buy the tools if using such a high-end part? > > The PowerPC model is a SWIFT model, which requires a SWIFT compatible > simulator. This is true. > As far as I know the object files for this model is only > available for SPARC/Solaris (correct me if I'm wrong). We have the SWIFT models for both Solaris and PC/Windows. > This means that > you will have to get a expensive simulator as well as a expensive > machine to be able to run your simulation. The cost of the full ISE > license from Xilinx will be peanuts... True, and you also need the Embedded Development Kit which is currently priced as a promotion for $495. Steve > > > Petter > -- > ________________________________________________________________________ > Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 49767
Phil Connor wrote:
> Hi Everyone,
>
> I'm using an fpga with the clock temporarily off and so have only
> combinational logic.
>
> Now, in this mode I need to generate a signal which is a falling edge
> only. This edge needs to be produced whenever there is any change
> (rising or falling) on any one of a set of input signals.
>
> I've got as far as using XOR on all the inputs to produce a toggling
> signal but I am now at a loss as to how to convert this to a falling
> edge only.
>
> toggling_output <= A xor B xor C ..........
>
> falling_edge_only <= ?????
>
> I suspect there is either a simple answer or it is impossible. Anybody
> know which?
>
> Solutions that will synthesise in VHDL would be appreciated. My
> synthesis tool rejects all my attempts although they simulate
> perfectly as a functional models.
>
>
> Thanks for any pointers
>
> Phil
Not sure if this method can be use in your application:
toggling_output <= A xor B xor C ..........;
process(clk, reset) -- Store the value when clock is active
begin
if reset='1' then
last_toggling_output <= '0';
elsif clk'event and clk='1' then
last_toggling_output <= toggling_output;
end if;
end process;
-- Produce falling edge
falling_edge_only <= (not (toggling_output xor last_toggling_output));
-- Or if you need to make sure that the fallign edge won't happen
-- when clock is on
-- falling_edge_only <= (not (toggling_output xor last_toggling_output))
-- when clock_is_off='1' else '1';
Hope it help.
Joe
Article: 49768"Alderan" <renzo.busonera@tin.it> schrieb im Newsbeitrag news:utSC9.33649$744.1247092@news1.tin.it... > I've measured the signal and when the downlaod cable isn' t connected to the > system board, the signal in TMS and TDI is about 3.6 V (instead of tms_in > and Din signals that are 4.9V) The TDO is 3.58V as so DONE signal. But when ?? Dont you have 9536, which is a 5V part? So TDO from the 9536 should be somewhere 4.5V++ > i connect the cable to system board the signals drops down to 0.8 V because > the Tms and TDI input and of XC9536 assorb about 30 mA. > > It' possible that Jtag input of the device assorb all that current? No way, there is something wrong. Are the power connections right (GND/VCC)? -- MfG FalkArticle: 49769
"Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it> schrieb im Newsbeitrag news:Y5SC9.2071$2B1.41281@twister2.libero.it... > I have a zero delay with the post-place&route simulation. The others > delays are realistic; do I have to suppose that (for some reason I don't > know) the timings of that section of design weren't applied properly? Maybe. -- MfG FalkArticle: 49770
As a workaround for this situation use the XIL_IMPACT_ENV_LPT1_BASE_ADDRESS
environment variable in iMPACT. If this variable is set, the specified value will be used as the
port address for the lpt port.
The port base address is listed as a resource in Windows Device Manager->Ports->LPTx devices. Right
click on an LPT
device, then select Properties->Resources->Input/Output Range.
From a command window set the aforementioned env variable prior to invoking iMPACT.
Specify the port base address value in hex.
ex. set XIL_IMPACT_ENV_LPT1_BASE_ADDRESS=378
This will set the LPT1 base address. LPT2, LPT3 and LPT4 are also supported
Dziadek wrote:
> Hi,
> The motherboard printer port in my PC is used by some hardware, so I have to
> connect the Parallel Cable to another printer port on an PCI I/O card. The
> port is EPP etc, but - as I suppose for most PCI printer ports - does not
> use the original printer port addresses (378,etc.) but some other in PCI
> space.
> The Impact programmer does not locate the cable. The cable works OK when
> connected to standard printer port.
> Does anybody use the Parallel Cable with PCI printer port? Does it work at
> all or maybe there are some hints to make it running?
>
> TIA
> Dziadek
Article: 49771> No way, there is something wrong. Are the power connections right (GND/VCC)? > Yes i've found the mistake. I had a description of the 44 pin socket wrong (it was a design from above and not from bottom) so i have inverted all the contacts in the Cpld device. I hope that device is not damaged. Thanks GiovanniArticle: 49772
I got a reply which could probably help me to better describe my issue: "While I agree that it's better to maintain a system synchronous to one central colock and having other (you mentioned "slow") events brought in with an edge detector rather than the edge itself (you still need the edge detection for a valid indication, don't you?) there are rare times when independent edges are helpful. If there are a dozen edges with data that has data valid times that are on the order of the system clock, the edge might be the best way to go. From this rare perspective, the synthesizer might be where the "problem" lies. Look in your allowable directives and attributes to see what effects you can have on synthesis of clocks. There are probably ways to override the inferrence of a global clock buffer in your synthesis. Mention your synthesizer (XST? Synplify?) and you may get a pointer to the proper attribute or directive from someone whose gone through the same thing. ...that is if you decide the edge detector isn't the way to go." I'm using Lonardo Spectrum, and I'd be grateful for any help or any prompt to where I could find some info. Thanks in advance. Mirko Scarana PhD Student "La Sapienza" University, RomeArticle: 49773
process(clk)
if rising_edge(clk) then
sync_register<=3D slow_input;
sync_z<=3D sync_register;
rising_edge_happened<=3D sync_register and not sync_z;
Presumably you have a clock in your system that is faster than you slow i=
nputs. The above synchronizes the input to the local clock, then generat=
es a 1 clock wide pulse each time a rising edge is detected on the slow i=
nput (presumes that the slow input changes state and then stays that way =
for longer than the period of the clock.
Mirko Scarana wrote:
> I got a reply which could probably help me to better describe my issue:=
>
> "While I agree that it's better to maintain a system synchronous to one=
central colock and having other (you mentioned "slow") events brought in=
with an edge detector rather than the edge itself (you still need the ed=
ge detection for a valid indication, don't you?) there are rare times whe=
n independent edges are helpful. If there are a dozen edges with data th=
at has data valid times that are on the order of the system clock, the ed=
ge might be the best way to go. From this rare perspective, the synthesi=
zer might be where the "problem" lies. Look in your allowable directives=
and attributes to see what effects you can have on synthesis of clocks. =
There are probably ways to override the inferrence of a global clock buf=
fer in your synthesis. Mention your synthesizer (XST? Synplify?) and you=
may get a pointer to the proper attribute or directive from someone whos=
e gone through the same thing. ...that is if you decide the edge detecto=
r isn't the way to go."
>
> I'm using Lonardo Spectrum, and I'd be grateful for any help or any pro=
mpt to where I could find some info.
> Thanks in advance.
>
> Mirko Scarana
> PhD Student
> "La Sapienza" University, Rome
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49774Hi Ray, The point was "thwarting" was highly probable with mapping and placement when using HDLs, I don't believe I said file formats had anything to do with the aforementioned "thwarting"? Austin "Ray Andraka" <ray@andraka.com> wrote in message news:3DDABEA8.A7B00D8B@andraka.com... > But not nearly to the same degree. For the most part, a design will be > functional under any tool you compile it with. It is usually the attributes, > and in the case of some of the cheaper tools, unsupported language constructs > that thwart portability, not file formats. > > Austin Franklin wrote: > > > > > I also believe this ability is somewhat tool specific? Are the mapping > > and > > > > placement abilities of HDLs cross tool abilities? > > > > > > > > > Is there a schematic file format that crosses tool boundaries? > > > > I believe there are some schematic translators, and possibly EDIF, but not > > really seamlessly, as it is an acknowledged deficiency of schematic tools. > > > > That was the point I was making about HDLs, that, depending on how much > > "tool specific" things your design contains/relies on, that then becomes the > > same issue to some degree. > > > > Austin > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > > >
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