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Jyoti, The mult18x18 was introduced in the Virtex-II, but the part that you mentioned here is a Virtex-E. Virtex-E was the family before Virtex-II so there is no dedicated hardware multiplier (mult18x18) in this device. Your next best bet is probably using Coregen for Virtex-E to generate a multiplier that's made of LUTs and RAM. Best regards, Ryan Laity Xilinx Applications Jyoti Wagholikar wrote: > Hi, > > I am trying to instantiate embedded MULT18X18 signed multiplier in > Xilinx foundation 3.1i series. While implementing the design on > XCV100E-8-PQ240, I am getting the following error: > > ERROR:NgdBuild:432 - logical block 'M1' with type 'MULT18X18' is > unexpanded > > I noticed that libraries getting attached to the project are : Virtex > and Simprim, I tried to change the library to virtex II ( It contains > MULT18X18). But while implementing, the library, automatically, got > changed to virtex. > > Can you please give me the direction regarding this? It will help me > to go ahead in my project. > > I tried to generate multiplier core from Logicore, I found that the > timing analysis (delay) for pipelined and non pipelined multiplier is > same. I am wondering if core uses internal pipelined register while > generating pipelined multiplier. > > thanks in advance, > > -JyotiArticle: 49701
On 19 Nov 2002 03:56:01 -0800, phil_j_connor@hotmail.com (Phil Connor) wrote: >Hi Everyone, > >I'm using an fpga with the clock temporarily off and so have only >combinational logic. > >Now, in this mode I need to generate a signal which is a falling edge >only. This edge needs to be produced whenever there is any change >(rising or falling) on any one of a set of input signals. > Do you mean that you need this only once ? IOW, when clock is off, initially your output is high and the first change on these inputs makes it go to zero and stay there ? If yes, you can use a Set Reset (SR) latch. You can set it in the clocked process and use the toggling_output as your reset signal. This would be useful in a wake-up from suspend situation. With an active low enable oscillator, you can turn-off your own clock by setting the clock enable in the clocked process and any activity on the input can turn it back on. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 49702
> > Peter, I gess this is an incomming call for you. ;-) > > ASYNCHRONOUS FIFOS!!!!! > > Yes, there is a way. Use gray encoded read/write pointers to transfer them > over the clock boundary. Then make sure to stop writing, when the FIFO has > 2..3 or less words free, NOT if there is just one word, free. Same with > reading. > I see, the point is to include some amount of tolerance to handle delays between the two clock domains, right? But how exactly do I pass the pointers over the boundary? Will a simple mpram (using LUTs and not block RAM, I guess) do? I'm new to hardware design (as you may have noticed...) but don't you guys use asynch fifos rather frequently? I'm just surprised that it's such a big issue... :-) Thanks for your help, BernhardArticle: 49703
> > Synchronize signals for the slow domain as inputs with two D flops on > the system clock (120MHz). Hmm, bad idea if the input clock is faster than the system clock, right? > > Another question regarding SRAMs in Celoxica (using the built-in SRAM access > > functions): I neither see a way of using ZBT or pipelined SRAMs without > > dividing the Handel-C clock down nor to make use of address and data > > pipelining of those RAMs. > > > There is only one clock for synthesis. If 120 won't do it, > double it on-chip to 240 MHz. You will have to > do your own access procedures. I was wrong. I still have to write my own controller, but it'll work perfectly with the system clock. I wasn't sure about when output values are written to the busses in Handel-C and whether the signal would, after a rising clock edge, endure for at least the RAM's hold time. > > Handel-C is used for system-level simulations with > cpu and logic modules or for converting working C code > processes directly into hardware. > Since you are designing a new low-level hardware > function for synthesis, and there is no such existing code, > Handel-C may be a tough fit. You're right, and still we want to see how far you can get whith a pure Handel-C design, so I don't have much of a choice... Thanks for help Regards, BernhardArticle: 49704
Hi Phil, The following is a Verilog code that generates a short pulse on each transition of the input signal. It works fine in post place and route simulation (and in hardware). For behavioral simulation you can insert some delay (e.g., r <= #2 !r). module pulser(in, out, rst); input in; output out; input rst; reg r; assign out = !(in ^ r); always @(negedge out or posedge rst) if (rst) r <= 1'b0; else r <= !r; endmodule Regards, -- Georgi phil_j_connor@hotmail.com (Phil Connor) wrote in message news:<7c8e85ff.0211190356.531993c4@posting.google.com>... > Hi Everyone, > > I'm using an fpga with the clock temporarily off and so have only > combinational logic. > > Now, in this mode I need to generate a signal which is a falling edge > only. This edge needs to be produced whenever there is any change > (rising or falling) on any one of a set of input signals. > > I've got as far as using XOR on all the inputs to produce a toggling > signal but I am now at a loss as to how to convert this to a falling > edge only. > > toggling_output <= A xor B xor C .......... > > falling_edge_only <= ????? > > I suspect there is either a simple answer or it is impossible. Anybody > know which? > > Solutions that will synthesise in VHDL would be appreciated. My > synthesis tool rejects all my attempts although they simulate > perfectly as a functional models. > > > Thanks for any pointers > > PhilArticle: 49705
Hi all !!
This is my first post in news, i read it sometimes, but i am a
newbie. I have been looking to develop a board for Altera's APEX, and
searching the group, i only find people doing their businesses. I'm
going to take it as a project, and i think i would need some help from
the group. Also say that if the project goes on it'll become a GPL
(http://www.gpl.org) project, so every novice it this kind of stuff
could get more experienced in FPGAs (like my case).
Also, for that people that don't want to wait....
...can find a FREE development Xilinx board at
http://www.iearobotics.com/personal/juan/doctorado/jps-xpc84/jps-xpc84.html
Thanks
Article: 49706I would like some input to a subjective question: What would you label a "big" FPGA design for one engineer? This would include logic design (documentation), coding, test, synthesis and hardware debug. I have just finished a design, coding, test and synthesis that fills over 95% of XC2S150. It has fifty VHDL source files and has taken eight months and looks now to fundamentally be working but not a product yet - is this outrageous amount of time? Could some of you share with me your methods of estimating effort for FPGA designs to production? The company does not subscribe to any methodology. I really would appreciate this. Thanks A lonely FPGA designer.Article: 49707
Hello. Trying to design multiplier using carry save adder and 4:2 compressor on a Xilinx Virtexe. The optimized synthesis use LUT for all the functions instead of carry chain. Is anyone know how to force the Synthesis tool to implement the logic function using the carry chain? Thanks JackArticle: 49708
"Bernhard Mäder" <nonuschk@gmx.net> schrieb im Newsbeitrag news:3dda7db2@news.swissonline.ch... > > > > Peter, I gess this is an incomming call for you. ;-) > > > > ASYNCHRONOUS FIFOS!!!!! > > > > Yes, there is a way. Use gray encoded read/write pointers to transfer them > > over the clock boundary. Then make sure to stop writing, when the FIFO has > > 2..3 or less words free, NOT if there is just one word, free. Same with > > reading. > > > > I see, the point is to include some amount of tolerance to handle delays > between the two clock domains, right? But how exactly do I pass the pointers Just drive the gray encoded read/write pointers(addresses) via FlipFlops, sample them on the other side and reconvert them to binary to calculate the difference between the read/write pointer. > over the boundary? Will a simple mpram (using LUTs and not block RAM, I > guess) do? No RAM, simple FlipFlops are just right. > I'm new to hardware design (as you may have noticed...) but don't you guys > use asynch fifos rather frequently? I'm just surprised that it's such a big > issue... :-) We do, and its not such a big issue. Usually you use them as black boxes, which are supplied by the FPGA/ASIC/whatever Vendor. Xilinx has some VHDL sources for asynchronous FIFOs. Have a look at the xapps. -- MfG FalkArticle: 49709
Agreed. I originally had an "I concur with Rickman" at the beginning of my post,
but then when I went back and reread yours, I wasn't sure if that was what you
were saying so I deleted the first sentence.
rickman wrote:
> Ray Andraka wrote:
> >
> > Where slack does come into play with metastability is that your
> > metastability resolution time available is equal to the slack time. If your
> > path leading from your syncronizer has little slack, your chances of a
> > metastable event lasting long enough to matter is greatly increased. You
> > want to maximize the slack after a synchronizer, preferably with
> > geographically close registers with no intervening logic.
> >
> > rickman wrote:
> > stuff about slack time not being related to metastability
>
> That is the well understood part of metastability. I was commenting on
> Michael's post which seemed to confuse the very small calculated input
> time window which will result in a FF going metastable and slack time
> which will provide settling time for the metastability to be resolved to
> a defined state. These are two independant concepts and even though
> they are both aspects of metastability, they have nothing to do with one
> another.
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49710
Good luck.
Learning both HDL and FPGA at the same time is not IMHO the way to do
it. I think your best chance for success in this would be to use system
generator and accept the VHDL it produces. It will be considerably more
optimal than anything you will likely create on your first run through
both FPGAs and HDLs. I hope you have plenty of time built into your
schedule. Yes, there are several people here who have done this type of
thing, however none that I am aware of attempted it as their first foray
into both HDLs and FPGAs.
Tom wrote:
> I am trying to implement the baseband layer of Bluetooth on an FPGA,
> using Xilinx (project navigator) software.
> I have produced a simple maximal shift sequence and now want to
> Gaussian filter this.
> Has anybody used this software to complete this task before? If so
> could you offer me any hints or tips on how to start as I'm
> clueless, I had never used an FPGA or HDL until last week!
> Thanks very much
>
> Tom
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49711
The structure you describe is essentially a wallace tree (depending on the
connection topology you choose). It is useful for a learning exercise, but
is twice the area and slower than a partial products based multiplier that
uses carry chains in Xilinx. The carry side of each half adder is included
in the LUT if you use a carry chain, where it needs an additional LUT if you
do not. See the multipliers page on my website for the details.
Most of the current synth tools will infer a carry chain. Synplify has a
minimum bit width of about 6 bits before it gts inferred because the speed
penalty getting on/off the chain is greater than doing it with a LUT for
small adders. You can force the issue by instantiating the carry chain
primitives.
Jack wrote:
> Hello.
> Trying to design multiplier using carry save adder and 4:2 compressor on
> a Xilinx Virtexe. The optimized synthesis use LUT for all the functions
> instead of carry chain. Is anyone know how to force the Synthesis tool
> to implement the logic function using the carry chain?
>
> Thanks
>
> Jack
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49712This is a link to the public library in Groton Massachusetts - I liked their childrens room and art galley, do you by any chance belong to the "Friends of the Groton Public Library" association? "Pepito Perez" <zumbita00@yahoo.es> wrote in message news:441d2f16.0211191028.1daf4384@posting.google.com... > Hi all !! > > This is my first post in news, i read it sometimes, but i am a > newbie. I have been looking to develop a board for Altera's APEX, and > searching the group, i only find people doing their businesses. I'm > going to take it as a project, and i think i would need some help from > the group. Also say that if the project goes on it'll become a GPL > (http://www.gpl.org) project, so every novice it this kind of stuff > could get more experienced in FPGAs (like my case). > > > Also, for that people that don't want to wait.... > ...can find a FREE development Xilinx board at > http://www.iearobotics.com/personal/juan/doctorado/jps-xpc84/jps-xpc84.html > > ThanksArticle: 49713
> Also, for that people that don't want to wait.... > ...can find a FREE development Xilinx board at > http://www.iearobotics.com/personal/juan/doctorado/jps-xpc84/jps-xpc84.html > > Thanks You can find another free, open-source development board for bigger Xilinx FPGA at http://fpga.f2g.net/ :o)Article: 49714
"Stan" <vze3qgji@verizon.net> ha scritto nel messaggio news:H0kC9.7115$Q27.597@nwrddc01.gnilink.net... > Also, both the write-enable and the enable need to be > asserted, with setup > and hold wrt the rising edge. -Stan Yes, it was my fault, I swapped two signals names. :) Now all simulates nicely, but some recent discussions read on this newsgroup gave me some thoughts. I write the block RAM in a "sequential" way; the address is generated by a counter, clocked by the same signal that drives the RAM write clock. In the ModelSim simulation, I see that the address change is almost simultaneous to the write clock (I know very few of FPGAs yet, but I think this is a 'magic' done by DLLs, right?). However this doesn't generate a timing error/warning. Is this situation correct or I'll go into big troubles sooner or later? Note - if I use both clock edges, one for memory write and one for address increment, I go far below my needed performances (by the way: why?). -- LorenzoArticle: 49715
Austin Franklin wrote:
> Ray,
>
> It appears you are using your HDL for, more or less, a netlister. I have no
> problem with parameterized modules, that's the way this stuff SHOULD be
> done, whether HDL or schematic. It's above that level that I really care
> about...and personally, I believe schematics (or some graphical interface)
> is far more functional for most humans to understand/work with.
Yes, the point is I have the option to use it as a netlister for stuff I want
to tightly control (typically data path) or to use a higher level of abstraction
(RTL) for the stuff that I am not as fussy about such as my control signals. An
RTL level description can be made to preserve duplicated registers and whatnot
with extra attributes. Typically, these attributes might differ a bit between
tools, but then where they do there is no overlap and you can include attributes
for all tools. The ones not used by a tool are generally ignored.
While an HDL can do the netlisted stuff (and like I said, I do a good amount of
that to force the construction of my data paths), it's real value is to those
who for whatever reason don't want to design at the device level. You can get
away with a fairly gross description and get a working circuit, albiet not
usually as dense or as fast as a netlisted design, but certainly functional
without having to get into the details of the part. (Gawd, I never thought I'd
be saying those words).
The netlisting is not tool specific as long as you use primitives out of the
device library (e.g. unisims) and then put them together. Even the placement
does not have to be tool specific provided the tool supports user attributes by
passing user attributes through to the edif netlist (Synplicity, Leo, Mentor
Precision, XST all do that, FPGA express doesn't do it too well last I looked).
Where you get some tool specificity is when you infer logic, particularly LUTs
and then encapsulate them to create a LUT. In many cases, you can get away with
inferring the LUT logic and letting the placer worry about putting it with the
flip-flop. In cases where you can't you can either use the tool specific
constructs (Synplify's is xc_map) to make a LUT out of inferred logic, or you
can write a function that converts a boolean string to an INIT attribute for a
LUT primitive (or you could compute and enter the LUT init string manually, but
I don't recommend it...not to readable and very prone to mistakes). In any
case, the modifications to get a structural design to work under different tools
is very minimal. It is more work to get an RTL level design where you did some
of the pushing on a rope routine to make it do what you wanted to port to
another tool. For portability, it is that middle ground that provides the most
resistance, not the RTL just want it functional designs and not the structurally
instantiated ones.
>
> To be able to match schematics ability to do critical logic mapping and
> placement is relatively new to HDL, and yes, that does make it able to match
> schematics in performance and density ability (for the netlisted logic that
> is), as you really are not using the synthesizer to do any synthesizing...I
> guess that's a good thing.
>
> I also believe this ability is somewhat tool specific? Are the mapping and
> placement abilities of HDLs cross tool abilities? Will the highly mapped
> and placed HDL code used for Synplify work with FPGA Express? That, of
> course, is a major issue in touting portability if it is not, as you ARE
> relying on a single vendor for the tool, just like you are with schematic,
> though not as entirely...as the code can be massaged to "work", but not
> necessarily as well as it would with the tool it was intended for.
>
> Regards,
>
> Austin
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3DD2F558.13CA7450@andraka.com...
> >
> >
> >
> > Austin Franklin wrote:
> >
> > > I don't understand. What tools are you talking about? I simply run my
> > > testbench, written in HDL, same as I would for any design even if the
> design
> > > is in HDL, and get the same output waveforms...or better yet, it
> displays
> > > the actual signals on the schematics.
> >
> > My viewlogic license is only enabled for viewsim and viewdraw. It doesn't
> > support the viewlogic VHDL, that was extra. Frankly, the Viewlogic VHDL is
> quite
> > poor compared to Modelsim or Aldec.
> >
> > > What about placement? Problems I've had were the tools didn't allow the
> use
> > > of consistent names, either when a change was made with to either the
> > > design, or the toolset.
> >
> > I haven't had much problems with placement, at least not with stuff
> instantiated
> > in the code (that is one of the major reasons I do as much structural
> > instantiation as I do). Only inferred logic changes its names,
> instantiated
> > logic generally does not. Inferred flip-flops generally take on the name
> of the
> > output net, so there is no problem floorplanning using inferred
> flip-flops. The
> > LUTs do tend to get random names, so they are not as easy to deal with in
> > floorplanning, but then if you do your design with one level of logic, the
> > mapper packs them with the flip-flops anyway.
> >
> > > And what preculdes you from doing that with schematics? Did you ever
> see
> > > Philip's tool for generating schematic elements?
> >
> > Yes, I did, and it is a very nice tool too. I never did get my own copy
> because
> > just as he came out with it I was in the middle of a transition to HDLs.
> HDLs
> > give you that capability without having to obtain an add on tool.
> >
> > >
> > >
> > > > The advantage is if I make a change to the macro, it only gets
> changed
> > > > in one place, which is not necessarily true with schematics (using 2
> bit
> > > slices
> > > > for arithmetic, it is almost true, but you still have the special
> cases at
> > > the
> > > > start and end of a carry chain). The parameterization includes
> options
> > > for
> > > > layout, assignment to different device families (RLOC format for
> example),
> > > > automatic signed/unsigned extension, automatic selection of reset
> vector
> > > values
> > > > with the proper FDRE/FDSE etc. These are things that were a little
> > > awkward with
> > > > schematics, and are very easy to do with the HDL generates.
> > >
> > > Hum, I don't find them awkward at all with schematics, but do with
> HDLs...
> >
> > For example, say you have (this is from a design that I did with
> schematics) a
> > bank of 128 129 bit LFSRs. Each is identical except it has a different
> reset
> > value. With an HDL, you can construct one parameterized module that
> generates
> > the proper combination of sets and resets without ever having to look
> inside the
> > module, then you can instantiate those 128 modules in a generate statement
> that
> > indexes a constant array (probably in a package in another file so that
> you
> > never have to modify the source even if you change the constants) to
> > parameterize the initial values of each module. If I want to change the
> intial
> > values, I just edit the list of initial values, which by the way can be
> > expressed as binary, decimal, hex, octal or any mix of that you like.
> With
> > schematics, you need to generate each module using FDREs and FDSEs. As I
> > recall, Philips tool didn't do this readily, and it certainly didn't read
> the
> > init values out of a common file. Similarly, I can set up filter
> coefficients
> > for distributed arithmetic filters as a naturally ordered list of
> coefficients
> > in a separate package. My VHDL filter is parameterized to read the
> coefficients
> > from a file, process them (with a procedure) to create the init values for
> the
> > DA LUTs, and then build the filter including placement. The code is
> > parameterized for the coefficient width, filter add tree width, bits per
> clock,
> > length of the filter etc, and I never have to go inside that module to
> modify
> > anything. It took a while to build the library to where I was as
> productive
> > with VHDL as I was with schematics, but I am now well past there.
> >
> > > Mainstream? Not really. Synplify may be the "tool de Jour", but I
> don't
> > > see that as being any better than schematics, though you are locked to a
> > > single vendor with schematics, no doubt. Also, as you know, every damn
> > > revision of these HDL compilers generates different code...which reeks
> havoc
> > > on some designs.
> >
> > Depends on the definition of mainstream, I suppose. Where I come from,
> > mainstream means that which most people are doing, not what which is
> 'best'.
> > When all of my customers are asking for an HDL design flow, I think that
> can be
> > described as the mainstream. Schematic entry for FPGA design, like it or
> not,
> > can't really be considered mainstream anymore, at least by the definition
> of
> > mainstream I am familiar with. You can get around the variations between
> > compilers by using structural generation for the critical parts of your
> design.
> > We do it in a large percentage of each of our designs. As an indicator, I
> spend
> > far more time tweaking things for PAR than I do for getting the synthesis
> to
> > turn out what I want.
> >
> > >
> > > I agree. Designs I do for my own projects, I do in schematics...simply
> > > because it keeps the parts cost down, ups the speed significantly...and
> I
> > > don't have to wrestle with the tools. I do mostly HDL work for clients
> now,
> > > as for misbegotten reasons, they believe it saves them time and
> money...when
> > > in every instance, it absolutely, unquestionably does not.
> >
> > I'm not sure an HDL will save money or not. Because my library is far
> more
> > parameterized than I was able to achieve with schematics, and because I
> have the
> > option of structural cosntruction where it matters or RTL level coding
> where
> > things are not as critical, my design capture is perhaps a little bit
> shorter
> > than it was with schematics. I have seen tremendous gains in the
> simulation
> > however because the sophistication of the testbenches is much higher.
> >
> > >
> > >
> > > > So will I be seeing you in San Jose tomorrow? If so, we can discuss
> this
> > > in
> > > > person.
> > >
> > > No, sigh...I am unable to make it, but I was assured by Philip that you
> > > would defend the fort better than either of us would ;-)
> >
> > Depends which fort. I don't defend the schematic fort anymore. I got out
> of
> > there right before it burned down around me. As for using a mix of
> schematics
> > and HDLs, I find that more awkward than using either...it means
> maintaining two
> > libraries, proficiency on additional tools and customers griping louder
> because
> > of more tools needed to support a design. You missed a good meeting, They
> were
> > very receptive and have been following up this week (which is something we
> > didn't see before).
> >
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49716
But not nearly to the same degree. For the most part, a design will be
functional under any tool you compile it with. It is usually the attributes,
and in the case of some of the cheaper tools, unsupported language constructs
that thwart portability, not file formats.
Austin Franklin wrote:
> > > I also believe this ability is somewhat tool specific? Are the mapping
> and
> > > placement abilities of HDLs cross tool abilities?
> >
> >
> > Is there a schematic file format that crosses tool boundaries?
>
> I believe there are some schematic translators, and possibly EDIF, but not
> really seamlessly, as it is an acknowledged deficiency of schematic tools.
>
> That was the point I was making about HDLs, that, depending on how much
> "tool specific" things your design contains/relies on, that then becomes the
> same issue to some degree.
>
> Austin
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49717Hi All, I want to design 1GHz LVDS for my project "the design of 1GHz SERDES". Any inputs on the design of LVDS in CMOS are welcome. Thanks, PallaviArticle: 49718
We need a adaptor for Actel Sculptor II programmer. The type is: SMPA-208PQ-ACTEL-1. Does anyone here is from Ottawa and happen to have this adaptor? We may need to use for 2 weeks to meet our deadline. Any help is appreciated, FrankArticle: 49719
Hi, I am after storing around 1000 samples from a 12-bit ADC on the spartan-II dual port blockram. Inorder to configure the dual port ram as a single port block ram (256 x 16), i declare the component in vhdl as :- --- component RAMB4_S16 generic(INIT_00,INIT_01,INIT_02,INIT_03 : bit_vector (255 downto 0):= X"0000000000000000000000000000000000000000000000000000000000000000"); port (WE,EN,CLK,RST : in std_logic; ADDR: in std_logic_vector (7 downto 0); DI: in std_logic_vector (15 downto 0); DO: out std_logic_vector (15 downto 0)); end component; --- INIT_00 -> INIT_03 will initialize the first 1024 memory locations..Can anyone tell me whether the above syntax is correct / not ? Also, should I declare the INIT_XX as an attribute before using it in my design ? Any help would be appreciated..Article: 49720
Hi. Good luck on your project. It is definitely a worthwhile investment if you want to get a jump start on FPGAs. You may want to consider a few things before you start, though. I am not sure about Altera's free tools, but this should be a consideration if you are doing this out of your own pocket. I am a Xilinx user and know that the Webpack, although it has a few sore spots, is quite popular with the hobbyist electronics community. The design flow will be quite important and you will want to keep it low cost. You might also want to have an FPGA project in mind as you design the board, because building the board is only half the fun. The rest of the "fun" is writing the code, simulating it, debugging it, cursing at it, and then finally seeing it work. Good luck. strut911Article: 49721
Well, i have made my first mistake ............
When i said gpl.org, i meant :
http://www.gnu.org/copyleft/gpl.html
Thanks Mike !
"Mike D" <mdelphia@snet.net> wrote in message news:<dpwC9.6766$1z2.1259493467@newssvr10.news.prodigy.com>...
> This is a link to the public library in Groton Massachusetts - I liked their
> childrens room and art galley, do you by any chance belong to the "Friends
> of the Groton Public Library" association?
>
>
> "Pepito Perez" <zumbita00@yahoo.es> wrote in message
> news:441d2f16.0211191028.1daf4384@posting.google.com...
> > Hi all !!
> >
> > This is my first post in news, i read it sometimes, but i am a
> > newbie. I have been looking to develop a board for Altera's APEX, and
> > searching the group, i only find people doing their businesses. I'm
> > going to take it as a project, and i think i would need some help from
> > the group. Also say that if the project goes on it'll become a GPL
> > (http://www.gpl.org) project, so every novice it this kind of stuff
> > could get more experienced in FPGAs (like my case).
> >
> >
> > Also, for that people that don't want to wait....
> > ...can find a FREE development Xilinx board at
> >
> http://www.iearobotics.com/personal/juan/doctorado/jps-xpc84/jps-xpc84.html
> >
> > Thanks
Article: 49722hi ! i would like to know were is the switch block type and architecture use in virtex II some one can help me ? thanxxArticle: 49723
I wrote: > Has Xilinx said anything about future versions of WebPack being able > to support the 2VP4? It seems a shame that it doesn't support at > least one part that actually contains a PowerPC processor. The number hamish@cloud.net.au writes: > Why wouldn't you buy the tools if using such a high-end part? 1. Because I'm a cheap bastard. 2. Because it's a low-end Virtex II Pro, not a high-end.Article: 49724
Stefan Kulke <kulke@informatik.tu-cottbus.de> wrote in message news:<ardc7h$5dd$1@Maust.bbone.tu-cottbus.de>... > Thanks for the answers! > > I know now, that the input Pin GCK0 isnt a clock input in my schematic. > GCK0 => IBUFG => CLKIN from CLKDLL > > The follow assignment is in my constraint file: > NET "gck0" LOC = "p80"; > > If i take this, i will not get a clocksignal. > If i take LOC = "DLL0", then the constraint file editor will overwrite > it with old value. > If i take LOC = "p187", then the follow error message will appear: > "ERROR:MapLib:103 - symbol "gck0" (pad signal=gck0) driving > IBUFG->CLKDLL is > LOCed to a generic IOB site. It must be LOCed to a GCLKIOB site." > > If i have not got: > * a input gck0 > and > * old systemclock (pin 185, > with 'TIMESPEC "TS_clk_a1" = PERIOD "clk_a1" 48 MHz HIGH 50 %;') > and > * INST XLXI_15 LOC="DLL3" is in my constraint file > (without using the editor, i dont know where is this option) > (XLXI_15 is the instname of ibufg). > then the projectmanager say the ucf-file is corrupt. > > Unfortunately the documents ds001_2.pdf and xapp174.pdf dont help me by > this problem. > The documents can be found in support from xilinx. > I have try many others possibilities, but none were successfully. > I dont know, what i m doing wrongly. > > I will be glad, if i can get more informations or answers. > > > with kind regards > > Stefan I am not sure if this will help, but try putting the following in your UCF file for the input clock "GCK0" - NET "GCK0" LOC=p80; NET "GCK0" TNM_NET="GCK0"; TIMESPEC "TS_GCK0" = PERIOD "GCK0" 48 MHz HIGH 50 %; INST DLL_INST LOC="DLL0"; Vikram.
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