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Hi everybody, I am looking for a programmable oscillator for a board consisting mainly of a Xilinx Virtex 2000E . (XCV2000E) For this purpose I looked at DS1075 econ-oscillator ,but this oscillator is 5 V. On the other hand the Virtex-E I/O's ( I assume that I/O's include clock inputs)are 3.3 . Is there a solution for this problem ? I need to be able to program the clock in-circuit ? please do reply, thanks very much , Anand KulkarniArticle: 49776
"Ray Andraka" <ray@andraka.com> wrote in message news:3DDB109D.D0CD8056@andraka.com... > The reason for doing a carry save adder is to defer the add carry to the last > adder in the tree. Normally this is done in order to permit construction of > just one fast adder. The speed of an adder tree is limited by the speed of > the propagation through any path in the tree, and the worst case paths are > from the lsb of an input to the msb of the output. In other technologies, a > ripple carry adder is slower than fancier carry look-ahead schemes, but the > fancy schemes take up considerably more logic. By deferring the carry to the > last stage, one only has to build one of these expensive adders. The rest of > the adders have the same cost as the ripple carry adder but without the ripple > propagation. So by doing this, you speed up the adder tree as if all the > adders were the more expensive fast adders. > > Now enter the FPGA, with its dedicated adder carry chains (these actually do > have some carry look-ahead built in, but it is hidden from the user). No they don't, not Virtex anyway! It's strictly ripple carry. The ripple carry is very fast because there are special goodies in both synthesis and P&R to optimize them, but it's good old simple ripple carry propagation, bit-by-bit. In fact, if the ripple carry is not fast enough, Xilinx P&R refuses to do any P&R at all! No, if you want a parallel carry look-ahead, you code all the Gs and Ps youself. Which I have done! > In the > case of the FPGA it is very hard, impossible in many cases, to build an adder > that is faster than the built in adder function because the dedicated > resources are so much faster than the general purpose routing. zzzt! Does not compute! > Since that > ripple adder is the fastest one can build in the fpga, there is no penalty (in > fact there is an advantage) to using them through out the adder tree rather > than only at the final add. The advantage is that by doing this, all the > carry logic is put on the dedicated resources, so you essentially get the > carry half of all the 3:2 adders for free. If you decided to build an adder > without using the chains (including the Carry Save type), you need two LUTs > per full adder instead of the one because you can't take advantage of the > dedicated carry logic, so not only do you get no speed advantage in an FPGA by > using a CSA tree, but you also get soaked for twice the resources, and in fact > you get a speed degradation due to the irregular routing. > > The bottom line is that carry save adder trees DO NOT MAKE SENSE for FPGAs > that have dedicated adder resources. Does not compute! Run Will Robinson run! -the robotArticle: 49777
Phil Connor wrote: > > Many thanks to Ben, Muzaffer and Joe, > > What a great bunch you are, generously offering your solutions ! > > With your help I've solved the problem now using the ideas of Muzaffer > and Joe. I'm sure yours would work too Ben although I'm a bit > frightened of the tool directives. However, it would have been the > only solution if I hadn't been able to use the clock-back-on period to > reset the falling edge signal. > > Hope I can do the same for you all some day. > > Regards > > Phil So please share with us the solution you came up with. I am still not sure I understand what your goal is. But I am also interested in what you end up with in the logic. Working in an HDL without knowing ahead what logic you are trying for is alien to me. I always think of my logic first and then think of how to write the code to produce it. Maybe I am old fashioned. I think I understand Georgi's approach as a FF producing 'r', a second version of the input but delayed through the FF clocked by the output. The output is the xnor of r and the input so it will produce a negative edge when the input changes. This clocks the FF and r is inverted changing the state of out back to a '1'. In essence r follows the input with a slight delay. Joe's approach is to use a clocked FF to do the same thing. He xnors the input and the FF delayed version of the input giving a negative pulse until the next clock edge. But if the input is not synchronized to the clock, this circuit can generate glitches that may or may not be useful in your circuit. A simpler circuit is just the xnor of the input and the inverted input. The inverter will provide a delay which will create a negative pulse on each transition of the input. The delay will be the difference in the routing and the logic in the two inputs to the xnor. You will need to control these delays via placement constraints. You may need to assure that the input is generated in a LUT and xor'd in another LUT in the same CLB. You will also have to use a constraint to keep the tools from optimizing the inverted input into the LUT. It will be best if you can control the placement of this LUT in a different CLB. Georgi's approach does not have such issues with control of timing in place and route, if I understand it correctly. The width of the output pulse in his design is controlled by the path from the output through the FF and through the xnor element that produces the output. At minimum this will be the delay through two logic elements. So this one will be much easier to use without careful tuning. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 49778
Anyone know of any recommended limitations on the design size or come to think of it, the capabilities of XST? Put another way is there a point in time when one should consider moving to a high price synthesis engine? Cheers, DeclanArticle: 49779
Hello there, In my recent design, I notice that a timing parameter named "Tiotp" which is reported by ISE 5 tools. It seems a IOB timing parameter, but I cannot find any description on it in the handbook of VirtexII. If I remember rightly, for the recent version of ISE, it is "Tioop" of IOB which means propagation delay from the O input of the IOB to PAD. The FPGA gurus and Xilinx people, would you explain it to me? -- BadahanaArticle: 49780
Hi NG, I'm a beginner in FPGA programming and would like to get some hints on some questions on FPGA programming. My local part distributor offers xcs-05-3-pc84 (plcc84 case) and xcs-10-3-pc84 Xilinx-FPGA's. (20$ and 40$ each) I would like to know what kind of project complexity I'm able to realize (when having the knowledge) with 100 CLBs / 360 FF / 5000 gates in the xcs-05 fpga and 196 CLBs / 616 FF / 10k gates in the xcs10 fpga. Am I able to realize a USB V1.1 Master Core or a PCI 2.1 compliant core or a TFT-DVI interface. Need I the Spartan-XL features to realize the above mentioned goals? (especially the io-latches feature and the 3.3V Supply instead of 5V) Any hints are welcome Many thanks in advance Markus ============================================ Markus Wolfgart DLR ============================================ PS.: remove the xx_ from email adr. to reply ============================================Article: 49781
I heartily disagree. Structural code, which is required for placement and
mapping in the code is probably the most portable way to write code in VHDL.
The same would be true with schematics if the tools shared a common file format,
but they don't. WIth HDL's the file format is common, so that is not an issue
here.
I know my structural code works properly under synplify, precision, leo and XST
with at most an attribute change (one or two lines per file, and you can use the
replace in all files in Aldec to do it in one fell swoop). I can also put the
attributes for all of these tools in, because they are non-interfering. It
isn't the structural code with the associated placement and mapping that causes
a problem, rather it is the RTL code that has been 'rope-pushed' that causes a
problem. That is part of the reason I opt for structural code when things are
critical. For example, this works in any of the above with a renaming on th
syn_translate off/on to the appropriate pragma in that tool. The rest of the
attributes are user attributes, which as long as your synth supports them is
portable. All the majors do now. This code snippet places SRL16's and FDRE's
in an array.
L:for i in 0 to width-1 generate
constant y:integer:= (btoi(row_limit/=0)*(i mod (row_limit+1)) +
btoi(row_limit=0)*(i/(col_limit+1)))*row_pitch;
constant x:integer:= (btoi(col_limit=0)*(i/(row_limit+1)) +
btoi(col_limit>0)*(i mod (col_limit+1)))*col_pitch;
constant xy_str:string:= "x"&itoa(x) & "y" & itoa((y/2)-origin);
constant k: integer:= x - col_pitch + (1-first_slice)*(1-2*btoi(col_pitch<0));
constant rc_str:string:= "R"&itoa(origin-(y/2)) & "C"&itoa(k/2) &".S" &
itoa((k+1) mod 2);
constant rloc_str : string := pickstring(virtex,rc_str,xy_str);
signal ds,qr,qs: STD_LOGIC;
attribute INIT of U0 : label is "AAAA";--INIT= attribute to pass to PAR
through synplicity
attribute BEL of U0:label is bel_lut(y mod 2);
attribute BEL of U1:label is bel_ff(y mod 2);
attribute BEL of U2:label is bel_ff(y mod 2);
attribute RLOC of U0 : label is rloc_str;
attribute RLOC of U1 : label is rloc_str;
attribute RLOC of U2 : label is rloc_str;
begin
U0: SRL16E
--synthesis translate_off
generic map ( -- init generic is for simulation model, not seen by Synplicity
or PAR
INIT => X"AAAA")--int2bit_vec(lut_init,16))
--synthesis translate_on
port map (
CLK => clk,
CE => weq,
A0 => dx0(i),
A1 => dx1(i),
A2 => dx2(i),
A3 => dx3(i),
D => wdq,
Q => ds);
U1: FDRE port map (
Q => qx(i),
D => ds,
R => lcl_rst,
CE => lcl_ce,
C => clk );
end generate L;
Austin Franklin wrote:
> Hi Ray,
>
> The point was "thwarting" was highly probable with mapping and placement
> when using HDLs, I don't believe I said file formats had anything to do with
> the aforementioned "thwarting"?
>
> Austin
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3DDABEA8.A7B00D8B@andraka.com...
> > But not nearly to the same degree. For the most part, a design will be
> > functional under any tool you compile it with. It is usually the
> attributes,
> > and in the case of some of the cheaper tools, unsupported language
> constructs
> > that thwart portability, not file formats.
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49782
How about a fixed oscillator and a PLL?
Anand wrote:
> Hi everybody,
>
> I am looking for a programmable oscillator for a board consisting
> mainly of a Xilinx Virtex 2000E . (XCV2000E)
>
> For this purpose I looked at DS1075 econ-oscillator ,but this
> oscillator is 5 V.
> On the other hand the Virtex-E I/O's ( I assume that I/O's include
> clock inputs)are 3.3 .
>
> Is there a solution for this problem ?
>
> I need to be able to program the clock in-circuit ?
>
> please do reply,
>
> thanks very much ,
> Anand Kulkarni
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49783
Big hint, use a more recent part. XC2S50 (50K marketing gates) can be
had in single quantities from Avnet for under $20, depending on the
package. These have more CLBs (16x24 IIRC), each of which has double the
resources of the XCS family CLBs, plus it has 8 4K memory blocks plus
clock DLLs.
Markus Wolfgart wrote:
> Hi NG,
>
> I'm a beginner in FPGA programming and would like
> to get some hints on some questions on FPGA programming.
>
> My local part distributor offers xcs-05-3-pc84 (plcc84 case)
> and xcs-10-3-pc84 Xilinx-FPGA's. (20$ and 40$ each)
>
> I would like to know what kind of project complexity I'm able
> to realize (when having the knowledge) with 100 CLBs / 360 FF /
> 5000 gates in the xcs-05 fpga and 196 CLBs / 616 FF / 10k gates
> in the xcs10 fpga.
>
> Am I able to realize a USB V1.1 Master Core or a PCI 2.1 compliant
> core or a TFT-DVI interface.
> Need I the Spartan-XL features to realize the above mentioned goals?
> (especially the io-latches feature and the 3.3V Supply instead of 5V)
>
> Any hints are welcome
>
> Many thanks in advance
>
> Markus
>
> ============================================
>
> Markus Wolfgart
>
> DLR
>
> ============================================
> PS.: remove the xx_ from email adr. to reply
> ============================================
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49784
I stand by my claims...all of them. The Virtex does have a look ahead carry
built into the carry chain on a bit pair basis, however this logic is hidden
from the user (it does show through in the delay model though, the delays for
both bits in a slice are the same). The circuit shown in the data books is a
functional equivalent, not the circuit implemented in the silicon. The circuit
in the silicon does utilize carry look ahead at the slice level. The carry
chain in all the Xilinx products is dedicated logic AND routing.
If your G and P circuit is running faster than your ripple carry adders for
under 32 bits, then you are either not using the carry chains or you have long
routes leading into the carry chain logic (try floorplanning, and put a register
immediately adjacent to the carry chain inputs). Depending on the device family
and speed grade, the carry chain propagation is on the order of .1 to .2 ns per
bit pair plus the delay getting on/off the chain. Prop time through a LUT plus
minimal route is 10 to 20x that. Until you get to very wide adder widths (and
for the very small ones where the on/off times become significant), the built in
carry chains will beat any attempt at faster arithmetic using the general
purpose logic and interconnect. If your design is too fast for the carry
chains, it will also be too fast for user constructed fast carry logic unless
that is very deeply pipelined (and at that point you are much better off using
two parallel paths and processing the data split phase).
I challenge you to show me a 16 bit adder that is faster than a 16 bit adder
using the carry chain for one of the Virtex families.
Stan wrote:
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3DDB109D.D0CD8056@andraka.com...
> > The reason for doing a carry save adder is to defer the add carry to the
> last
> > adder in the tree. Normally this is done in order to permit construction
> of
> > just one fast adder. The speed of an adder tree is limited by the speed
> of
> > the propagation through any path in the tree, and the worst case paths are
> > from the lsb of an input to the msb of the output. In other technologies,
> a
> > ripple carry adder is slower than fancier carry look-ahead schemes, but
> the
> > fancy schemes take up considerably more logic. By deferring the carry to
> the
> > last stage, one only has to build one of these expensive adders. The rest
> of
> > the adders have the same cost as the ripple carry adder but without the
> ripple
> > propagation. So by doing this, you speed up the adder tree as if all the
> > adders were the more expensive fast adders.
> >
> > Now enter the FPGA, with its dedicated adder carry chains (these actually
> do
> > have some carry look-ahead built in, but it is hidden from the user).
>
> No they don't, not Virtex anyway! It's strictly ripple carry. The ripple
> carry is very fast because there are special goodies in both synthesis and
> P&R to optimize them, but it's good old simple ripple carry propagation,
> bit-by-bit. In fact, if the ripple carry is not fast enough, Xilinx P&R
> refuses to do any P&R at all! No, if you want a parallel carry look-ahead,
> you code all the Gs and Ps youself. Which I have done!
>
> > In the
> > case of the FPGA it is very hard, impossible in many cases, to build an
> adder
> > that is faster than the built in adder function because the dedicated
> > resources are so much faster than the general purpose routing.
>
> zzzt! Does not compute!
>
> > Since that
> > ripple adder is the fastest one can build in the fpga, there is no penalty
> (in
> > fact there is an advantage) to using them through out the adder tree
> rather
> > than only at the final add. The advantage is that by doing this, all the
> > carry logic is put on the dedicated resources, so you essentially get the
> > carry half of all the 3:2 adders for free. If you decided to build an
> adder
> > without using the chains (including the Carry Save type), you need two
> LUTs
> > per full adder instead of the one because you can't take advantage of the
> > dedicated carry logic, so not only do you get no speed advantage in an
> FPGA by
> > using a CSA tree, but you also get soaked for twice the resources, and in
> fact
> > you get a speed degradation due to the irregular routing.
> >
> > The bottom line is that carry save adder trees DO NOT MAKE SENSE for FPGAs
> > that have dedicated adder resources.
>
> Does not compute! Run Will Robinson run! -the robot
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49785>I would like to know what kind of project complexity I'm able >to realize (when having the knowledge) with 100 CLBs / 360 FF / >5000 gates in the xcs-05 fpga and 196 CLBs / 616 FF / 10k gates >in the xcs10 fpga. I suggest doing enough of a design so that you can answer that question yourself. Or finding a design you can push through the tools far enough to get some numbers. You might get some ideas by browsing in opencores.org. Here is a URL to a PCI bridge that uses 1300 slices and some RAM, but that's a test chip that includes a bridge and CRT core too. http://www.opencores.org/projects/pci/ Maybe if you look harder than I did you can find a breakdown. [I also second Ray's suggestion to use a newer part.] -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 49786
Well, it does not seem to work. The "Properties" dialog box for PCI printer does not report I/O range at all (because it is an emulation, not a physical port). Instead I have tried to use addresses of resources listed for the PCI card, but it does not work, too. Is your solution implemented in Impact 4.2? Today I expect to get another PCI I/O card. Then I will try to run Impact with this new one. Thanks for help, anyway. Dziadek "Neil Glenn Jacobson" <neil.jacobson@xilinx.com> wrote in message news:3DDC0AF3.566AC256@xilinx.com... > As a workaround for this situation use the XIL_IMPACT_ENV_LPT1_BASE_ADDRESS > environment variable in iMPACT. If this variable is set, the specified value will be used as the > port address for the lpt port. > The port base address is listed as a resource in Windows Device Manager->Ports->LPTx devices. Right > click on an LPT > device, then select Properties->Resources->Input/Output Range. > > From a command window set the aforementioned env variable prior to invoking iMPACT. > Specify the port base address value in hex. > > ex. set XIL_IMPACT_ENV_LPT1_BASE_ADDRESS=378 > > This will set the LPT1 base address. LPT2, LPT3 and LPT4 are also supported > > > > Dziadek wrote: > > > Hi, > > The motherboard printer port in my PC is used by some hardware, so I have to > > connect the Parallel Cable to another printer port on an PCI I/O card. The > > port is EPP etc, but - as I suppose for most PCI printer ports - does not > > use the original printer port addresses (378,etc.) but some other in PCI > > space. > > The Impact programmer does not locate the cable. The cable works OK when > > connected to standard printer port. > > Does anybody use the Parallel Cable with PCI printer port? Does it work at > > all or maybe there are some hints to make it running? > > > > TIA > > Dziadek >Article: 49787
Best way is to use a single fast clock and sample the signals. But if you want it to implement it in multiple clocks and doesn't want xilinx to use global clocks then you can use some attributes in synthesis ... like for synplify you can use syn_noclockbuf attribute .. you can find something similar in Leonardo spectrum or you can instantiate IBUFs for the clock signals. I guess this way you can prevent xilinx from using global clocks. -Vishker "Mirko Scarana" <mirko.scarana@tiscali.it> wrote in message news:<295d08614c0ab0edc721718738d6dbca.114635@mygate.mailgate.org>... > Hi all, > I am relatively new to fpga design, and I am experiencing a problem with > global clock routing. > I am using ISE v5.1 targeting a Xilinx x2v500fg456 device. > The point is that my design uses some (slow) signals to edge-trigger > different internal registers. > When it comes to the place & route phase, the tool tries to consider all > those signals as global clocks and fails the routing. > Apart from modifying the design by avoiding edge-triggering on those > signals, is it possible to force the P&R tool not to route the signals > as global clocks? > By the way, the signals are internally generated, they are not external > inputs. > Thanks in advance, best regards. > > Mirko Scarana > PhD Student > "La Sapienza" University of RomeArticle: 49788
Phil Connor <phil_j_connor@hotmail.com> wrote: > Hi Holger, > > You may be right but if this works I wonder what entirely > combinational logic would be synthesised? Effectively, the same kind of "combinational" logic that rising_edge() would result in. It is likely the logic is not strictly "combinational" any more - your categorization is wrong IMHO: Even if you build a circuit from gates it is no longer combinational when there is a feedback. To detect a single distinct edge, you need some kind of a storage for the previous value somehow - this may be a delay element or a flip flop. In this case you rely on timing effects, and purely boolean algebra does no longer apply (temporal logic does). Thus the circuit is probably still digital, but no longer combinational. Holger -- Please update your tables to my new e-mail address: holger.veit$ais.fhg.de (replace the '$' with '@' -- spam-protection)Article: 49789
Markus Wolfgart <xx_markus.wolfgart@dlr.de> wrote: : Hi NG, : I'm a beginner in FPGA programming and would like : to get some hints on some questions on FPGA programming. : My local part distributor offers xcs-05-3-pc84 (plcc84 case) : and xcs-10-3-pc84 Xilinx-FPGA's. (20$ and 40$ each) : I would like to know what kind of project complexity I'm able : to realize (when having the knowledge) with 100 CLBs / 360 FF / : 5000 gates in the xcs-05 fpga and 196 CLBs / 616 FF / 10k gates : in the xcs10 fpga. : Am I able to realize a USB V1.1 Master Core or a PCI 2.1 compliant : core or a TFT-DVI interface. : Need I the Spartan-XL features to realize the above mentioned goals? : (especially the io-latches feature and the 3.3V Supply instead of 5V) Just asking another question on your question: Why do you wnat to go with such old devices for a design-in. The Spartan II family should is also 5 Volt tolerant, while giving more cells per buck, is programmable with the free Webpack and is readily available with catalogue distributors, e.g. Schukat carries the smallest device, a XC2S15-5TQ144 for about 15 Euro. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 49790
Hi Rick, I used almost word for word the code suggestion of Joe. (Thanks Joe!) This produces a negative edge on the first change of any input after the clock is stopped (which is all I need). The signal then resets to high when the clock starts again. The application , as others have guessed, is a wake-up from sleep mode. The code simulates fine in post-route and I've not seen the short pulses you mention but you've got me worried enough to go back and re-check it. You clearly have a good understanding of what logic will be produced. I wonder though if you're taking account of the clock being stopped and so the short pulses can become a continuous state. However, all this is only a work-around to get to a practical solution. To strictly answer my original posting it seems the answer is that it is impossible. That is, given a toggling signal there is no purely combinational logic that will pick out only the negative edges. Unless anybody knows different....... Regards PhilArticle: 49791
Hi all,
I'm trying to use the logick lock methodology from Altera but
with little (if none) success. Furthermore, I would like to
use scripts to perform all the steps.
I'm using Leonardo 2002e and Quartus 2.0.
The entry is VHDL.
For the moment, I would like to try a very simple architecture which
hierarchy is :
A top level controleur_can_periodique embeds a module controleur_can
and some processes.
I managed to produce separate edif files for the entities
and produce an atom controleur_can.vqm but I don't know how to
import it on the top file. Indeed I do it but I don't know if
I produced a good vqm file as I get messages such as :
Info: WYSIWYG I/O primitives converted to equivalent logic
Info: WYSIWYG I/O primitive
controleur_can:inst_controleur_can|convertit~I converted to equivalent logic
did I put some I/O on my sub-module ? How to prevent this ?
Also, why does quartus produces .sof file for the sub-module ?
So, could someone tell me :
- how many scripts do I need for leonardo, quartus (one for each module ?)
and how to use them
- what should I put in them
- How, and when, to use the command cmp logiclock_import
Indeed, the quartus compiler stops if I use it as stated in the Altera
Application Note 195 (Scripting with Tcl ....)
The following piece of code doesn't seems to work
while { [cmp is_running] } {
FlushEventQueue
puts "--- Importing LogicLock Regions ---"
# Import all LogicLock regions for the project.
cmp logiclock_import
}
So I've tried to compile without logiclock_import (silly ?)
Could someone give me some light ?
It would be wonderfull if you have a set of simple VHDL files and all the
scripts to produce the final .sof file.
Thanks very much for your help
Stephane Mancini
Article: 49792
I synthesize my design by FPGA compiler II. Maxplus2 compile the *.edf
netlist and I select VHDL output(*.vho) and delay output(*.sdo). The
*.vho and *.sdo will be feed to third party EDA for timming
simulation. But maxplus2 always flatten bus of the top-design even if
I turn off "flatten buses" option in maxplus2. And I try each bus
style in FPGA compiler II when exporting netlist, including %s(%d:%d),
%s[%d:%d], %s{%d:%d}, %s<%d:%d>. Maxplus2 still flatten the bus, does
the maxplus2 can't support grouped or un-flattened bus? Or I neglect
some option setting? I don't want to expanded bus, because it is not
convenient for the connection of top design to testbench signals.
FOR example:
$original bus
MAD: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
$after FC-II synthesis and maxplus2 processing=> VHDL output(*.vho)
MAD[0] : IN std_logic; bus has expand as sigle I/O port
MAD[1] : IN std_logic;
MAD[2] : IN std_logic;
Article: 49793Haven't encountered this error before... I am building a truncating module in schematics by simply using a bus tap to take off a sub-bus. Main bus is 15bits wide, and I am taking bits 12-8. ISE complains that the bus and sub-bus cannot be connected to different I/O markers... how do I get around this?? thanks adrianArticle: 49794
Hello,
I have a problem when I want to simulate my synthesized project with
Modelsim 5.6a. First I wrote a little VHDL programm with FPGA-Advantage 5.3:
-- This is only a test-programm and didn't make any sense.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY uut IS
port(
clk : in std_logic;
a : in std_logic;
b : in std_logic;
sel : in std_logic;
q : out std_logic
);
END uut ;
ARCHITECTURE design_rtl OF uut IS
BEGIN
mux : process(clk)
begin
if clk'event and clk = '1' then
q <= a;
if sel = '1' then
q <= b;
end if;
end if;
end process mux;
END design_rtl;´
Then I synthesized the code with Leonardo Spectrum and got a *.vhd file
containing the following code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim ;
use unisim.all ;
package vcomponents is
component IBUF
port (
O : OUT std_logic ;
I : IN std_logic) ;
end component ;
component OFDX
port (
Q : OUT std_logic ;
C : IN std_logic ;
D : IN std_logic ;
CE : IN std_logic := '1' ;
GSR : IN std_logic := 'Z' ;
GTS : IN std_logic := '0') ;
end component ;
component BUFG
port (
O : OUT std_logic ;
I : IN std_logic) ;
end component ;
end vcomponents ;
package body vcomponents is
end vcomponents ;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim ;
use unisim.all ;
entity uut is
port (
clk : IN std_logic ;
a : IN std_logic ;
b : IN std_logic ;
sel : IN std_logic ;
q : OUT std_logic) ;
end uut ;
architecture design_rtl of uut is
signal clk_int, a_int, b_int, sel_int, nx6: std_logic ;
begin
sel_ibuf : unisim.vcomponents.IBUF port map ( O=>sel_int, I=>sel);
b_ibuf : unisim.vcomponents.IBUF port map ( O=>b_int, I=>b);
a_ibuf : unisim.vcomponents.IBUF port map ( O=>a_int, I=>a);
reg_q : unisim.vcomponents.OFDX port map ( Q=>q, C=>clk_int, D=>nx6,
CE=>
OPEN, GSR=>OPEN, GTS=>OPEN);
clk_ibuf : unisim.vcomponents.BUFG port map ( O=>clk_int, I=>clk);
nx6 <= (a_int and not sel_int) or (b_int and sel_int) ;
end design_rtl ;
Now I want to simulate this code. But when I try to compile it I receive the
following error message:
ERROR:
D:/projekte/FPGA-Advantage/simu/ls/uut_design_rtl/netlists/uut_design_rtl.vh
d(64): Unknown identifier: gsr.
ERROR:
D:/projekte/FPGA-Advantage/simu/ls/uut_design_rtl/netlists/uut_design_rtl.vh
d(64): Unknown identifier: gts.
What did I wrong? The librarys unisim and simprim I compiled with a *.tcl
script from Xilinx to use them with Modelsim and I defined these libraries
as Standard Libraries in FPGA-Advantage.
Note: Simulation after Place&Route works perfectly.
Thanks for any help
Michael
Article: 49795"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:ari76b$210$1@news.tu-darmstadt.de... > Markus Wolfgart <xx_markus.wolfgart@dlr.de> wrote: > : Hi NG, > > Why do you wnat to go with such old devices for a design-in. > > The Spartan II family should is also 5 Volt tolerant, while giving more > cells per buck, is programmable with the free Webpack and is readily > available with catalogue distributors, e.g. Schukat carries the smallest > device, a XC2S15-5TQ144 for about 15 Euro. One big advantage with the old devices is that they come in PLCC, making prototyping very easy. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 49796
If you insist on needing local clocks, you need to be very careful about clock skew. Normally, you'll want to keep the number of
flip-flops clocked by the local clock to an absolute minimum. In most cases however, using local clocks is unnecessary.
Vishker wrote:
> Best way is to use a single fast clock and sample the signals. But if
> you want it to implement it in multiple clocks and doesn't want xilinx
> to use global clocks then you can use some attributes in synthesis ...
> like for synplify you can use syn_noclockbuf attribute .. you can find
> something similar in Leonardo spectrum or you can instantiate IBUFs
> for the clock signals. I guess this way you can prevent xilinx from
> using global clocks.
>
> -Vishker
>
> "Mirko Scarana" <mirko.scarana@tiscali.it> wrote in message news:<295d08614c0ab0edc721718738d6dbca.114635@mygate.mailgate.org>...
> > Hi all,
> > I am relatively new to fpga design, and I am experiencing a problem with
> > global clock routing.
> > I am using ISE v5.1 targeting a Xilinx x2v500fg456 device.
> > The point is that my design uses some (slow) signals to edge-trigger
> > different internal registers.
> > When it comes to the place & route phase, the tool tries to consider all
> > those signals as global clocks and fails the routing.
> > Apart from modifying the design by avoiding edge-triggering on those
> > signals, is it possible to force the P&R tool not to route the signals
> > as global clocks?
> > By the way, the signals are internally generated, they are not external
> > inputs.
> > Thanks in advance, best regards.
> >
> > Mirko Scarana
> > PhD Student
> > "La Sapienza" University of Rome
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49797Hi all, can somebody help me with the following problem? The target device is a Xilinx Virtex FPGA (speed gr. -6) Data is available to the FPGA from outside in a small window 1.5ns before CLK and stays at the inputs until 800ps after CLK. I read that data into IOB registers on each rising edge of CLK. I have set constraints on the inputs as follows: NET "dimmcsxsib" OFFSET = IN 1.5 ns BEFORE "dimmclkxci" Now, without using a DLL for dimmclkxci, I get Tsetup = 2.3 ns, Thold = 0.0 from the static timing analyzer, with Tsetup violating my constraint. Without the IOB delay element, I get Tsetup = 0.509ns, Thold = 0.943ns Now, the window is considerably smaller, but Thold violates my constraints. With dimmclkxci going through a DLL, I get Tsetup = 1.7 ns, Thold = -0.4 ns which looks promising but still violates the constraint. Forcing the DLL to bring the rising edge of CLK0 earlier by inserting more buffers into the feedback line doesn't seem to work (I have two BUFG in series, so it's clear that the 2nd BUFG isn't driven by a CLKDLL...): ERROR:LIT:179 - BUFG symbol "dlldlybufg" (output signal=s2) is driving a CLKDLL. When the CLKIN pin or the CLKFB pin of a CLKDLL is being driven by a BUFG,the BUFG must also be driven by a CLKDLL. To by-pass this error, set environment variable XIL_MAP_ALLOW_ANY_DLL_INPUT. The mapper seems to ignore the XIL_MAP_ALLOW... env variable, because I still get the error after setting it to 1. Can anybody help me here? Thank you, AndyArticle: 49798
Vincent PINON wrote:
> Hello,
>
> I need to program an Altera Flex10k under Linux
> (embedded LFS with very few resources).
>
> I have heard of the Bitblaster abilities for simple PS programming,
> but the cable is too big (and expensive).
>
> With the Byteblaster (that can be soldered directly on the board),
> it seems that the only solution is to use Max+2...
> much too heavy for a simple programmer.
>
> According to what I have read on the web,
> the "Jamplayer" should be a good solution...
> But I didn't find that soft anywhere !
>
> If you know a free open-source software,
> or at least the protocol to write into the FPGA,
> you could help me a lot ;-)
>
> Vincent.
Vincent,
Here is a function for configuration of Flex10K,
running under Linux. My program does serial
configuration through PCI, so the rest is probably
not relevant to you.
This source won't compile directly, but if you regard
it as pseudo-code, it should be easy to do include this in
your own program. The 'progress' argument is a function
callback to implement progress bars. The function reads
data taken directly from the *.TTF file created by MaxPlus2.
To access the parallel port under Linux, you can either
directly access the hardware (iopl, needs root) or use the
parport driver.
Kind regards,
Iwo
===============
long int Altera_Config(long int bytes,void (*Progress)(int percent))
{
long i,to,tick,tc;
unsigned char b,v;
int percent;
T_nCONF(0);
T_CLK(0);
T_DTA(1);
usleep(1*1000);
T_nCONF(0);
usleep(1*1000);
T_nCONF(1);
for (to=timeout; to>0; to--)
{
usleep(1*1000);
if (T_nSTAT() != 0) break;
}
if (to==0) return(-1);
tick = bytes / 100; tc=tick; percent = 1;
for (i=0; i<=bytes; i++)
{
tc--;
if (tc==0)
{
Progress(percent++);
tc=tick;
}
v = SOF[i];
if (T_nSTAT() == 0)
{
return(i+1); /* Point of failure */
}
for (b=0; b<8; b++)
{
if (Bit(0,v)) T_DTA(1); else T_DTA(0);
T_CLK(0); T_CLK(1);
v >>= 1;
}
}
/* more clocks required... */
for (i=0; i<40; i++)
{
T_CLK(1);
T_CLK(0);
}
/* Wait for CONFIG_DONE */
for (to=timeout; to>0; to--)
{
usleep(1*1000);
if (T_CONF_DONE() != 0) break;
}
if (to==0) return(-1);
return(0);
}
Article: 49799Dear all, I have a question about Xilinx's ISE tool regarding clock enable input of FFs. I use FFs with clock enable input(that is FDCE) and constrain clock frequency with PERIOD attribute. The timing analyzer will check all data paths between two FFs whether the sets of path delay are within specified value with respect to the constrain. Likewise, are paths to clock enable input of FFs also setup/hold timing-checked at this time ? Thanks, Hiro
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