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Hi, I am using Xilinx 5.1i targeting a XC2S200 part w/Leonardo spectrum. The problem I am having concerns slice usage. The Leonardo outout reports 71% usage, the mapper in 5.1i reports 91% - why??? I have replicate logic turned off in the map options and it doesn't seem like 91% in the floor planner tool - am I in trouble with space? Interpreting the number wrong? some other dependency? please let me know. Mike D.Article: 51276
Hi, I am a newbie in FPGA field.I often heard people are talking about the power consumption of the clock inside FPGA.What's the main issue of it? Will the clock line consume lots of power? Thank you very much! sincerely ------------- Kuan Zhou ECSE departmentArticle: 51277
Hi, Does anyone know what is the best choice for an fpga developement kit? Altera offers this kit for University student : http://www.altera.com/education/univ/kits/unv-kits.html I wonder if there are other supplier of boards like this (could be Xilinx too) that could compete with this. Are there third party manufacturer that are worth considering? Thanks DavidArticle: 51278
In article <d977c973.0301091237.27e58ed3@posting.google.com>, Frederic Bastenaire <fba@free.fr> wrote: >> >> The mode pin is already connected to gnd, so the transceiver runs in >> mode 0. Our Documentation is wrong here (thank you for the hint) and we >> will fix it. >> This applies to both, TE-XC2Se and TE-BL from TE-XC2S. >> >> However you never need to add a wire to the board, as you can simply >> sort out such things in the fpga. >> >> best regards >> Thorsten > >Hello, > >I am using a TE-XC2S system. Could you please tell me exactly what >is wrong in the TE-BL documentation? The MODE pin is shown to be >connected to ground. What is exactly the problem and how should it be >solved on FPGA side? > >Yours, > >FB The MODE pin should be connected to ground. I was looking at the description of the USB interface in the TE-XC2Se documentation, where the last paragraph says that the PDIUSBP11A is set to mode 1. I believe this is what Thorsten is referring to above. -- Caleb Hess hess@cs.indiana.eduArticle: 51279
> > Hi, > > > > Can anyone point me to some good references on using external RAM with > > FPGA's (specifically Spartan IIE). Sorry, I have no reference when built my FPGA/SRAM interface, but little hint is using the WE (write enable) and RE (read enable) properly will max your performent, consider using DLL to controll your clock phase > > Would it be possible to implement using a > > schematic design (which I prefer)? > > Yes, y not? > > Thanks > > > > AdrianArticle: 51280
Many of these app notes are found under the "Memory Corner" at http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Memory+Corner Marc Randolph wrote: > "Noddy" <g9731642@campus.ru.ac.za> wrote in message news:<1042095472.447551@skink.ru.ac.za>... > > Hi, > > > > Can anyone point me to some good references on using external RAM with > > FPGA's (specifically Spartan IIE). Would it be possible to implement using a > > schematic design (which I prefer)? > > Xilinx has a number of app notes on their web site for interfacing to > external memory. > -- Marc Baker Xilinx ApplicationsArticle: 51281
Almost all FPGA power is due to the charging and discharging of internal capacitances. The metal lines distributingthe clock(s) all over the chip have a substantial capacitance, and clocks have the highest frequency of any signal on the chip. That's why clock power can be (up to?) a third of total power, but this fraction depends very much on the design style. Peter Alfke, Xilinx Applications ================================== Kuan Zhou wrote: > Hi, > I am a newbie in FPGA field.I often heard people are talking about the > power consumption of the clock inside FPGA.What's the main issue of it? > Will the clock line consume lots of power? > > Thank you very much! > > sincerely > ------------- > Kuan Zhou > ECSE departmentArticle: 51282
A Xilinx rep really tried to push the Virtex-II Pro on us. He said it is the next generation of the Virtex family and has a smaller die and will be cheaper. Does anyone else see a problem with this? I think the chip has some really nice features, but it is a POINT solution. It needs to be an offshoot to the main product family. I don't need the SerDes for most designs. And I am not going to use the embedded 405 processor when I can just plop down a $25 405 chip and not worry about all the headaches of trying to deal with a processor inside an FPGA. For an analogy, imagine if Ford decided to put a tractor shovel in the front of their new Ford Explorer. It would be pretty cool if you needed it, but most people don't need it. Imagine if they said "It's the only way you can buy the new Explorer, but don't worry, it's cheaper than last year's Explorer." Does this explanation convince you to buy the car? I certainly hope that Xilinx comes to their senses and continues the Virtex line WITHOUT the embedded SerDes and processor. Then I get my IO count back. They can continue the Pro line for those who need these features. -tomArticle: 51283
There is some miscommunication here: If you are happy with Virtex-II, keep buying and using it. End of story. If you like an on-chip PowerPC microprocessor for free, drastically reducing you package pin-count and board area, and/or of you want to narrow down you busses by going gigabit serial, then buy and use Virtex-IIPro. If you like neither the PowerPC nor the gigabit I/O, look at the price and the available I/O and make your (as usual) intelligent decision. We are not forcing anything upon you, we just make a tempting offer, "lower price for more functionality". Should make you happy either way. Peter Alfke, Xilinx Applications tbiggs wrote: > A Xilinx rep really tried to push the Virtex-II Pro on us. He said it > is the next generation of the Virtex family and has a smaller die and > will be cheaper. > > Does anyone else see a problem with this? I think the chip has some > really nice features, but it is a POINT solution. It needs to be an > offshoot to the main product family. > > I don't need the SerDes for most designs. And I am not going to use > the embedded 405 processor when I can just plop down a $25 405 chip > and not worry about all the headaches of trying to deal with a > processor inside an FPGA. > > For an analogy, imagine if Ford decided to put a tractor shovel in the > front of their new Ford Explorer. It would be pretty cool if you > needed it, but most people don't need it. Imagine if they said "It's > the only way you can buy the new Explorer, but don't worry, it's > cheaper than last year's Explorer." Does this explanation convince you > to buy the car? > > I certainly hope that Xilinx comes to their senses and continues the > Virtex line WITHOUT the embedded SerDes and processor. Then I get my > IO count back. They can continue the Pro line for those who need these > features. > > -tomArticle: 51284
Peter Alfke wrote > There is some miscommunication here: > If you are happy with Virtex-II, keep buying and using it. End of story. > If you like an on-chip PowerPC microprocessor for free, drastically > reducing you package pin-count and board area, and/or of you want to > narrow down you busses by going gigabit serial, then buy and use > Virtex-IIPro. Does "for free" mean that V-II and V-IIPro cost the same at equivalent LUT counts?Article: 51285
I appreciate the help from all, I have some good ideas to start with. Thanks Jason "Jason Berringer" <jberringer@trace-logic.com.delete> wrote in message news:ptIR9.16736$VW5.1466136@news20.bellglobal.com... > Hello All, > > I'm working on a rather trivial project for myself to help me get further > acquainted with FPGAs and VHDL in particular (No I'm not a student, I'm > educating myself, or trying to). > > I'm attempting to build a voltmeter. I'm using an ADC tied to the FPGA and > then eventually I want to output the reading on a LCD display also tied to > the FPGA. I'm a little bit confused as to the steps needed to get from one > end to the other. Firstly my values coming from the ADC are binary values, > so I have to convert them to an integer (I'm assuming) then I have to do > some multiplication and division to get my final result which will be a > fixed point number (again an assumption but I want at least one decimal > place for accuracy). Then this value must be converted somehow so that I can > send it to the LCD. I understand a BCD to hex converter for the display, but > how does one convert say a 16 bit fixed point number to a unit that can be > displayed. > > I would appreciate any pointers or useful links that may help me discover > all of the steps required to do this. I know that there are ICs to do this > already out there, but that isn't any fun, and they won't help me learn > anything. > > Thanks for the help (in advance) > > Jason > >Article: 51286
Jason Berringer wrote: > > Hello All, > > I'm working on a rather trivial project for myself to help me get further > acquainted with FPGAs and VHDL in particular (No I'm not a student, I'm > educating myself, or trying to). > > I'm attempting to build a voltmeter. I'm using an ADC tied to the FPGA and > then eventually I want to output the reading on a LCD display also tied to > the FPGA. I'm a little bit confused as to the steps needed to get from one > end to the other. Firstly my values coming from the ADC are binary values, > so I have to convert them to an integer (I'm assuming) then I have to do > some multiplication and division to get my final result which will be a > fixed point number (again an assumption but I want at least one decimal > place for accuracy). Then this value must be converted somehow so that I can > send it to the LCD. I understand a BCD to hex converter for the display, but > how does one convert say a 16 bit fixed point number to a unit that can be > displayed. > > I would appreciate any pointers or useful links that may help me discover > all of the steps required to do this. I know that there are ICs to do this > already out there, but that isn't any fun, and they won't help me learn > anything. If you choose one of the 'ADC's with uC', you can choose how much/little to process in the FPGA, and have the learning advantage of an always-working system, and a code template. Good examples of these are 24 Bit ADC, plus FLASH uC - sub $10 http://www.ti.com/msc 16/24 bit ADC plus FLASH uC - http://www.analog.com/microconverter or, you could pull the ADC inside the FPGA. Candidates for this would be Dual-Slope ADC, or Sigma-Delta ADC. In both cases, make the totaling counters BCD, not binary, and you avoid entirely the Bin-Decimal conversion. In Voltmeters, decimal point is typically external, and tracks the IP attenuator, so the ADC is a 1999, 3999, 9999 etc counter, and the DP is decided by the Analog system gain. LCD choices are Character Module, or Direct Drive. Direct drive needs a backplane, and suits 7 segment displays - BCD-7seg is a straight forward ROM in FPGA/CPLD. Character Modules need an INIT string, and a Set-Cursor preamble, and can work in 4 bit or 8 bit modes. These would suit a 'code it in uC-ASM, then re-code in VHDL' development path. -jgArticle: 51287
In article <avl311$p4d$1$8302bc10@news.demon.co.uk>, Tim <tim@rockylogic.com.nooospam.com> wrote: >Does "for free" mean that V-II and V-IIPro cost the same at >equivalent LUT counts? From the die area viewpoint, each SerDes only removes a (singular) BlockRAM. Similarly, the processor is, IIRC, 64 CLBs and 4 BlockRAMs. Removing these from the V-IIPro parts results in nearly trivial area savings, but cut out a huge amount of functionality. I heard the same arguments on BlockRAMs with respect to the Virtex parts. If you look at the die, you realize the SerDes'es and processor are very small, and incredibly useful considering the small cost. If you don't use them, the cost (silicon area) is very low. If you do use them, they are critical! -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 51288
From Avnet xc2vp4FG256 3008 slices 1 PPC 4 RIO $180 xc2v500FG256 3072 slices $149 Right now it will cost you $30 bucks to get the PPC and Rocket IO. Of course the Pro came out after the V2 so the prices are a little higher. When all the embedded people start using the Pro and the volume goes up I think the Pro will cost less than the V2 for the same amount of slices. So PPC will be _less_ than free. You'll have to pay more money not to have one. Steve "Tim" <tim@rockylogic.com.nooospam.com> wrote in message news:avl311$p4d$1$8302bc10@news.demon.co.uk... > Peter Alfke wrote > > There is some miscommunication here: > > If you are happy with Virtex-II, keep buying and using it. End of story. > > If you like an on-chip PowerPC microprocessor for free, drastically > > reducing you package pin-count and board area, and/or of you want to > > narrow down you busses by going gigabit serial, then buy and use > > Virtex-IIPro. > > Does "for free" mean that V-II and V-IIPro cost the same at > equivalent LUT counts? > > > >Article: 51289
Steve Casselman wrote: > > From Avnet > xc2vp4FG256 3008 slices 1 PPC 4 RIO $180 > xc2v500FG256 3072 slices $149 > > Right now it will cost you $30 bucks to get the PPC and Rocket IO. Of course > the Pro came out after the V2 so the prices are a little higher. When all > the embedded people start using the Pro and the volume goes up I think the > Pro will cost less than the V2 for the same amount of slices. So PPC will be > _less_ than free. You'll have to pay more money not to have one. Hmmm - hard to believe. There could be some merit in a 'same-pinout Pro', with the Processor disabled/untested/yield fallout, but the testing time / Yield factors of the processor core, would dominate over the supposed 'small die area', so the 'For Free' claim has to be fed through the standard Marketing English -> Fact filter. -jg > "Tim" <tim@rockylogic.com.nooospam.com> wrote in message > news:avl311$p4d$1$8302bc10@news.demon.co.uk... > > Peter Alfke wrote > > > There is some miscommunication here: > > > If you are happy with Virtex-II, keep buying and using it. End of story. > > > If you like an on-chip PowerPC microprocessor for free, drastically > > > reducing you package pin-count and board area, and/or of you want to > > > narrow down you busses by going gigabit serial, then buy and use > > > Virtex-IIPro. > > > > Does "for free" mean that V-II and V-IIPro cost the same at > > equivalent LUT counts?Article: 51290
Has to do with packing. Xilinx reports a slice used if either or both LUTs are
used. I think Leo assumes slices will be packed as tightly as possible.
Compare the LUT counts for a fairer comparison.
Mike D wrote:
> Hi,
> I am using Xilinx 5.1i targeting a XC2S200 part w/Leonardo spectrum. The
> problem I am having concerns slice usage. The Leonardo outout reports 71%
> usage, the mapper in 5.1i reports 91% - why??? I have replicate logic turned
> off in the map options and it doesn't seem like 91% in the floor planner
> tool - am I in trouble with space? Interpreting the number wrong? some other
> dependency? please let me know.
>
> Mike D.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 51291In article <3E1E2306.781A@designtools.co.nz>, Jim Granville <jim.granville@designtools.co.nz> wrote: >Hmmm - hard to believe. No it isn't. As I said in my other post, both the RocketIOs and the PowerPCs are small. You would only get some 64 more CLBs and 4 BlockRAMs if you removed the PowerPC, IIRC. Yet the V2Pro is a process shrink, which makes the cost per transistor considerably lower. So you spend a few transistors on a processor, the cheaper transitors means the net cost ends up being lower. >There could be some merit in a 'same-pinout Pro', with the Processor >disabled/untested/yield fallout, but the testing time / Yield factors >of the processor core, would dominate over the supposed 'small die >area', so the 'For Free' claim has to be fed through the standard >Marketing English -> Fact filter. Except that the circuit density on the FPGA and the PowerPC are about the same, and they have the same defect tolerance, namely none. Thus, being such a small percentage of the die, the probability of a failure in the PPC is very low. It's hard to convince people theses days that an in order, single pipeline, small cache processor is effectively free on modern silicon. But it is. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 51292
It all has to do with volume. If the Pro gets in more designs than the V2 then a larger Pro die will cost less than a smaller V2 die. I think in 5 years all FPGAs will have processors. Right now all the new FPGAs have multipliers and block ram whether you use them or not. All the Xilinx have distributed ram which is not free but nobody complains about that. In the future look for other functions to be on all parts like A to D and D to A converters. About ten years ago someone said to me "FPGAs will never replace processors because of A, B, C..." I still say if A B and C are needed to have a full system then some day you will find them inside a FPGA. Even today a lot of cost is in the packaging and not the silicon. For example the xc2v500 in the 456 pin package is $322 so the package costs more than the silicon. You can expect this trend to continue.... Steve "Jim Granville" <jim.granville@designtools.co.nz> wrote in message news:3E1E2306.781A@designtools.co.nz... > Steve Casselman wrote: > > > > From Avnet > > xc2vp4FG256 3008 slices 1 PPC 4 RIO $180 > > xc2v500FG256 3072 slices $149 > > > > Right now it will cost you $30 bucks to get the PPC and Rocket IO. Of course > > the Pro came out after the V2 so the prices are a little higher. When all > > the embedded people start using the Pro and the volume goes up I think the > > Pro will cost less than the V2 for the same amount of slices. So PPC will be > > _less_ than free. You'll have to pay more money not to have one. > > Hmmm - hard to believe. > > There could be some merit in a 'same-pinout Pro', with the Processor > disabled/untested/yield fallout, but the testing time / Yield factors > of the processor core, would dominate over the supposed 'small die > area', so the 'For Free' claim has to be fed through the standard > Marketing English -> Fact filter. > > -jg > > > > "Tim" <tim@rockylogic.com.nooospam.com> wrote in message > > news:avl311$p4d$1$8302bc10@news.demon.co.uk... > > > Peter Alfke wrote > > > > There is some miscommunication here: > > > > If you are happy with Virtex-II, keep buying and using it. End of story. > > > > If you like an on-chip PowerPC microprocessor for free, drastically > > > > reducing you package pin-count and board area, and/or of you want to > > > > narrow down you busses by going gigabit serial, then buy and use > > > > Virtex-IIPro. > > > > > > Does "for free" mean that V-II and V-IIPro cost the same at > > > equivalent LUT counts?Article: 51293
Austin Lesea <austin.lesea@xilinx.com> writes: > I agree that a hardware platform to implement the ppr is an exciting > concept, and it may be that with our Virtex II Pro we could actually > run the latest software under LINUX in a machine made from Virtex II > pros, with the place and route (and perhaps other stuff) accerlerated > by dedicated gates (similar to our exisiting eXtreme DSP apps). Can we infer from this that a forthcoming release of the Foundation ISE will run on Linux/PPC? :-) (No, I don't really expect that.)Article: 51294
Hi, Do you have any paper or documentation addressing this problem? Then I can cite it in my thesis. sincerely ------------- Kuan Zhou ECSE department On Thu, 9 Jan 2003, Peter Alfke wrote: > Almost all FPGA power is due to the charging and discharging of internal > capacitances. The metal lines distributingthe clock(s) all over the chip > have a substantial capacitance, and clocks have the highest frequency of any > signal on the chip. That's why clock power can be (up to?) a third of total > power, but this fraction depends very much on the design style. > > Peter Alfke, Xilinx Applications > ================================== > Kuan Zhou wrote: > > > Hi, > > I am a newbie in FPGA field.I often heard people are talking about the > > power consumption of the clock inside FPGA.What's the main issue of it? > > Will the clock line consume lots of power? > > > > Thank you very much! > > > > sincerely > > ------------- > > Kuan Zhou > > ECSE department > > >Article: 51295
Hi Austin, > Austin Lesea <austin.lesea@xilinx.com> writes: > I agree that a hardware platform to implement the ppr is an exciting > concept, Yes it is, but it's somewhat of an old concept...around even before FPGAs...for PCB routing at least. >and it may be that with our Virtex II Pro we could actually > run the latest software under LINUX in a machine made from Virtex II > pros, with the place and route (and perhaps other stuff) accerlerated > by dedicated gates (similar to our exisiting eXtreme DSP apps). The issue, from my experience, is that these algorithms require large memory...very large memory, especially for something like a VII, and this is probably not well suited to "dedicated" hardware. AustinArticle: 51296
The fix for the schematic editor problem and can be downloaded from: https://www.altera.com/support/software/download/service_packs/quartus/dnl-q ii22_017.html This link also has a description of the problem. - Subroto Datta Altera Corporation "Rene Tschaggelar" <tschaggelar@dplanet.ch> wrote in message news:3E1B4021.2090607@dplanet.ch... > I found a bug in quartus2 Web V2.2. > When tring to place legacy components in schematic editor, > such as the 74165b shiftregister, its connectors are off > grid. This makes it somewhat hard to connect. > > Did anyone figure a workaround ? > > Their support is useless : login(!), place a question, > relogin(!) to get a reply, so I didn't ask there. > > Rene > -- > Ing.Buero R.Tschaggelar - http://www.ibrtses.com > & commercial newsgroups - http://www.talkto.net >Article: 51297
Hi, I have a choice between synchronous and asynchronous global reset in the design. In older devices choosing async reset usually lowered resource utilization due to dedicated async reset input of the CLB. How is it now, with Spartan-2 and newer that have sync/async choice for the dedicated reset input? Which method is recommended? Sync method seems better (simpler timing management), but maybe there are some dark sides. Can you share some experience? Regards, DziadekArticle: 51298
>I have a choice between synchronous and asynchronous global reset in the >design. In older devices choosing async reset usually lowered resource >utilization due to dedicated async reset input of the CLB. This gets discussed here occasionally. Check google-groups. There are two major problems the global reset: It's sloooow. So it (normally) doesn't do you any good to make it synchronous. (even if you have only one main clock) It's async, so you have to consider metastability. Mostly, this means looking at what happens when state machines come out of reset. One trick is to have a local FF that is used to reset the state machine. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 51299
>It's hard to convince people theses days that an in order, single >pipeline, small cache processor is effectively free on modern >silicon. But it is. Nice. Thanks. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
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Compare FPGA features and resources
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