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Lyndon Amsdon wrote: > Hi, > > >>The only solution is buying a programmer, but it's unreasonable. >>I think is better you buy some other device that you can program with >>Byteblaster interface. > > > I've come to this conclusion too. I originally wanted to use Altera > just because they still had support for 5v logic levels on their > outputs. I'm now thinking maybe I should just use something like > Xilinx CPLDs which I believe have 5v TTL tolerant inputs and set > outputs open collector with a external pullup. I know the support for > Xilinx is huge. > BTW, Altera still have 5V logic, eg the Max7000S series. The Max3000A series runs on 3.3v, but is 5v compatible. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 51026
>
> Not all C models are free since most of them will embed license checks
> in the generated C or Asm code.
>
> > I personally wouldn't do any project without a V2C compiler. C sims
> > for most of the work, Verilog for detailed checks. Of course this is
> > really meant for simpler clock schemes that have predicable time
> > flows.
>
> Do you know any free Verilog to C tools?
>
> The optimization methods you have described are not mutually
> exclusive. They could all be applied to each node in a cluster.
>
> Petter
I believe there are a few Verilog to C compilers out there besides the
one I developed for myself. Tenison comes to mind. Maybe Icarus?
Search through the verilog open sw
My own tool V2C may get GPLed one day, in the mean time I use it for
an RTL subset of Verilog. Since I am an old schematic physical
instance devices guy, I don't support any behavioural parts of Verilog
or the always @ operator. Right now it supports hierarchy smashing,
continuos assignments and instanced FFs. Complex Verilog wire
expressions are fine. This type of Verilog is easy to schematic (if
need be) & synthesize.
So for instance a tiny state machine example would look like
module sm (CK, Clr, ins.., outs ... );
input ....; output ...; // etc
wire x,x_; // x is the FFed state, x_ will be the next x state
assign x_ = ..Clr....ins.... x ......; // whatever
assign outs = ... x .... x_ ....// whatever
EFF ux (CK,Clr, x_,x); // EFF and others CKed elements are C macros
endmodule
This sort of Verilog is usually expressed by other coders by always
inlining the FF internal code that must use always @ with the rest of
state machine code. I don't like that style since it makes all code
into FF variant code, & usually takes several times more source as
well. By using explicit FF instances, I can ignore most of the complex
Verilog semantic issues. As a Verilog user, I want to know exactly how
many flops in a design.
The Master Slave behaviour is expressed by the various FF macro calls
and the final clock macro at end of code. This is currently limited to
1 CK, although multiple CKs could be added with some work or by using
distibuted decoded ENs to gate CK.
the above is smashed and gives simple C output in same assignment
order and included into the C main
...
ulong CK,Clr,ins..,outs..,x,x_,...
x_ = ..Clr....ins.... x ......; // changing Verilog syntax to C syntax
EFF(Clr,x_,x);
...
The biggest issue is that of levelization, assignments must be in time
order of signal. Even more so, no signal can loop across hierarchy
without being FFed to preserve same cycle timing. Signals are limited
to 32 bits. Macros are used in the C output to do Verilog bit level
correct packing, so { [:],,[] {..} [:] } expressions are ok.
I will probably add levelization, arbitrary bit widths >>32, easier
inline C code, and many more features, but I will not likely add
always @ since I am not in the true Verilog compiler business.
Anyway, its free for me, it runs circles around Modelsim speed, the
code is trivial to synth in FPGA Express, great for DSPs, 1M CK cycles
runs in a few mins, typical 60 x86 ops per Verilog statement, so 16M
statements per/sec or more. Even compiles about 1MByte/sec.
end of ad
Article: 51027
On Thu, 12 Dec 2002 19:12:08 -0500, "Jeff" <dsfdsaf@hotmail.com> wrote:
>Hi,
>We want to buy a board with Xilinx FPGA Virtex-II. The algorithms we
>developed can be downloaded to the FPGA to evaluate our system. I wish the
>FPGA is bigger than XC2V3000. Also I require the board comes with 8 channel
>high speed A/D, whose maximum sampling rate should be higher than 50 MHz.
>Our application is related with software radio. I have found one even with
>DDC chips besides FPGA and ADC. Unfortunately it has only 4 channel ADC.
>Anyone know the similar products?
>
>Thanks
Have a look at:
http://www.fpga-faq.com/FPGA_Boards.htm
Philip Freidin
Fliptronics
Article: 51028Petter Gustad <newsmailcomp4@gustad.com> wrote in message news:<87adisoky8.fsf@filestore.home.gustad.com>... > johnjakson@yahoo.com (john jakson) writes: > > Automatic partition in order to minimize communication overhead is of > course difficult. The designer could of course partition the design > manually to reduce the communication overhead. An adaptive algorithm > could also be incorporated to migrate the process to a different host > to reduce the communication. Many signals could be regenerated at each > host, e.g. if each clock is generated using something like initial clk > = 0; always #10 clk = ~clk; then it could be regenerated at each host > instead of transmitting the signal over the interconnect. Okay in a dataflow model, there are a string a blocks operating on a continuous stream of data. There it may be okay to implement independent clock generators, in fact for development these blocks do have their own clock generators anyway....so we save on that overhead. And secodnly we need to sync between only two consecutive blocks as they are operating like an assembly line ... one after the other. Here, Block A simulation will talk to Block B simulation only when it really want to..i.e. Block A has data for Block B. This means that we need not keep the whole simulation synchronosed to a single global clock reference. Instead we might be better off sync'ing it on Data Valid indications that emerge on the block interfaces.. this should shave off a significant communication penalty. But we still need to make sure that this synchronisation on data valid needs to be as clean as possible. > > One big problem is that the license cost is linear, while the > performance increase is usually not. Personally I would think it would > be great if could throw 16 $3,000 PC's at the problem and get an 8x > increase in performance. However, a simulation license usually costs > 10-15 times as much as a PC. If a vendor was selling a distributed > simulator for less than linear cost this could be worthwhile. do you have figures or studies that substantiate this assertion? I plan to run a small proto run of this kind on a small simple design and try to provide figures. If they are already avaiable then it will save me this time. > > Speculative simulation could also be explored. Several nodes could > use some statistical information from previous runs an speculatively > execute cycles. If the guess was the right one it could simply pass > the result to the master node or whatever. yeah exactly, this would require us to carry timestamps on every update fo signal values that we send to other blocks. if the simulatior finds that the arriving packet carries a tiemstamp that is behind in time it discards whtever results it generated in that period and also sends new values with this previous timestamp, so toehr blocks who had depended on this fellow's wrong outputs would realise their folly and start using these fresh stimuli.. and so on and so forth till everyone is in line. But apparently this calls for a significant clarity of protocol which must be absolutely clean an crystal clear abt it's implementation... > > Does anybody know any distributed simulator vendors besides Provis > (www.provis.com)? Nothing wrong with Provis, but I'm a little > surprised that so few vendors don't have parallel simulators, > synthesis engines, static timing analyzers, and place & route tools. Well, if you go up this thread, David Casselman did point out SimCluster by avery design www.avery-design.com . You might want to see their simulators. If I am not mistaken Leospec does have a thing known as incrememntal synthesis, wherein we synthesise smaller blocks of the design withotu flattening them and stitch them all up in the end. This seems ideal and fertile for parallel concurrent synthesis, with no communication penalties as in simulations. THe EDA vendors should have jumped at parallel synthesis much before the notion of concurrent simulations took wing. I am not entirely clear about how to manage a concurrent PAR. regards, Nachiket Kapre Design Engineer Paxonet Communications Inc.Article: 51029
Hi Rudi,
I tried in:
http://www.opencores.org/projects/fpga/ -- only specs are there for
FPGA core!
{FPGA Core Specification Author: Marko Mlinar
marko.mlinar@campus.fri.uni-lj.si
Damjan Lampret damjan.lampret@yahoo.com Rev. 0.6}
http://www.asics.ws/fip_sub.html -- No soft core for FPGA model
available.
I am looking for a FPGA model/core[embedded array like Varicore!](any
LUT based architecture!), not the cores targeted to FPGAs.
Thanks,
Dasari.
russelmann@hotmail.com (Rudolf Usselmann) wrote in message news:<d44097f5.0212260243.6ab34fd9@posting.google.com>...
> dasariware@yahoo.com (dasari) wrote in message news:<e1df9052.0212251805.10648805@posting.google.com>...
> > Hai,
> >
> > I would like to know any free FGPA(lut based) cores available on net!!
> > (any architecure!) (VHDL/Verilog RTL/Netlist)
> >
> > Also,I would like to know some comparision of Varicore with any of the
> > xilinx Xc4000/vertex device in performance?
> > http://www.actel.com/varicore/index3.html
> >
> >
> >
> > Thanks,
> > Dasari.
>
> Try www.opencores.org - this is probably the largest and
> best selection of free soft IP cores around. My company
> has also a reference page of the free IP cores we have
> contributed to opencores: www.asics.ws.
> And of course the FPGA manufacturers (e.g. XILINX and
> Altera) have a large collection of examples that include
> soft IP cores.
> There are many, many more, do a search ...
>
> Cheers,
> rudi
> ------------------------------------------------
> www.asics.ws - Solutions for your ASIC needs -
> NEW ! 4 New Free IP Cores this months (so far :*)
> FREE IP Cores --> http://www.asics.ws/ <---
> ----- ALL SPAM forwarded to: UCE@FTC.GOV -----
Article: 51030Philip Freidin <philip@fliptronics.com> wrote in message news:<orin0v06al64e61ans2frp8htl88pgqvmu@4ax.com>... > On Thu, 12 Dec 2002 19:12:08 -0500, "Jeff" <dsfdsaf@hotmail.com> wrote: > >Hi, > >We want to buy a board with Xilinx FPGA Virtex-II. The algorithms we > >developed can be downloaded to the FPGA to evaluate our system. I wish the > >FPGA is bigger than XC2V3000. Also I require the board comes with 8 channel > >high speed A/D, whose maximum sampling rate should be higher than 50 MHz. > >Our application is related with software radio. I have found one even with > >DDC chips besides FPGA and ADC. Unfortunately it has only 4 channel ADC. > >Anyone know the similar products? > > > >Thanks > > Have a look at: > > > http://www.fpga-faq.com/FPGA_Boards.htm > > > > > Philip Freidin > Fliptronics Nice lists. On last project we had DINI do a custom board with 6x XC2V3000. We did the analog front end 120MHz AD-DA (ADIs) daughter board ourselves with another shop. http://www.dinigroup.com/Article: 51031
hi, would like to have some information regarding the Implementation of 8 bit Ramdac. since the RAMDAC(BT481 of Brooktree make) what we were using is obsolete. and we r not getting the pin2pin compatible or any equivalent part for that. so we r trying to implement the RAM (color/overlay palette) in FPGA and an external DAC. but the thing we r not clear abt the some of the functions in that RAMDAC. how he has implemented the control logic to mix the overlay and color palette. if any one of u knows about this please give me the solutions. regards, Ranga ReddyArticle: 51032
Hello, I am a student who wants to understand how an sram cell in an fpga works. I know it's something with five transistors, but I don't understand how it works. Can maybe someone explain this to me? thank you very much! Tom, -- Install Debian now: http://debian.linux.beArticle: 51033
I have a situation where I need to bring an oscillator into a GCK input on a Virtex, then bring it to an IOB and back in from that IOB to drive about 25% of the chip. This has to do with the fact I am using the Virtex itself as the system controller for a modest embedded PCI system. So the 33Mhz oscillator comes into the FPGA, drives a PCI target on self-same FPGA, then goes off chip to a PCI connector, another board, where a different bus master is clocking from the PCICLK and making bus master transactions back to the FPGA. So.... how does one: a) Turn off optimization so I can instantiate four or more non-inverting buffers in series to create a delay of a few NS. b) Get the software to not complain when I try to bring an oscillator into a GCK, then out an IOB and back in the same or different IOB in order to instantiate a BUFG to drive some of the logic inside the chip. Again, oh great gurus, I appreciate the exquisite nature of the pearls of wisdom floating upon the comp.arch.fpga newsgroup. CharlesArticle: 51034
The Actel website http://www.actel.com/appnotes/MXPowerUpAN.pdf talks about power-up behaviour of 42MX24's, and a problem where IO can be driven into an unknown tristate mode, and not function properly, caused by fast power-up ramp rates. Does anybody know of a similar problem with 32300's, where outputs are left tristate after configuration? Regards, Bob.Article: 51035
muthu_nano@yahoo.co.in (Muthu) wrote in message news:<28c66cd3.0212250047.7dc59bca@posting.google.com>... > Aurash Lazarut <aurash@xilinx.com> wrote in message news:<3E084E50.30D2E989@xilinx.com>... > > Muthu, > > > > DCMs are located on the top and bottom of the bram column (on the IOB > > ring) if you stay with the mouse on these resources in graphical rep. of > > the die, you can see the coordinates (the same in fpga_editor) > > Hope this helps, > > Aurash > > Hi Aurash, > > Thanks. If we use more than 8 BUFG, then manual placing of BUFG is > required. But what should be the approach. Should we LOC the DCM > first? where can i find more details? > > Thanks and regards, > Muthu Irrespective of the number of DCMs used in a design, it is always advisable to LOC the DCM and the BUFG/BUFGMUX. For more details on usage of global clocks - (assuming a Virtex2 device) - http://www.xilinx.com/publications/products/v2/handbook/ug002_ch2_gcn.pdf Hope this helps, Vikram.Article: 51036
Tom, I suppose you understand how an inverting buffer works: A pull-down n-channel transistor and a pull-up p-channel transistor with their gates connected together. Now take two such inverters and connect them in a ring, A feeding B and B feeding A. That circuit is a latch, it is stable in either of two states, either the output of A is Low and the output of B is High, or vice versa, Now you need a way to write data into the latch, and the simplest is to brute-force pull one of the inverter outputs ( called a node) either High or Low. You need to overcome the strength of the inverters in the latch. Or you use more sophisticated and elegant ways to force data into the latch. The important thing is that this latch will retain the 0 or 1, as long as there is a supply voltage. Hope this helps. Happy New Year! Peter Alfke ================================ Tom Deblauwe wrote: > Hello, > > I am a student who wants to understand how an sram cell in an fpga works. I > know it's something with five transistors, but I don't understand how it > works. Can maybe someone explain this to me? > > thank you very much! > Tom, > -- > Install Debian now: > http://debian.linux.beArticle: 51038
>a) Turn off optimization so I can instantiate four or more non-inverting >buffers in series to create a delay of a few NS. That's generally considered to be a bad design approach. The delay will vary over temperature and supply voltage and from chip-to-chip. The spec sheets won't promise any min delay. You might get a down-binned part... You will have to fight the tools. I couldn't figure out why you wanted the delay. Can you use some other approach? How about a length of PCB trace? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 51039
Altera FlexEPF10K100ABC356-2 PCI CARD do you know if that will work with the student software?Article: 51040
"Steve Casselman" <sc@vcc.com> wrote in message news:<5M0O9.1472$W34.116600010@newssvr21.news.prodigy.com>... > I'm sure I could design > a system that could sell for about $5K that would speed up Par by 10x-20x > but I don't think Xilinx would go for it. It would be about a $2 Million > project most of it man power. > > The offer is on the table!!! Hey Steve, how about using JBits? I'm surprised no one's mentioned it in this thread. Part of the reason Xilinx makes JBits available is so you can implement your own place & route tools. (JBits SDK is a Java toolset and API to the Virtex bitstream Xilinx makes available to researchers. http://www.xilinx.com/products/jbits/) Show 10x speedup over 5.1i par on real designs and you'll get lots of interest! --Mike (Please post replies, I don't read email to this spam-sink address.)Article: 51041
Hello, I'm thinking of letting my Data I/O coast on without further software updates, and put the money into a new BP programmer. I'm frustrated by the lack of pricing information on the BP website, or any distributors' sites. Would anyone who recently bought a BP-1200 care to post some prices for the 1200, any of the extra modules, any upgrades, and the software upgrade to generate serial numbers. Also, is it possible to write your own little program to generate serial numbers, and have the free BP software call it, or do you still have to pay for an "advanced features" package? It would be great if some kind soul posted some info here; alternatively, I'd be grateful for a scanned pricelist by email. I've contacted the local rep, but since there's no reply, I assume he's on vacation. Thanks for any info, David. -- dave - dfnr2@yahoo.comArticle: 51044
I have ISE 5.1i running under windows 2000. I am getting the following warnings I'd like to suppress (during synthesize / synthesis) from the syntesis report. WARNING:HDLCompilers:38 - infc_constants.v line 142 Macro 'W_ERR_CS_ADDR' redefined These redefinitions are intended and I do not to to see the warnings, they clutter up the console output. Any ideas how I might suppress these warnings? I checked xilinx support website, no joy. thanks p.s. i have searched http://www.xilinx.com/support/searchtd.htm answers database answers archive application notes technical tips xilinx software version 5.1i application version i+F+34450 keywords: supress warningsArticle: 51045
Dave wrote: > I'm thinking of letting my Data I/O coast on without further software > updates, and put the money into a new BP programmer. I'm frustrated > by the lack of pricing information on the BP website, or any > distributors' sites. Would anyone who recently bought a BP-1200 care > to post some prices for the 1200, any of the extra modules, any > upgrades, and the software upgrade to generate serial numbers. Last time I checked, BP prices were a little breathtaking. Probably why = they're not posted <g>. You might also want to look at Needhams = Electronics: http://www.needhams.com -- Bill Posted with XanaNews Version 1.12.5.6Article: 51046
Correction I said XCT but meant XST View Synthesis Report. snippets: Release 5.1i - xst F.23 Target Device : xcv2000e-6bg560 verilog2001 : YESArticle: 51047
You need to talk to Altera about whether or not their student
version software supports FLEX10K100A.
Now it sounds to me the FLEX10KA is directly attached to the PCI bus,
and if that's the case, I think you are in for a lot of trouble.
First thing you should do is to download Opencores.org PCI IP core
(http://www.opencores.org/projects/pci/), try to figure out how to
target FLEX10KA, and understand how its backend interface works.
If Opencores.org PCI IP core doesn't work, the only choice will likely
be to develop your own PCI IP core since commercial PCI IP cores cost
many thousands of dollars.
Here is some information on how I developed my own PCI IP core which you
may find it helpful.
http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&newwindow=1&selm=at6ekl%24k4n%241%40newsreader.mailgate.org
Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)
Matthew Campbell wrote:
>
> Altera FlexEPF10K100ABC356-2 PCI CARD do you know if that will work
> with the student software?
Article: 51048Hi, Previously (with F3.1) when VCC is used for the SRLs address, it was sourced from the slice without consuming logic. Now with the F4.2 i see that a LUT is used to source VCC and GND as well. is there any setting to add to avoid this problem? also in the logic used report, those LUT are not taken into account!
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