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Lana wrote: > > I would like to design a module which will enable me to input 12-bit > samples and output 16-bit samples. One implementation that I've > though of entails the design of shift register using 6 8-bit > registers. However, this would entail that 4 cycles to load the > registers and 3 cycles to output the contents along with a bit of > logic to switch between the two modes. Is there a more efficient > manner of doing this that will result in better bandwidth and resouce > usuage? This sounds more like a FIFO, or Dual Port memory description than a shift register. Your cycle counts suggest you want to compress 4 x 12 bit samples, into 3 x 16 bit packets for storage or transmission ? A 48 bit Dual port memory allows the greatest read/write clock freedoms, but if you have a common clock domain, and want to maximise the data-rate, then you do not need to wait for 4 loads before doing 3 sends - they can be interleaved. The average output clock is 3/4 of the IP clock, and you need a latency of 2 readings to have enough info to load into the first packet 1 + 1/3 readings, thereafter, 3 output clocks [x16 wide] are generated for every 4 ip clocks [x12 wide] A first guess at this, gives 12 bits for the Queue, and 16 bits for the OP register, plus 2bits for a state-engine to control the QueueMux. - jgArticle: 51101
Would anyone who recently bought a BP-1200 care > to post some prices for the 1200, any of the extra modules, any > upgrades, and the software upgrade to generate serial numbers. > > Also, is it possible to write your own little program to generate > serial numbers, and have the free BP software call it, or do you still > have to pay for an "advanced features" package? > > > David. Hi, I tend to agree with Mathew, isp is the way forward, especialy now that everything seems to come in ever smaller surface mount chips.Generating a serial number isn't very difficult, but it is a pain to have to keep downloading a different file each time, a small batch file can do it though.Alternatively I made a programmer some years ago that did this, If you had a need I could probably adapt it for you.Article: 51102
In article <7B373EDCA1DF1741917BCFC2E20A52DA08BF1F0A@pfx21.stu.nus.edu.sg>, Liao Jirong <iscp1097@nus.edu.sg> wrote: >To understand how the mapping affects the delay, I try to look into the >.xdl output, which is converted from .ncd output from Xilinx tools. Is >there any document on this? There isn't any that I know of. However, .xdl is very human readable and effectively self documenting. However, I don't think you can really get a delay feel from it, as routing has a significant effect and you can only do a gross ad-hoc estimate of delays based on logic levels and manhattan distance. >Btw: anybody know how to count the delay from the Xilinx mapping output? > >Thanks. > > -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 51103
"Rob Finch" <robfinch@sympatico.ca> wrote in message news:<RTWM9.6274$iQ3.1481370@news20.bellglobal.com>... > Just thinking out loud... This is really a bit off topic (but somewhat > similar) but, > > I've been thinking about trying to build a simple neural network accelerator > (mostly as an academic exercise). Each neuron needs to take input from > multiple sources and accumulate the results, ideally within a single clock > cycle. > > The problem with using bram for this is that it doesn't allow enough > simultaneous read ports. So much time would be spent reloading the bram or > switching outputs for different neurons that it would mostly negate any > advantage of building the thing in hardware. So, I've been thinking about > using registers and distributed ram to build a serially loaded synaptic > weights matrix(s). As long as the network can be built entirely within the > FPGA and weights matrix doesn't need to be reloaded, I think the whole thing > could be made to work very fast. > > Of course I'm thinking of trying something really simple to begin with like > recognizing characters from an 8x8 pixel image input. I'd be relying on a > pre-trained network. > > Rob Well this seems very interesting. My design also involves reading in multiple pixels of an image at the same time and feeding them to an array of parallel processors. These processors will write their outputs to memory. The problem is that the output from the processors has to be added to the value that is already in the memory at an address generated by the processors, and more than one proceesor can generate the same memory address. alisonArticle: 51104
Hi Peter, Just so you know, the published (Xilinx) documentation recommends otherwise. I forget where I saw it; it was either in an App Note, or in an ISE output file (PAR? MAP?), but it said to tie the unused pins to ground with a 10K resistor. $.02, SH On Tue, 31 Dec 2002 10:48:10 -0800, Peter Alfke <peter@xilinx.com> wrote: >If they are unused, just leave them unconnected.Article: 51105
Nothing wrong with that recommendation, but overly cautious, in my optinion. The resistor (instead of a short) protects against accidental misconfiguration, the resistor ( instead of open, with internal pull-up or -down) protects against crosstalk, which would not do any harm anyhow since the input signal is not used. My suggestion is more constructive, since it achieves lower ground bounce. There are many ways to "skin a cat" Happy New Year Peter Alfke ============ Spam Hater wrote: > Hi Peter, > > Just so you know, the published (Xilinx) documentation recommends > otherwise. > > I forget where I saw it; it was either in an App Note, or in an ISE > output file (PAR? MAP?), but it said to tie the unused pins to ground > with a 10K resistor. > > $.02, > SH > > On Tue, 31 Dec 2002 10:48:10 -0800, Peter Alfke <peter@xilinx.com> > wrote: > > >If they are unused, just leave them unconnected.Article: 51106
Hi, I am now learning ISE webpack 4.2. The following sentences in .do file can simulate internal variables. view wave add wave * add wave /testbench/uut/dir add wave /testbench/uut/count add wave /testbench/uut/ce The HDL bencher is a useful tool to make test waveforms. But I cannot find the method to do the above in HDL bencher. Can you tell me? ThanksArticle: 51107
>However, I don't think you can really get a delay feel from it, as >routing has a significant effect and you can only do a gross ad-hoc >estimate of delays based on logic levels and manhattan distance. Estimate of delay is fine. How to do that? Could you specify more details?Article: 51108
Adam Elbirt <aelbirt@nac.net> wrote in message news:<3E109B65.3050702@nac.net>... > Anyone know of an application note or on-line documentation where Xilinx > specifies how they calculate their estimated gate counts for Virtex (or > other families) implementations? > > Adam Adam, The gate count method of calculating the device densities in FPGAs is always deceptive. Both Xilinx and Altera used this method to mention the gate density all this time and confused the customers. Worse, Xilinx uses a different method to mention the gate density(typically the System Gates method) and Altera (logic gates method). e.g. A Xilinx 200K device (XC2S200) is smaller than Altera's 100K device(EP1K100) !!!!!! This method is even more complicated now with FPGAs getting more and more complex with memory, etc built-in. So, now they have started the LE/LC method which is typically one LUT, one FF and one CY bit. I know I have not answered your question, but this might provide some insight. ThanksArticle: 51110
Peter Alfke <peter@xilinx.com> wrote: > That way you have additional ground connections from the inside to the > ground plane, and although the resistive part may be not perfect, all > the lead inductances are in parallel, and thus reduce the inductive > kick. Thank you for your help and also "es guets Neu's", as we say in Switzerland ;-) > Happy New Year und ein Gutes Neues Jahr, hoffentlich besser als 2002. > Peter Alfke, Xilinx Applications > ============================= > Andreas Schweizer wrote: >> Hi everyone, >> >> in the design I'm working at, we're using a Virtex-II >> FPGA in the FG 676 package. Many of the I/O pins are >> however unused. Is it a good idea to connect these >> to GND? or leave them unconnected or connect some to >> GND and some to Vcco? >> >> Thank you for reading and a happy 2003 to all! >> AndyArticle: 51111
Hi Bob I'm not sure if the problem we had with a 14100 some time ago (2+ years) is the same. After power up all I/O were tristate. Connected up Silicon explorer to try and find the problem and all started to function normally. Eventual diagnosis from Actel was that probably the very last fuse was not correctly programmed. It was some time ago and I don't remember the exact details. I think the fuse has something to do with enabling the I/O after power up. For some reason success or failure of programming this fuse does not show up in the programming log. I recollect that this was a known problem in another family (I don't remember which one) but unusual for the ACT3. HTH Kate "bob" <bob@sanboli.freeserve.co.uk> wrote in message news:auhtp5$lsp$1@news6.svr.pol.co.uk... > The Actel website http://www.actel.com/appnotes/MXPowerUpAN.pdf talks about > power-up behaviour of 42MX24's, and a problem where IO can be driven into an > unknown tristate mode, and not function properly, caused by fast power-up > ramp rates. > Does anybody know of a similar problem with 32300's, where outputs are left > tristate after configuration? > > > > Regards, > Bob. > >Article: 51112
hi, This was useful. Thanks, Valli. vhdlcohen@aol.com (ben cohen) wrote in message news:<21cb1efc.0212311208.30049590@posting.google.com>... > allan_herriman.hates.spam@agilent.com (Allan Herriman) wrote in message news:<3e1066be.16045482@netnews.agilent.com>... > .... > > "Bus gates" (if I understand your terminology) are devices that can > > act like bidirectional switches or transmission gates and are used to > > connect two tri-state signals together. > > These can be modeled directly using a Verilog gate primitive. > > VHDL is a little harder, but it can be done. Ben Cohen's zero ohm > > resistor model shows how. I found a copy of the model in the file > > "synplify.vhd" in an installation of Synplify. > > > > Regards, > > Allan. > > The gate switch model is also at my site > http://www.vhdlcohen.com/ > > BenArticle: 51113
Hi Tony, > http://ce.et.tudelft.nl/~reinoud/mpga/README.html The source files helped me to some level. Thanks and Regards, Dasari. "Tony Burch" <tony@burched.com.au> wrote in message news:<3e0ff62d$0$27996$afc38c87@news.optusnet.com.au>... > Hi Dasari, > > The MPGA project may be of interest: > http://ce.et.tudelft.nl/~reinoud/mpga/README.html > > Best regards > Tony Burch > http://www.BurchED.biz > FPGA boards for System-On-Chip prototyping and education > > "dasari" <dasariware@yahoo.com> wrote in message > news:e1df9052.0212251805.10648805@posting.google.com... > > Hai, > > > > I would like to know any free FGPA(lut based) cores available on net!! > > (any architecure!) (VHDL/Verilog RTL/Netlist) > > > > Also,I would like to know some comparision of Varicore with any of the > > xilinx Xc4000/vertex device in performance? > > http://www.actel.com/varicore/index3.html > > > > > > > > Thanks, > > Dasari.Article: 51114
http://www.xilinx.com/products/virtex/asic/performance.htm "High logic capacity, up to 10 million system gates (3 to 4 million equiv. std cell gates) ·" http://www.eedesign.com/columns/eda/OEG20021125S0047 -- November 25, 2002 "Regardless of their tagged specifications that may call for supporting 400,000 design gates, or 800,000 equivalent ASIC gates, or 4,000,000 FPGA gates, or 12,000,000 system gates, two systems, each based on two Virtex-II XC2V-6000 FPGAs, will have the same design capacity. For example, the ZeBu ZV-6000, the universal verification platform introduced at the Design Automation Conference 2002 by EVE, maps designs into two XC2V-6000 FF1517 FPGAs plus 128Mbits of SRAM chips and sells for $49,000 inclusive. " http://www.amis.com/conversion/adv/adv5.cfm There's No Use Comparing System Gates with ASIC Gates "System Gate Semantics While no one seems to be quite sure what a system gate is, it has become the metric for this new breed of FPGA devices. As near as we can tell, two system gates are equivalent to one ASIC gate and four system gates are about equal to one ASIC dual-port RAM bit. What this means is a fully utilized million-gate FPGA can normally be cost-reduced into an ASIC with less than 180K ASIC gates of logic and less than 290K ASIC gates of RAM. This adds up to about 470K ASIC gates — less than half the number of system gates. Truth is, it's difficult to fully utilize the FPGA and the resulting ASIC gate count is often much lower than expected. Furthermore, if your design just needs gates and no RAM, the million-gate FPGA will support less than 180K ASIC gates. " http://www.amis.com/conversion/xpressarray/ A graph shows Price versus Volume(no. of gates). Hope this helps. Dasari. fpga_wonderkid@yahoo.com (FPGA Wonderkid) wrote in message news:<23069c63.0301012324.689bcc41@posting.google.com>... > Adam Elbirt <aelbirt@nac.net> wrote in message news:<3E109B65.3050702@nac.net>... > > Anyone know of an application note or on-line documentation where Xilinx > > specifies how they calculate their estimated gate counts for Virtex (or > > other families) implementations? > > > > Adam > > Adam, > The gate count method of calculating the device densities in FPGAs is > always deceptive. Both Xilinx and Altera used this method to mention > the gate density all this time and confused the customers. Worse, > Xilinx uses a different method to mention the gate density(typically > the System Gates method) and Altera (logic gates method). e.g. A > Xilinx 200K device (XC2S200) is smaller than Altera's 100K > device(EP1K100) !!!!!! This method is even more complicated now with > FPGAs getting more and more complex with memory, etc built-in. > So, now they have started the LE/LC method which is typically one LUT, > one FF and one CY bit. > > I know I have not answered your question, but this might provide some > insight. > > ThanksArticle: 51115
Also check the papers on Cooley's DeepChip site. The broad conclusion seems to be that FPGA gate counts and ASIC gate counts converge as things gets bigger. YMMV.Article: 51116
Allan Herriman wrote: > On 29 Dec 2002 23:50:59 -0800, sri_valli_design@hotmail.com (Valli) > wrote: > > >Hai all, > > > >Can someone pass some functional info., and vhdl/verilog model for bus > >keeper, and bus gate logic! > > A bus keeper is a device that maintains the last level driven on a > tri-state bus. > It has one connection (not including power supply) that acts as both > an input and an output. If the signal is high, then it drives a weak > high out. If the signal is low, then it drives a weak low out. > No necessarily so weak either. There are some devices with bus keepers I've come across (LVCH ?) that need 500uA to overdrive the keeper.Article: 51117
Hi, Happy New Year to all. I understand the series termination on the control and address line, those are not bidirectional, my question is about the data lines? How do you terminate a bidirectional line with series resistors,? To put some numbers on it assume 50 Ohm trace impedance a Xilinx Virtex2 on one end and a DRAM on the other, and assume the trace is long enough to require termination. Thanks, jakab Eric Pearson <ecp@mgl.ca> wrote in message news:En0Q9.96317$E_.74803@news02.bloor.is.net.cable.rogers.com... > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3E1057E4.77E3799C@yahoo.com... > > Rob Finch wrote: > > > > > > Hi, > > > > > > Just wondering if anyone has interfaced ordinary DRAM (72 pin simms) to > an > > > FPGA and are series damping resistors required ? > > > > I have not used standard DRAM with an FPGA, only SDRAM. But the > > electrical issues are the same. The series damping resistors are used > > for impedance matching to minimize reflections. If your traces are only > > 3 inches or so you won't need to worry with this. If your traces are 6 > > inches or more you definitely need to consider the issue. In between it > > depends on the details of your driver speed. So try to keep all your > > traces as short as possible. The RAS and CAS lines are of special > > concern since reflections can cause double clocking of the DRAM. > > I have sucessfully used 72 pin DRAM simm's with a number of FPGA designs. > Trick is too meet all the dram timing specs, and keep the > high fanout ras / cas edges fast and monotonic (as stated above) > > Controlled impedance drive is usually required. individual series damped > drivers > for each address and control pin is usually sufficient for a single SIMM. > > A pll multiplied clock or other methods can be used to carefully place > ras and cas edges, while keeping address and data synchonous > at the fpga boundary edge. > > Sdram's are much nicer. > > Regards... > > Eric Pearson > >Article: 51118
Hi Jakab, also a happy new year to you! > a Xilinx Virtex2 on one end and a DRAM on the other, These have built-in "resistors". You can configure the IO's as DCI (digitally controlled impedance) and provide two reference resistors per IO bank (VRN, VRP). If you instantiate the correct IO buffers in your code, probably LVDCI or LVDCI_DV2 (the former with 50 Ohm reference resistors, the latter with 100 Ohm), the virtex-ii automatically matches the impedance. HTH, AndyArticle: 51119
In article <7B373EDCA1DF1741917BCFC2E20A52DA08BF1F0B@pfx21.stu.nus.edu.sg>, Liao Jirong <iscp1097@nus.edu.sg> wrote: > >>However, I don't think you can really get a delay feel from it, as >>routing has a significant effect and you can only do a gross ad-hoc >>estimate of delays based on logic levels and manhattan distance. > >Estimate of delay is fine. How to do that? Could you specify more >details? Unfortunatly, Xilinx doesn't publish the delay details you want, so you just have to come up with a crude measure based on manhattan distance. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 51120
Hi Andy, This solves one half of my problem; if virtex2 drives the bidirectional line then DCI will probably work, what about the DRAM driving the same line (not the same time, of course). There is no built in series resistor in the DRAM !? --- jakab Andreas Schweizer <aschweiz@iiic.ethz.ch> wrote in message news:3e1458fc@core.inf.ethz.ch... > Hi Jakab, > > also a happy new year to you! > > > a Xilinx Virtex2 on one end and a DRAM on the other, > > These have built-in "resistors". You can configure the IO's as > DCI (digitally controlled impedance) and provide two reference > resistors per IO bank (VRN, VRP). > If you instantiate the correct IO buffers in your code, > probably LVDCI or LVDCI_DV2 (the former with 50 Ohm reference > resistors, the latter with 100 Ohm), the virtex-ii automatically > matches the impedance. > > HTH, > Andy > >Article: 51121
Hi, <BR> I want to connect two of my designs in quartus. There is a bus in one design. I want to take only one bit of that bus and connect it to other component(design). Is there any bus splitter in quartus? <BR> I can not change the internals of the design. So Internally I can not take that one bit and assign it to one port. <BR> Any comments how this can be achieved? <BR> Sudip Saha <BR> sudip.saha@Philips.comArticle: 51122
Hi all,
I read an article recently which mentioned that an inference of a
latch due to an incomplete IF statement is an asynchronous piece of
code. I agree with that. But if I had this piece of code within a
process which triggers @ the rising edge of a clk, would it still be
considered async ? I would think not.
for e.g.
----------------------------------------------------
Code A
process(A)
begin
if (A = 1) then
B <= C;
end if;
end process;
----------------------------------------------------
----------------------------------------------------
Code B
process(clk)
begin
if clk'EVENT and clk = '1' then
if (A = 1) then
B <= C;
end if;
end if;
end process;
----------------------------------------------------
I would assume Code B to be synchronous, while code A is async. Am I
correct ?
Thanks,
Prashant
Article: 51123If you need termination on the bi-directional data lines, then parallel or AC termination can be used. The data lines can often be left un-terminated if you have the timing margin for a settling period, or you keep the nets short. Eric Pearson "jakab tanko" <jtanko@ics-ltd.com> wrote in message news:av1uul$1nt$1@news.storm.ca... > Hi Andy, > > This solves one half of my problem; if virtex2 drives the > bidirectional line then DCI will probably work, what about the DRAM > driving the same line (not the same time, of course). There is no > built in series resistor in the DRAM !? > --- > jakab > Andreas Schweizer <aschweiz@iiic.ethz.ch> wrote in message > news:3e1458fc@core.inf.ethz.ch... > > Hi Jakab, > > > > also a happy new year to you! > > > > > a Xilinx Virtex2 on one end and a DRAM on the other, > > > > These have built-in "resistors". You can configure the IO's as > > DCI (digitally controlled impedance) and provide two reference > > resistors per IO bank (VRN, VRP). > > If you instantiate the correct IO buffers in your code, > > probably LVDCI or LVDCI_DV2 (the former with 50 Ohm reference > > resistors, the latter with 100 Ohm), the virtex-ii automatically > > matches the impedance. > > > > HTH, > > Andy > > > > > >Article: 51124
Jeff, Please add user options to the .UDO file that HDL bencher wrote out. Regards, Wei Jeff wrote: > Hi, > I am now learning ISE webpack 4.2. The following sentences in .do file can > simulate internal variables. > > view wave > add wave * > add wave /testbench/uut/dir > add wave /testbench/uut/count > add wave /testbench/uut/ce > > The HDL bencher is a useful tool to make test waveforms. But I cannot find > the method to do the above in HDL bencher. > Can you tell me? > > Thanks
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Compare FPGA features and resources
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