Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi, anybody out here has some insight, why the 8 bit picoblaze (up 112 MHz) is clocked lower than the 32 bit microblaze (up 150 MHz) ? cheersArticle: 48251
Thanks. >I found a flowchart on page 2-4 of > >http://support.xilinx.com/support/sw_manuals/3_1i/download/dev_ref.zip > >This together with a description of all the different programs was >fairly easy to incorporate into script to run partgen, ngdbuild, map, >par, trce, bitgen, promgen, ngdanno, and ngd2ver. Is the Floorplanner in there? I didn't see it but I might have missed it. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 48252
>You mentioned metastability, and that caught my attention. >Metastability is a reality, but it (and the fear of it) is highly overrated. ... >Metastability is a real, but highly overrated problem. When is Xilinx going to put numbers into the data sheets? Worst case? I wouldn't say "overrated". It might be less of a problem now than it was a while ago. But users demands/expectations are going up too. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 48253
>Ok there are 10 of us in the world who want to have Open source tools of >some sort. My problem is I want to make a living off of the tools I write. >How do I do this. ... Have you read Eric Raymond's The Cathedral and the Bazaar? It's the best view into Open Source I've seen. Possible ways to make money via Open Source: I think they all start with writing some code that lots of people think is useful. Then you might get vendors to pay you to adapt/maintain it for their chips/tools. Or get users to pay you to enhance/maintain it to do something they need. Become famous (or at least well known) so people will hire you to consult (or lecture). It seems unlikely to me that a small handful of people will be able to write a full set of tools, even if the vendors would cooperate. Just too much work/time. And the target isn't standing still. I keep looking for something around the edge, some tool/utility that isn't critical enough that the vendors need it but it useful enough so that some users would jump on it. No great ideas yet. Something along the lines of a Floorplanner might be right. Or some hack/tool to give hints/directions to the normal placer. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 48254
Have a look at Actel ProAsic family. Dziadek "Matthias Dyer" <dyer@tik.ee.ethz.ch> wrote in message news:3daad887@pfaff.ethz.ch... > In our lab we'd like to add an reconfigurable module to a mobile > Bluetooth-Node (BT & uC). Issues as low-power, flexibility and performance > are important for us. > > I first thought about a CoolRunner II implementation but I think we are too > limited with CPLDs. We also want to enable partial and dynamic > reconfiguration where I believe that the Virtex family is leading. > > Has anyone used Virtex FPGAs in an low power embedded design? > What system-level power saving possibilities do I have (not in the FPGA > design)? > > Or do you have other suggestions for other components? > > Thanks for any help > > Matthias Dyer > > > -- > ------------------------------------------------------------- > Matthias Dyer phone: +41-1-6327061 > Gloriastr. 35, ETZ G-63, fax: +41-1-6321035 > CH-8092 Zurich, Switzerland email: dyer@tik.ee.ethz.ch > > Computer Engineering and Networks Lab (TIK) > Swiss Federal Institute of Technology (ETH) Zuerich > -------------------------------------------------------------Article: 48255
"Stan" <vze3qgji@verizon.net> wrote: >Did you connect all 32 devices to the same clock? -Stan Yes, no reason why not if the signal edges are well controlled. Peter. -- Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 48256
Ray Andraka <ray@andraka.com> wrote: > That is, provided XDL runs on your design. It gets into an infinite loop with > one of my larger designs, apparently because of the size of the ncd file (never > writes an end process in 2GB of output, then stops generating output when the > file reaches 2GB in length but keeps running internally). Could be a filesystem limitation (can't handle > 2Gb files). Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 48257
Somebody know how to generate LUT for DA FIR with Altera? Another question is if I use LPM multiplier using EAB, it this a DA multiplier? If not, what's the difference from DA multiplier? thanks for your helpArticle: 48258
Hi all,
is it possible (and how) to use GCK2/3 pins as
normal IO pins ?
If i use it into my source i receive an error:
ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB
component:
PAD symbol "pingck2" (Pad Signal = pingck2)
BUF symbol "pingck2_IBUF" (Output Signal = pingck2_IBUF)
Each of the following constraints specifies an illegal physical site for a
component of type IOB:
Symbol "pingck2" (LOC=P182)
Please correct the constraints accordingly.
Problem encountered during the packing phase.
PS: Xilinx Spartan/Virtex
Thanks
--
Stefano Mora
email: stefano.mora@*libero.it
(remove *)
Article: 48259Apparently, Xilinx has stopped making the Parallel Cable III. I've designed a DIY version of it using a single-sided PCB (with a few wire links) capable of being made at home. All components are through-hole, and it is just under 3" square. If anyone is interested in making one, please contact me. I can email the artwork (.PRN file for a LaserJet printer. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 48260
On Tue, 15 Oct 2002 13:58:17 GMT, "Stefano M" <stefano.mora@antispam.libero.it> wrote: >Hi all, >is it possible (and how) to use GCK2/3 pins as >normal IO pins ? >If i use it into my source i receive an error: > >ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB > component: > PAD symbol "pingck2" (Pad Signal = pingck2) > BUF symbol "pingck2_IBUF" (Output Signal = pingck2_IBUF) > Each of the following constraints specifies an illegal physical site for a > component of type IOB: > Symbol "pingck2" (LOC=P182) > Please correct the constraints accordingly. >Problem encountered during the packing phase. > >PS: Xilinx Spartan/Virtex For this particular xilinx family, you *can* use the GCK pins as general purpose inputs, with the following restrictions: - There is no input flip flop - You can't use it as an output - You must use an IBUFG rather than an IBUF This was fixed in Virtex2, BTW. Regards, Allan.Article: 48261
The DA LUT contains all the possible sums of the 1xN products. See
the tutorial on distributed arithmetic on my website.
No, the LPM multiplier is not a DA multiplier. DA reduces the logic
for a sum of products. It works by rearranging the partial sums
then using a scaling accumulator to do all the multiplies. In the
extreme case where there is only one product term, DA is reduced to
a scaling accumulator. If that is done in a full parallel
implementation, then you arrive at a regular multiplier. I refer
you to both the multiplier and distributed arithmetic tutorials on
my website.
Dongho wrote:
> Somebody know how to generate LUT for DA FIR with Altera?
> Another question is if I use LPM multiplier using EAB, it this a
> DA multiplier? If not, what's the difference from DA multiplier?
>
> thanks for your help
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48262Good Morning. I have a need to modify an FPGA design that was created in Altera HDL. Though it is similar to VHDL and Verilog, I would like to get my hands on a command reference or users' manual. Does anyone know where I could get a copy? You would think Altera would be the obvious answer, but they have not been much help... Thanks. JoshArticle: 48263
It looks like there is a 2GB limit, but that is not the only problem. We don't see a
single endmodule in that 2GB of output. Even with the workaround we got for the 2GB
limit, we never reached an endmodule in 250 million lines of output. That's why we
thought it is something more than just a file limit (we also tried turning off the
pips to reduce the output file size with the same result).
hamish@cloud.net.au wrote:
> Ray Andraka <ray@andraka.com> wrote:
> > That is, provided XDL runs on your design. It gets into an infinite loop with
> > one of my larger designs, apparently because of the size of the ncd file (never
> > writes an end process in 2GB of output, then stops generating output when the
> > file reaches 2GB in length but keeps running internally).
>
> Could be a filesystem limitation (can't handle > 2Gb files).
>
> Hamish
> --
> Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48264
Hal, didn't you know that floorplanning isn't considered a normal design flow,
only the 5% designs from hell need it ;-)
Hal Murray wrote:
> Thanks.
>
> >I found a flowchart on page 2-4 of
> >
> >http://support.xilinx.com/support/sw_manuals/3_1i/download/dev_ref.zip
> >
> >This together with a description of all the different programs was
> >fairly easy to incorporate into script to run partgen, ngdbuild, map,
> >par, trce, bitgen, promgen, ngdanno, and ngd2ver.
>
> Is the Floorplanner in there? I didn't see it but I might
> have missed it.
>
> --
> The suespammers.org mail server is located in California. So are all my
> other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
> commercial e-mail to my suespammers.org address or any of my other addresses.
> These are my opinions, not necessarily my employer's. I hate spam.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48265"Rene Tschaggelar" <tschaggelar@dplanet.ch> wrote in message news:3DA7DA7C.9000509@dplanet.ch... > I found surprisingly little material about programming the FPGA > myself. The (Altera-) tools pproduce *.pof & *.sof files and > usually send them through the attached programmer. > I wasn't able to find a reference about their format or how they > are going to be sent to the FPGA or its config-chip. > Only the JTAG interface was described. > > Any hints ? Altera has an app. note describing the process. I used the info to configure an Altera device via a couple of output bits on an ADI DSP. It worked very well, when I'd sorted out several problems with the DSP development software. I also had to write some software to convert the Altera file into something the ADI tools could handle. Can't remember the details, though. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 48266
Thanks very much for the reply! adrian > You can do separate installs for 3.3 and 4.2 on the same machine. In order to > switch back and forth between them, you need to modify the XILINX environment > variable to point to the tools directory you are currently using. Other than > that, there is nothing special that needs to be done. IIRC, there was a new > xilinx registration number to enter when first installing 4.x, but that is a > one-time thing. > > I have both 3.3 and 4.2 installed on the same drive, different sub-directories > on my NT machine. To switch, I change just the directory name in the XILINX > environment variable, then I'm good to go. Can't use both at the same time > unless you are strictly command line, in which case you can use the set command > to do the enviroment locally. > > Noddy wrote: > > > Hi, > > > > I am presently designing for a Spartan II using Foundation 3.3 software. We > > have upgrades (still in their boxes) to Foundation 4.2 aswell as ISE 4.2. We > > need to upgrade the software sometime as I am going to be redesigning and > > modifying for a Spartan IIE. > > > > My question is the following: I was under the impression the ISE was really > > only useful if I was going to design for Virtex. Under this understanding, > > will probably want to install the software for Foundation 4.2. However, I > > still want to use Foundation 3.3 as I am still working on the design, and am > > worried about the design having problems in 4.2. So what I want to do is put > > Foundation 4.2 onto a separate hard drive, and plug into the same system. > > Will I have any registry issues? Is it possible to run two versions of the > > Xilinx Foundation software on the same machine? Do have to do the entire > > Xilinx licensing thing again when I install 4.2? Finally, should I rather be > > install ISE instead? > > > > Thanks > > > > Adrian > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 48267
> By registering the reset
> signals in the local clock domains, the reset will be applied to all
> elements within that clock domain in one clock cycle and be subject to
> the timing constraints for the clock period constraint.
John,
Does this apply if you synchronise your reset net at the top level and then
use it throughout your design with 'standard' asynch reset declarations....
process(clk,rst)
begin
if(rst = '1') then
signal <= reset_val;
elsif(rising_edge(clk)) then
..and so on, or do you have to use
process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
signal <= reset_val;
elsif.......
?
Nial.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- To email remove spamno from address.
Article: 48268Hello, Does anybody know how to (safely) drive Virtex2 inputs with 5V TTL levels? Thanks, jakabArticle: 48269
"Allan Herriman" <allan_herriman.hates.spam@agilent.com> schrieb im Newsbeitrag news:3dac2268.10441073@netnews.agilent.com... > For this particular xilinx family, you *can* use the GCK pins as > general purpose inputs, with the following restrictions: > > - There is no input flip flop > - You can't use it as an output > - You must use an IBUFG rather than an IBUF And how?? To do so using Webpack (which uses XST for VHDL synthesis), you must add a attribute to the signal attribute clock_buffer: string; attribute clock_buffer of my_input_signal: signal is "ibufg"; -- MfG FalkArticle: 48270
"emanuel stiebler" <emu@ecubics.com> schrieb im Newsbeitrag news:3DABA42C.8321741C@ecubics.com... > Hi, > > anybody out here has some insight, why the 8 bit picoblaze (up 112 MHz) 112 MHz (one hundred twelf megahertz???) In what device? the fastest Virtex-II?? My expirience is somewhere 50 MHz in a -5/-6 Spartan-II(E). > is clocked lower than the 32 bit microblaze (up 150 MHz) ? Looks like the microblaze is more pipelied than the picoblaze (which has some pipelining too). Picoblaze (Hello Ken ;-) was developed for minimum size on top priority, speed was second (AFAIK) -- MfG FalkArticle: 48271
Allan, thanks for your attention. > >PS: Xilinx Spartan/Virtex > > For this particular xilinx family, you *can* use the GCK pins as > general purpose inputs, with the following restrictions: > > - There is no input flip flop > - You can't use it as an output > - You must use an IBUFG rather than an IBUF OK, thanks > > This was fixed in Virtex2, BTW. What do you mean with 'fixed' ? Is this a trick only for Spartan & Virtex ? It is not usable for Virtex2 and following ? Thanks again -- Stefano Mora email: stefano.mora@*libero.it (remove *)Article: 48272
If the tools do the proper timing analysis for reset inactive to clock setup time, then yes - a registered reset at the top of the hierarchy can be distributed throughout the design as a standard asynchronous reset. The reset signal is synchronous. The reset is applied through an asynchronous mechanism. The reset event is still synchronous. There's a switch in the Xilinx timing analysis - reg_sr_q - which will include the paths for reset-to-clk for both the active and inactive transitions. Without the switch checked (default is off) neither of these paths are included. The activation of reset (timing parameters such as Trq mid-path) isn't so much of an issue for me because I don't have events that would get confused by a reset flop that doesn't propagate to its destination before the next clock since - gosh - the destination's getting reset, too. I would only include the paths through appropriate timing constraints to show me that the reset gets to my register with the appropriate setup (timing parameters such as Trck) to allow my system to start properly after the reset deasserts. Care should be taken that events not controlled by the reset (processor interrupt, for instance) are covered by the timing analysis for the invocation of reset or that the signals are otherwise safe. It's not the cleanest timing analysis from the auto-generated constraints standpoint but I imagine I could get the constraints to look good. Personally, I prefer to stick with true synchronous resets through the synchronous reset mechanism. Nial Stewart wrote: > > By registering the reset > > signals in the local clock domains, the reset will be applied to all > > elements within that clock domain in one clock cycle and be subject to > > the timing constraints for the clock period constraint. > > John, > > Does this apply if you synchronise your reset net at the top level and then > use it throughout your design with 'standard' asynch reset declarations.... > > process(clk,rst) > begin > if(rst = '1') then > signal <= reset_val; > elsif(rising_edge(clk)) then > > ..and so on, or do you have to use > > process(clk) > begin > if(rising_edge(clk)) then > if(rst = '1') then > signal <= reset_val; > elsif....... > > ? > > Nial. > > -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- > -- To email remove spamno from address.Article: 48273
--------------AB075A85A52036C41662103A Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Here are the K2 values for Virtex-IIPro: CLB @1.50V: K2 = 27.2, i.e. 1/K2 = tau = 36.8 picoseconds CLB @1.35V: K2 = 23.3, i.e. 1/K2 = tau = 42.9 picoseconds CLB @1.65V: K2 = 35.7, i.e. 1/K2 = tau = 28.0 picoseconds IOB @1.50V: K2 = 24.4, i.e. 1/K2 = tau = 41.0 picoseconds IOB @1.35V: K2 = 19.24, i.e. 1/K2 = tau = 52.0 picoseconds IOB @1.65V: K2 = 44.05, i.e. 1/K2 = tau = 22.7 picoseconds For each extra 100 ps of acceptable metastable delay, the MTBF increases by a factor 10.3 for CLB @ 1.35 V, or a factor 6.85 for IOB @ 1.35 V. Much better values, of course, at nominal or high Vcc. Klick on http://support.xilinx.com/support/techxclusives/techX-home.htm in early November. Here is the worst-case data point: 50 MHz asynchronous data rate, 330 MHz clock , single-stage synchronizer in IOB, Vcc = 1.35 V: clock-to-Q + short routing + set-up time + metastable delay exceeds clock period once per 30,000 years. At nominal Vcc: once per 100 million years. At a 250 MHz clock rate, delay exceeds clock period less often than once per billion years. Peter Alfke, Xilinx Applications ==================================== Hal Murray wrote: > > When is Xilinx going to put numbers into the data sheets? Worst case? > > I wouldn't say "overrated". It might be less of a problem now > than it was a while ago. But users demands/expectations are going > up too. > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam.Article: 48274
Dear Emanuel,
Microblaze is heavily pipelined so can be clocked faster than
picoblaze. OTOH, Picoblaze uses far fewer FPGA resources.
HTH, Syms.
emanuel stiebler <emu@ecubics.com> wrote in message news:<3DABA42C.8321741C@ecubics.com>...
> Hi,
>
> anybody out here has some insight, why the 8 bit picoblaze (up 112 MHz)
> is clocked lower than the 32 bit microblaze (up 150 MHz) ?
>
> cheers
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z