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For the chip to die of thermal damage, the die would have to be significantly hotter than 150 degrees C. We have shipped Xilinx FPGAs into down-hole equipment where the chip is operating several kilometers down, at the bottom of oil-drilling equipment. The FPGAs (and SRAMs and A/Ds) worked for weeks at an ambient temperature of 175 degrees Celsius. Silicon is much tougher than most people assume. :-) I have to believe you when you say you had a problem, but 65 degree chip temperature was not the real cause. Peter Alfke, Xilinx Applications ============================================ Pierre Lafrance wrote: > Hi all > I respined a product, changing the old Xilinx XV-300 with a XCV-600E. > Of course, I had to change voltage regulator from 2.5 to 1.8 volts, > and few 5 volts CPLD to 3.3v. > > The problem is : the XCV-600E overheat, and 1 of the prototype just > died. > I tried to find any hardware signal that would exceed voltage but > couldn't. Hardware seems to be just fine. I suspect the chips itself > to overheat. I just put a heatseak temporarly, but would like to > solve the problem if I can. > > Simulation with XPower estimate the chips temperature to be 50C, but I > measure up to 65C. > > The disign use 75% of BRAM, and 75% of FF of the XCV-600E. > Clock is 82MHz. > > Anybody experienced overheat with 600E ? > > Cheers ! > > PierreArticle: 47176
I'm having difficulty finding information on XCV600's on the Xilinx site. Part of the problem is I know nothing about this type of part, including terminology. I have two boards with this part, but do not know how to check if they are the same revision, whether the firmware (?) is the same, or where to get the firmware, if it is compatible. Any constructive suggestions would be appreciated.Article: 47177
Hi, Sorry that I ask the question about IC layout, but I cannot find any newsgroup about IC layout. Sorry for any inconvinence. Anyone can tell me some homepage or newsgroup talk about IC layout? Thank you. RealaArticle: 47178
hi, I am upgrading a XC5200 based project to spartenXL using Foundation1.5. the project can maped in xc5200. But when I set to spartenxl, many map errors report like : ERROR:x4kma:339 - The CY4 symbol "U24/$I1219/$1I25" (output signal=U24/$I1219/C12) has no signal connected to B1. This pin must be connected based on carry moded SUB-FG-CI. Xilinx answer database: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=6571 told me this may caused by connect non-GSR signal to GSR pins on symbols . I still confused on how to fix it. I notice there are 2 clocks connect to different clks of latchs in my system.There is a 16 bit magnitude compatator. when I delete the buffer connect to all clock, the project can maped. Other wise there would be a error. Does anybody ever fix this problem? what is GSR Pin? ThxArticle: 47179
Hi, I am new to designing in FPGA and CPLD. What are the issues to consider when designing DDR input and output logic in CPLD? Thanks, JamesArticle: 47180
Keep your design synchronous, or it will be
a real beach to get an ASIC made later.
Here's the verilog way...
module clk_divider(rsnt, clk, div10_qual, etc)
input clk;
output div10_qual;
reg [3:0] div10_cntr;
wire [3:0] next_div10_cntr = div10_cntr + 1;
wire wrap_div10_cntr = ~(next_div10_cntr < 10);
always @(posedge clk or negedge rstn)
if(~rstn)
div10_cntr <= 0;
else
if(wrap_div10_cntr)
div10_cntr[3:0] <= 0;
else
div10_cntr[3:0] <= div10_cntr[3:0] + 1;
assign clk_div10_qual = wrap_div10_cntr;
endmodule
Now use the same clk in whatever module needs
the divide by 10, gated with the qual signal, so
you will maintain a synchronous design.
BB
=====================================
"Denis Gleeson" <dgleeson@utvinternet.com> wrote in message
news:6f080894.0209161249.2f0e2102@posting.google.com...
> Hello ALL
>
> I have a 50MHz clock that I want to divide by 10 and then by 10
> and so on.
> Actual outputs required are
>
> 50MHz
> 5MHz
> 500KHz
> 50KHz
> 5KHz
> 500Hz
> 50Hz
>
> I think I could do a divide by 10 but I dont know how to achieve
> all these divides.
>
> I also wonder if I can have the main clock driving all flip flops together
> rather than have the MSB output of the first divide by 10 rippeling
through
> to the next counter and so on.
>
> Im coding in Verilog so any suggestions there would help.
>
> Thanks
>
> Denis
Article: 47181Blackie Beard wrote: > Keep your design synchronous, or it will be > a real beach to get an ASIC made later. <snip> How many people can still afford an ASIC? I don't want to start a flame, am just curious. At 130 nm just the mask set (~30 masks) is close to a million dollars, excluding design and verification efforts (That's a basic fact, we pay this all the time)... Is this irrelevant? Just asking, I may be living in a biased environment. Please no flames ! Peter AlfkeArticle: 47182
Don't worry, no flames, just two points in defense:
1. What if you do decide to go to an ASIC later?
wouldn't it have better to do it correctly? Also,
why multiply by a factor of 100 the possible
timing difficulties that can arise from a non-
synchronous design? Suppose the product
becomes popular (else why bother, maybe).
2. Depends on quantities. If you are talking about
selling less than 10K units over the lifetime of
the product (10K being an arbitrary number)
then the choice is FPGA. And ASIC's I've seen
from some vendors, for around 50K gates, will
only run $50-80K Non-recurring backend costs,
then $3-4 per unit (Qty 10K). Have a look at
chip express, AMD, etc. The prices you are
quoting sound like a custom analog design
with a huge die, and they are doing total design.
Anyway, that's my experience. Shop around.
: )
BB
===========================================
"Peter Alfke" <palfke@earthlink.net> wrote in message
news:3D8A8C44.FCE50C8F@earthlink.net...
>
>
> Blackie Beard wrote:
>
> > Keep your design synchronous, or it will be
> > a real beach to get an ASIC made later. <snip>
>
> How many people can still afford an ASIC?
>
> I don't want to start a flame, am just curious.
> At 130 nm just the mask set (~30 masks) is close to a million dollars,
> excluding design and verification efforts (That's a basic fact, we pay
this all
> the time)...
> Is this irrelevant?
> Just asking, I may be living in a biased environment. Please no flames !
>
> Peter Alfke
>
Article: 47183
I just want to clarify the statement:
> Now use the same clk in whatever module needs
> the divide by 10, gated with the qual signal, so
> you will maintain a synchronous design.
I don't mean like:
div10_clk = clk & div10_qual;
as then your design would not be synchronous.
I mean like this:
wire div_qual = (div == `DIV10) ? div10_qual : 1'b1;
always @(posedge clk or negedge rstn)
if(~rsnt)
whatever
else
if(div_qual)
whatever else
It will synthesize differently. So design is
synchronous, (everything throughout
your "chip" uses the same clock).
BB
=====================================
Article: 47184There ought to be a comp.arch.asic group. There are some groups if you search on 'chip'. But I don't know how relevant they are to you. "Reala" <-> wrote in message news:amdu7m$gar17@imsp212.netvigator.com... > Hi, > > Sorry that I ask the question about IC layout, but I cannot find any > newsgroup about IC layout. > Sorry for any inconvinence. > > Anyone can tell me some homepage or newsgroup talk about IC layout? > Thank you. > > Reala > > >Article: 47185
The only time I've ever seen an FPGA overheat was when I was driving output pins into outputs, usually caused by an incorrect pinout. Did you recompile with the updated pin file? Is it a new board, or did you hack?Article: 47186
In Peter's defense, I see several designs a year that claim to have intention
to move to an ASIC. Few if any ever do. Worse, if you code for an easy
transition to an ASIC, you leave many of the FPGA features on the table,
resulting in a design that is both bigger and slower than it would be for a
design specifically targeted to the FPGA. My advice if you intend to go that
route is to design specifically to the FPGA, then later if you decide to go to
ASIC start fresh. If the economics are there for the ASIC, the added design
cost for doing the design right are close to negligable and it buys you an
advantage for the period you are selling the product with an FPGA. That said,
the majority of design for FPGAs should be done as synchronous design. The
FPGAs as well as the tools are geared toward synchronous design, it is easier
to verify, and easier to get through reviews.
Blackie Beard wrote:
> Don't worry, no flames, just two points in defense:
>
> 1. What if you do decide to go to an ASIC later?
> wouldn't it have better to do it correctly? Also,
> why multiply by a factor of 100 the possible
> timing difficulties that can arise from a non-
> synchronous design? Suppose the product
> becomes popular (else why bother, maybe).
>
> 2. Depends on quantities. If you are talking about
> selling less than 10K units over the lifetime of
> the product (10K being an arbitrary number)
> then the choice is FPGA. And ASIC's I've seen
> from some vendors, for around 50K gates, will
> only run $50-80K Non-recurring backend costs,
> then $3-4 per unit (Qty 10K). Have a look at
> chip express, AMD, etc. The prices you are
> quoting sound like a custom analog design
> with a huge die, and they are doing total design.
>
> Anyway, that's my experience. Shop around.
> : )
> BB
> ===========================================
>
> "Peter Alfke" <palfke@earthlink.net> wrote in message
> news:3D8A8C44.FCE50C8F@earthlink.net...
> >
> >
> > Blackie Beard wrote:
> >
> > > Keep your design synchronous, or it will be
> > > a real beach to get an ASIC made later. <snip>
> >
> > How many people can still afford an ASIC?
> >
> > I don't want to start a flame, am just curious.
> > At 130 nm just the mask set (~30 masks) is close to a million dollars,
> > excluding design and verification efforts (That's a basic fact, we pay
> this all
> > the time)...
> > Is this irrelevant?
> > Just asking, I may be living in a biased environment. Please no flames !
> >
> > Peter Alfke
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47187
That sounds a little bit hot for a 600E clocked at 82 MHz, although if
lots of your LUTs are SRL16's that are being clocked all the time and
there is no airflow, it is concievable. Even so, it takes a lot of heat
(much more the 65C) to kill the part outright. More likely, you got the
pinout wrong and are driving out on pins that are also being driven by
something else. In that case, it is possible to damage the output
drivers. Another possibility is ESD damage.
Pierre Lafrance wrote:
> Hi all
> I respined a product, changing the old Xilinx XV-300 with a XCV-600E.
> Of course, I had to change voltage regulator from 2.5 to 1.8 volts,
> and few 5 volts CPLD to 3.3v.
>
> The problem is : the XCV-600E overheat, and 1 of the prototype just
> died.
> I tried to find any hardware signal that would exceed voltage but
> couldn't. Hardware seems to be just fine. I suspect the chips itself
> to overheat. I just put a heatseak temporarly, but would like to
> solve the problem if I can.
>
> Simulation with XPower estimate the chips temperature to be 50C, but I
> measure up to 65C.
>
> The disign use 75% of BRAM, and 75% of FF of the XCV-600E.
> Clock is 82MHz.
>
> Anybody experienced overheat with 600E ?
>
> Cheers !
>
> Pierre
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47188Yep, ModelSim is a bit tricky. You may want to try the following: When inside the ModelSim (even with an error), go to "Options" menu, then "Compile...", then "Verilog". You will have an option to add a path to libraries and includes, and command-line global defines. The applet will create a file "vlog.opt" in the project directory, and a line in the "modelsim.ini" file pointing the "vlog.opt". Keep the vlog.opt away from your root directory (it may be overwritten), and edit the path pointer to it in the local modelsim.ini. Another problem I saw was that some new primitives were not in the xilinx primitive file (I forgot which one), it looks like few files may be out of synch. Do search for your missing X_CLKDLL in the Xilinx root directory, and append the model. Regards, - A "tony" <at@cloanto.com> wrote in message news:654ee494.0209191136.1f668992@posting.google.com... > I have just downloaded the Modelsim XE simulator form the Xilinx > site, and I am trying to understand how it works. > > I would like to instantiate a CLKDLL and I have found out that > the simprims_ver library has a part called X_CLKDLL and I used > that one although I am at loss to explain the leading X_. The > instantiation looks like this: > > X_CLKDLL clkdll1( .CLK0(), > .CLK90(), > .CLK180( clk_90), > .CLK270(), > .CLK2X( clk_out ), > .CLKDV(), > .LOCKED(), > .CLKIN( clk ), > .CLKFB( clk ), > .RST( rst ) ); > > Now what happens is that when I compile the design (the file plus the > testbench) everything works smoothly, but when I load the design for > simulation, the X_CLKDLL instantiation generates an error, and won't > continue. Here is the output > > # Loading work.test_counter > # Loading work.counter > # ERROR: C:/Projects/Modelsim/verilog/counter/counter.v(37): Instantiation > of 'X_CLKDLL' failed (design unit not found). > # Region: /test_counter/dut > # Searched libraries: > # work > # Error loading design > > Apparently Modelsim is not using the XILINX libaries (which, based on > what I found on the Xilinx knowledge base, are precompiled in the XE > simulator). > > My first attempt was to add a library path before compiling the source > code. I did this using the compile dialog box, and clicking on the > "Default Options..." button. I pointed the directory to > > C:/"Program Files"/Modelsim/xilinx/verilog/simprims_ver > > where the X_CLKDLL module is. But even in this case, I had no luck. > Further search on the internet proved also useless. I am left with the > question of how to use library part for simulating verilog code with > Modelsim XE. > > Can anybody help out with this? > > Thanks a lot > TonyArticle: 47189
OK. Since I'm from the world of ASIC design, using FPGA's mainly for ASIC prototype verification, I'm ignorant of what types of FPGA features would emerge as advantages if synchronous design techniques were thrown out the window. I know you can do more stuff (clock doubling, pos/neg edge, easier clk divider code), but how does it reduce gate count? Thanks, BB ================================================ > if you code for an easy > transition to an ASIC, you leave many of the FPGA features on the table, > resulting in a design that is both bigger and slower than it would be for a > design specifically targeted to the FPGA.Article: 47190
I got so tired of trying to make Modelsim work, I switched to a different sim tool, even though Modelsim was free in my case. Then my testbench was working within 10 minutes.Article: 47191
The links below are good places to start. http://www.altera.com/products/devices/stratix/features/stx-dram.html http://www.altera.com/literature/an/an212.pdf Additionally cores are available for this purpose http://www.altera.com/products/ip/altera/m-alt-ddr_sdram.html - DS "James Wong" <james88664@mail.com> wrote in message news:ee79125.-1@WebX.sUN8CHnE... > Hi, > I am new to designing in FPGA and CPLD. What are the issues to consider when designing DDR input and output logic in CPLD? > Thanks, > JamesArticle: 47192
Peter Alfke wrote: > > Blackie Beard wrote: > > > Keep your design synchronous, or it will be > > a real beach to get an ASIC made later. <snip> > > How many people can still afford an ASIC? > > I don't want to start a flame, am just curious. > At 130 nm just the mask set (~30 masks) is close to a million dollars, > excluding design and verification efforts (That's a basic fact, we pay this all > the time)... > Is this irrelevant? > Just asking, I may be living in a biased environment. Please no flames ! > > Peter Alfke So just go with a 210 nm process where they are begging you to use their fabs. Maybe they are having a special and will give the masks away for free!!! B^) The OP was using an XCS05! I don't think that is done in anything close to a 130 nm process, is it? What are we talking, 250 nm or bigger, right? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47193
Kamal Patel wrote: > > Giuseppe, > > This is correct. Windows XP and Windows 2000 will > be the only supported Microsoft operating systems > for 5.1i, although 5.1i should still install and > run fine on Windows NT. > > Regards, > Kamal Patel > Xilinx Apps Let me get this straight. version 4.x supported 98, ME(?), NT, 2000, but definitely NOT XP. Now that they are adding XP, they are also dropping, 98, ME and NT??? I would have looked this up, but I think it is on a page that is a 1.5 MB PDF file. Interesting that Xilinx thinks it is ok to have a single web page of 1.5 MB, but breaks up their data sheets when they are this size... I am more than able to finish this email while I am waiting for the page to load. When the page finishes, I bet it is full of pretty graphics that have no information content but bloat the size so much... bet anyone??? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47194
Hello! I've to change the software for a xc5210-5pq208-i which is running on a controller board. The board cannot be changed but the software has to be modified. The sourcecode is in vhdl. I've got no old software like xact, only the new ise 4.2i. Is there any possibilaty or trick to create a new prom file for this old fpga with the new software? Thanks for every posting, NorbertArticle: 47195
Few days ago I was trying to solve the temperature problem in Spartan-2. The device went wrong (without permanent damage, however) when the PCB was at 100 deg C (the estimated silicon temp. was approx. 130 deg C). Going into details I have found that the failing unit was one of DLLs used as a clock mirror. I have solved the problem just by removing the DLL - with the cost of some clock delay and lower performance. What was strange to me: two other DLLs used for frequency multiplication/division were operating OK. The same behaviour has been found in three devices. Shall I worry about the other DLLs operation at high temp? Is something special with DLL working as a clock mirror that it fails first? Dziadek Peter Alfke wrote in message <3D8A4CB9.79158CD3@xilinx.com>... >For the chip to die of thermal damage, the die would have to be >significantly hotter than 150 degrees C. We have shipped Xilinx FPGAs >into down-hole equipment where the chip is operating several kilometers >down, at the bottom of oil-drilling equipment. The FPGAs (and SRAMs and >A/Ds) worked for weeks at an ambient temperature of 175 degrees Celsius. >Silicon is much tougher than most people assume. :-) > >I have to believe you when you say you had a problem, but 65 degree chip >temperature was not the real cause. > >Peter Alfke, Xilinx Applications >============================================Article: 47196
rickman wrote: > > Kamal Patel wrote: > > > > Giuseppe, > > > > This is correct. Windows XP and Windows 2000 will > > be the only supported Microsoft operating systems > > for 5.1i, although 5.1i should still install and > > run fine on Windows NT. > > > > Regards, > > Kamal Patel > > Xilinx Apps > > Let me get this straight. version 4.x supported 98, ME(?), NT, 2000, > but definitely NOT XP. Now that they are adding XP, they are also > dropping, 98, ME and NT??? > > I would have looked this up, but I think it is on a page that is a 1.5 > MB PDF file. Interesting that Xilinx thinks it is ok to have a single > web page of 1.5 MB, but breaks up their data sheets when they are this > size... I am more than able to finish this email while I am waiting for > the page to load. When the page finishes, I bet it is full of pretty > graphics that have no information content but bloat the size so much... > bet anyone??? I was right and wrong. The file did contain a pointless background graphic that jumped the size up, but it did not have the platform requirements I was looking for. I did find it in the Webpack installation I have on this machine. If ISE is the same as Webpack, Xilinx has dropped support for Windows 98, ME and NT with the 5.1 release. That leaves a lot of users out in the cold. I know one company who had pretty much standardized on NT since they did not see much reason to pay MS a much of loot to go to 2000. I guess they will have to rethink that now. Speaking of MS, anyone know what little tricks they are using to get companies to switch from 98, ME, NT and 2000 to XP? I just can't belive they are going to sit by and let everyone keep using the old OS with licences that can't be well enforced. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 47197
Duane:
Thanks for your reply.
> In any case, wherever you have the Xilinx software installed, there
> should be a library xilinx\vhdl\src\unisims that contains the correct
> libraries to use for your simultation.
I checked and the libraries are there. But they are in a VHDL directory
and I am trying to use verilog. Also, assuming that the VHDL libraries
are to be used, I still do not understand HOW to do it; I have replaced
X_CLKDLL with clkdll (because clkdll is part of the unisim directory)
but the result is exactly the same, which is that Modelsim does not find
the clkdll data:
# Loading work.test_counter
# Loading work.counter
# ERROR: C:/Projects/Modelsim/verilog/counter/counter.v(37): Instantiation
of 'clkdll' failed (design unit not found).
# Region: /test_counter/dut
# Searched libraries:
# work
# Error loading design
Now that I know (thanks to your reply) where to find the goods, I need some
help on how to coerce Modelsim to use them in my verilog code.
Thanks again.
Tony
P.S. I fiddled again with the verilog options that you access through the
"Default Options..." button under the "Compile HDL" dialog box, but to no
avail.
Article: 47198On Fri, 20 Sep 2002 03:55:02 GMT, Ray Andraka <ray@andraka.com> wrote: >In Peter's defense, I see several designs a year that claim to have intention >to move to an ASIC. Few if any ever do. Worse, if you code for an easy >transition to an ASIC, you leave many of the FPGA features on the table, >resulting in a design that is both bigger and slower than it would be for a >design specifically targeted to the FPGA. My advice if you intend to go that >route is to design specifically to the FPGA, then later if you decide to go to >ASIC start fresh. Actually there is no reason to start fresh with the ASIC. Anything you can do with any FPGA, you can do in standard cell easily (maybe except the 16 bit memory blocks, larger size SRAM is relatively easy). So it makes sense to use all features of the FPGA and then map them to standard cell. I'd bet one can do better with a .25u standard cell ASIC than any optimized FPGA at .13u process. One exception maybe the multipliers in Virtex-II or better the DSP block in Stratix. Especially the latter takes advantage of fully custom hard macro in a .13u 8LM copper process so it would be difficult to do better with .25u. But having the full flexibility of having all the metal layers only to the routing of hard wired gates still might be an advantage. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 47199
Hi > I respined a product, changing the old Xilinx XV-300 with a XCV-600E. > Of course, I had to change voltage regulator from 2.5 to 1.8 volts, > and few 5 volts CPLD to 3.3v. [...] Try to see what current takes board and look at voltage directly at the Virtex. Maybe voltage in this place is to low ie. 3.0V then virtex starts behave unstable - can take more current then should. Maybe this is the point (power supply). 65C is normal temperature. furia
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