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Hi As I said, I'm looking for more technical info about OFDM. Possibility to implement it in FPGA, maybe some HDL sources. I'll be very glad if You could help me. Best regards JurekArticle: 46676
Hello, Following this news group, I see alot of post on Xilinx and Altera. But I do not see much on Actel. Is any one using the ProAsicPlus and are you also using Libero in particular verilog. Thank you Dave ColsonArticle: 46677
Still seem to be getting 'unsigned 9 does not match type unsigned int 32' everywhere. The problem is, all my variables are 32 bits except where I have had to extract the least significant x bits to keep the compiler happy. How does the Handel-C error reporting system actually work? Clicking the '+' next to the red hand with the error reveals two blue arrows, both reporting errors in line 137: mdct.hcc Ln 137, Col 3-28: Type 'unsigned int 9' does not match type 'unsigned int 32' line 137: mdct_hardware_backward(n); Now expanding both blue arrows takes me to errors in line 894: mdct.hcc Ln 894, Col 4-11: Type 'unsigned int 9' does not match type 'unsigned int 32' mdct.hcc Ln 894, Col 8-10: Type 'unsigned int 9' does not match type 'unsigned int 32' line 894: out[oX] = MULT_NORM (-inp[iX+2] * trig_256[T+3] - inp[iX+0] * trig_256[T+2]); For information, n is unsigned 32, inp[] is array of signed 32, trig_256 is an array of signed 32, MULT_NORM is defined as #define MULT_NORM(x) ((x)>>14) I'll stick the whole workspace in http:/www.sli-institute.ac.uk/~gk/mdct.zip it should be quite small. GovArticle: 46678
In article <3D76F8AE.A73FC8B8@myrealbox.com>, Robin KAY <komadori@myrealbox.com> wrote: >[quote from Dennis O'Connor] >] - PALcode is decoded by the normal decoder, as opposed to to microcode, >] which is often a raw mask over a processor's internal control lines. > >That's what's called "horizontal" microcode. "Vertical" microcode >is often used, and is usually a minor superset of the non-microcoded >portion of the instruction set. Apparently you've never heard of it ? >[/quote] When vertical microcode fits the description above, IBM calls it "millicode". Microcode often uses a different instruction set for a "microengine" that is specialised for implementing the actual ISA. Some microinstructions may be effectively the same as some single-cycle "real" instrs, but the encoding may be different (e.g. because the microengine has more registers than the ISA). In this sense. modern IBM mainframes don't have microcode anymore: they have a hard-wired base instruction set augmented by millicode. The latest IBM Journal of Research and Development has a nice article on the microarchitecture of the z900. Michel.Article: 46679
thank's to all. @++, -- LaurentArticle: 46680
I did download a free version of Libero called Libero Silver a
month ago, but I ended up erasing it from my computer because the
Synplify-Lite that came with it was too restrictive.
The design in question was an IP core, and it needed to be synthesized
without I/O pads inserted because that's the way I designed it, but
Synplify-Lite won't let me synthesize the design without I/O pads.
Besides that, Libero Silver's device support is way too restrictive
compared to Xilinx and Altera's free tools.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Dave Colson wrote:
>
> Hello,
>
> Following this news group, I see alot of post on Xilinx and Altera.
> But I do not see much on Actel. Is any one using the ProAsicPlus and
> are you also using Libero in particular verilog.
>
> Thank you
> Dave Colson
Article: 46681I was able to run programs on a 6 MHz IBM AT computer. Nowadays we have 2 GHz machines. so why the need for higher speed? (rhetorical) hristo wrote: > in image processing and with color PAL , 33.32 Mhz is enough to do real time, > with less image size, the sufficient speed is much less > so why the need for higher speed? > > any practical casesArticle: 46682
Try looking into STREAMS-C compiler work ...
http://rcc.lanl.gov/Tools/Streams-C/
They have a freely downloadable C->VHDL compiler built on top of the
SUIF infrastructure that is also freely available.
Cheers,
Andy
Article: 46683The problem may just be with the "dimensionless" zero. I'd expect XST - and most synthesziers - to interpret 0 as a 32 bit value. Since (I expect) all you want is the single bit low, substitute the dimensioned constant 1'b0 and things should come together. Sizing constants is a fundamental part of Verilog; if you're not already familiar with the different forms (hex, decimal, binary, etc) check into a good Verilog reference. The first hit for my search on "Libraries Guide" was: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=7298 You find directions there. In the HTML collection you'll have a list of documents on the left of your browser window, one of which is the "Libraries Guide." The associated library elements mention whether they are Not Applicable, a Primitive, or a Macro for the various device families. Reala wrote: > Dear all, > > I write a code for modelsim in netlist formal. > eg: > mux mux1(muxout,0,yi,xi,si,xj,yj); > The simulation is OK. > > However, it is a warning for "0" in Xilinx Webpack for systhesis. > Actually,I want to connect this to "Gnd" or VCC". > How can I do? > Moreover I would like to find a library guide for Spartan-II XC2S200, > because my design in netlist format. I try to search in xilinx webpage but I > cannot find the information i want. > > Sorry for the simple question. > > RealaArticle: 46684
There's a different XY coordinate for each slice in the Virtex-2, right? The
X0Y0 should be as explicit as the Spartan-II R0C0.S0 format. The design
compiles fine with R0C0.S0 in a Spartan-II but errors in the Virtex-II with the
X0Y0 format. I tend to believe this is an honest bug.
I tried a couple things without success. The next suggestion is to look into
the COMPRESSION=1 constraint for the module ramq defined by an AREA_GROUP. I'd
try it for you but I have to get my day moving. Good luck!
- John_H
Jan Gray wrote:
> Following up on my earlier article, "RAM32X1S, Virtex-II, 4.1i PAR travails"
> (
> http://groups.google.com/groups?selm=a5j91k%24akt%241%40slb3.atl.mindspring.
> net ), I am now trying to make a trivial RPM, consisting of a RAM32X1S and a
> DFF, RLOC'd to the same slice.
>
> No matter what I try (including adding BELs), no joy.
>
> I get a variant of:
>
> ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=r/hset,
> RLOC=X0Y0)
> which require the combination of the following symbols into a single slice
> component:
> FLOP symbol "r/dff" (Output Signal = q)
> RAM symbol "r/ram/F" (Output Signal = r/ram/F)
> RAM symbol "r/ram/G" (Output Signal = r/ram/G)
> WEDECODE symbol "r/ram/WEDECODE" (Output Signal = r/ram/WEDECODE)
> BUF symbol "r/ram/BXBUF" (Output Signal = r/ram/A4')
> Unable to pack the register r/dff because of connectivity restrictions.
> Please correct the design constraints accordingly.
>
> I happen to know this is a perfectly legal packing of the slice, because if
> I DELETE the RLOC constraint on the DFF, the placer is quite happy to place
> the DFF in the same slice as the RAM32X1S on its own initiative.
> Specifically, the two 4-LUT RAM outputs go through the F5MUX, the F5 input
> of the FXMUX, and out onto output X, then back in on input DX, through the
> DXMUX and into the D input of FFX.
>
> This problem occurs in 4.1i, so I thought I'd try it under 4.2i. So I
> installed 4.2i. And 4.2i SP3. See following message for my blue screen of
> death travails there.
>
> Nope, not even 4.2i SP3 will accept my RAM32X1S and my DFF RLOC'd to the
> same slice.
>
> Can anyone offer any workarounds short of hard LOCs or XDL? I use RPMs to
> get repeatable datapath placements and timings so that I can tune up my
> design in a methodical way. Anything else is playing whack-a-mole on the
> critical paths.
>
> Quick and dirty Synplicity example:
>
> module tramq(clk, i, o);
> input clk, i;
> output o;
> reg o;
> reg we;
> reg [4:0] ad;
> reg d;
> ramq r(clk, we, ad, d, q);
> always @(posedge clk) begin
> {we, ad, d} <= {ad, d, i};
> o <= q;
> end
> endmodule
>
> module ramq(clk, we, ad, d, q)
> /* synthesis syn_hier="hard"*/;
> input clk, we, d;
> input [4:0] ad;
> output q;
> wire o;
> RAM32X1S ram(.A0(ad[0]), .A1(ad[1]), .A2(ad[2]), .A3(ad[3]), .A4(ad[4]),
> .D(d), .O(o), .WCLK(clk), .WE(we))
> /* synthesis RLOC="X0Y0" */;
> FD dff(.C(clk), .D(o), .Q(q))
> /* synthesis RLOC="X0Y0" */;
> endmodule
>
> Thanks.
> Jan Gray, Gray Research LLC
Article: 46685"Havatcha" <nospam@nospam.com> wrote in message news:3D77377E.9070006@nospam.com... > Petres, Zoltan wrote: [deleted] > You define the entire network in a hardware description language (like > VHDL or verilog) and download this onto the FPGA, so you know implicitly > the entire architecture of the network. Assuming you have prior > programming experience you should be able to learn VHDL, it can be a bit > confusing since you have to think in terms of parallel hardware but it > is worth a go. You can download software that will do this from > www.xilinx.com for free but you will need to buy the cable to connect > from your PC to the FPGA board. (100 dollars) > You will also need to build the board to mount the FPGA onto so some > electronics knowledge would be advisable. Where on that rather large website? Do you have to already have a license for some particular product to even see the part of the website where you can do the download? I'd like to learn VHDL also, while I'm unemployed and therefore have little money to buy anything.Article: 46686
Quite a while ago I wanted to make a chess program for my Acorn Atom. (1 MHz 6502 8-bitter CPU). So I overclocked the thing to 2 MHz, added 16 kB more RAM (which cost me around 700 USD), wrote a Minimal BASIC compiler with 8-bit arithmetic (-127 to +127) to get some speed, etc. Those were the days... Frank "John_H" <johnhandwork@mail.com> wrote in message news:3D7784D5.8C7480F5@mail.com... > I was able to run programs on a 6 MHz IBM AT computer. Nowadays we have 2 GHz > machines.Article: 46687
"Dave Colson" <dscolson@rcn.com> wrote in message news:<al7qan$1o0m8o$1@ID-159190.news.dfncis.de>... > Hello, > > Following this news group, I see alot of post on Xilinx and Altera. > But I do not see much on Actel. Is any one using the ProAsicPlus and > are you also using Libero in particular verilog. > > Thank you > Dave Colson Once I found out about ProASIC+ back in Jan. or Feb., I started porting all our microcontroller IP over to that platform. I have the full Libero "Platinum" package. ProASIC+ is working quite nicely for us. To date I've synthesized (using Synplicity that comes with it) a 24.5 MHz 68HC05 microcontroller, a 16C5x, and a proprietary 9-bit RISC we call the Q90. These designs included ACIA, timer/counters, PIO, up to 8k program RAM, and JTAG real-time debug/monitor interface. Our company, www.quickcores.com, has already introduced a low cost IP delivery system based on the ProASIC+. It was originally intended as an FPGA-embeddable microcontroller platform, but it can also be used as a handy platform for non-microcontroller designs. JerryArticle: 46688
--------------44F3B418D644882BA4DEFFAE Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Kevin, What can I say but the squeaky wheel gets the grease.... Kevin Brace wrote: > What I don't understand about Xilinx is that, XST of ISE 4.x can > actually generate an EDIF netlist, but Xilinx refuses to let people use > it from ISE's VHDL or Verilog GUI design flow. Since an EDIF file from XST is not a supported flow I think that we would be giving mixed messages if we were to allow EDIF as an output option. However plenty of work arounds (as you have discovered) exist to bypass this and still use the ISE GUI. > > > http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&threadm=aceeac%249fj%241%40newsreader.mailgate.org&rnum=1&prev=/groups%3Fhl%3Den%26lr%3D%26ie%3DUTF-8%26selm%3Daceeac%25249fj%25241%2540newsreader.mailgate.org > Please, Xilinx, stop spreading the lies that XST of ISE 4.x cannot > generate and EDIF netlist. I do not recall anyone at Xilinx stating that you can not generate an EDIF file from XST in 4.x software. We have never promoted EDIF as an output from XST for the fact that it is not supported. The fact that 4.x XST can generate an EDIF file was actually a poorly kept secret (sorry if this might dispell some consipracy theories...) About half way through the development process of 4.1i the decision was made to move away from EDIF and to generate an NGC file. Because the decision was made halfway through the development of 4.1i any work that was needed to be done to add constraints (specifically for the Virtex-II parts) was not done in the EDIF generation but only in the NGC generation. As such, you will get an EDIF file that is logically correct but could be missing attributes/cosntraints that you might expect. As our chips are getting larger we find it necessary to couple our tools together more tightly. By writing directly to NGC we are skipping a portion of the "translate" process. We are only treating XST as a Xilinx tool and not a 3rd party tool. Starting with 5.1i software the EDIF output has been removed from XST. There, I said it, 5.1i XST can not generate EDIF files. However, an RTL/technology viewer will be in place to view the results that XST generates. There also will be an ngc2edif executable that will produce an EDIF file without an typ of INIT programming information. This is for CORE Generator cores that might be producing NGC files and synthesis tools that will want to read in EDIF cores for timing analysis. Steve Elzinga > > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.) > > Vikram Pasham wrote: > > > > Rajeev, > > > > A good place to look is XST log file. XST might have given some warnings on nets > > with multiple drivers. Also, search on support.xilinx.com for answer records on > > Ngdbuild multiple driver error messages. > > > > ISE 5.1i provides an NGC to EDIF translator to generate a readable netlist file. > > ISE5.1i also provides a RTL schematic viewer which can be used to track such > > re-named internal nets. > > > > -Vikram > >Article: 46689
im Granville wrote: > > Kevin Brace wrote: > > > > rickman wrote: > > > > > > > > > I guess I never realized that you did not own full rights to the bit > > > stream from your design... amazing. > > > > > > > I see why you are disgusted with the ruling, and while I, too, > > don't agree with the ruling, let's say if you were an IP core vendor who > > is trying to collect royalty payment for each chip (or board) sold. > > If the licensee for some reason stops paying the royalty, wouldn't you > > have the right to sue and collect royalty from the licensee because the > > licensee's design contains the licenser's IP core? > > Also, most IP cores provided by PLD vendors prohibit conversion to an > > ASIC, unless the licensee gets a special permission. > > Of course, IP is protected separately, but this ruling made no > distinction > of IP, it was a Software-License usage issue. > So, if you create just a 16 bit counter, with zero Altera IP, that's > still > covered. I understand that. But your post made it sound like it was about IP and I can understand Altera (or anyone else) wanting to protect their IP. In fact, I think Altera makes the IP available with no royalties because the idea is that you are paying for the royalty when you buy their chips to put the design in. But they certainly don't have the same issue with the bitstream. I understand that the court has ruled that ClearLogic must cease making these parts. But as I said, I would expect to have full rights to my own design. I am surprised that running it through Altera tools would limit my rights. > > > Does Xilinx also have that restriction? If I want to use my bitstream > > > to program an ASIC, am I prohibited? I still don't know if Xilinx has this same restriction in the tools. I will be downloading the new Webpack soon, I will check the license. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46690
Yes, when you go to the web page to download it, it says version 4.2WP3.0. When the new version is available, you should be able to get a CD at http://208.129.228.206/solutions/kits/xilinx/webpack/ I got one of the 4.2 versions that way. "Giuseppeł" wrote: > > Xilinx newsletter says that the webpack 5.X will be dowlodable from october. > > Ciao > Giuseppe > > "Muthu" <muthu_nano@yahoo.co.in> ha scritto nel messaggio > news:28c66cd3.0209042144.367f0f73@posting.google.com... > > Hi, > > > > Is that ISE5.1i is free downloadable. If so, where can we get it. and > > How to install it.. Here we are using ISE4.1i.. > > > > Thanks in advance. > > > > Best regards, > > Muthu -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46691
> Still seem to be getting 'unsigned 9 does not match type unsigned int > 32' everywhere. The problem is, all my variables are 32 bits except > where I have had to extract the least significant x bits to keep the > compiler happy. > > How does the Handel-C error reporting system actually work? Its very easy : Let's walk through the first error message... (*) mdct.hcc Ln 137, Col 3-28: Type 'unsigned int 9' does not match type 'unsigned int 32' So, the compiler is saying that you are trying to use two quantities which ought to have the same type, but they don't match. Expanding this gives the two quantities it is upset about... (---*) mdct_test.hcc Ln 137, Col 3-28: Type 'unsigned int 9' does not match type 'unsigned int 32' (---*) mdct_test.hcc Ln 137, Col 3-28: Type 'unsigned int 9' does not match type 'unsigned int 32' The program text referred to by both is "mdct_hardware_backward(n)". This is a call to a macro proc that you defined elsewhere. To drill down into the macro to see where the problem lies, expand each of the above lines to give... (---+---*) mdct_test.hcc Ln 894, Col 4-11: Type 'unsigned int 9' does not match type 'unsigned int 32' (---+---*) mdct_test.hcc Ln 894, Col 8-10: Type 'unsigned int 9' does not match type 'unsigned int 32' These refer to some text inside your macro proc definition. The first is "out[oX]" and the second is "oX" (which is part of the first). The compiler is expecting an (unsigned 9) index to use with the array out[ ], but oX is a variable of type (unsigned 32). ------------- I noticed you attempted to define a compile-time constant value in your program : unsigned 32 n = 256; This line defines a variable called n, with type (unsigned 32), which has an initial value of 256 at runtime. Also, since its a variable, it could change value during runtime. At compilation time, its value is unknown. None of this is even close to what you intended! To fix it, do this instead : macro expr n = 256; Or you could do this : #define n 256 See the manual sections on "macro expressions" and the "pre-processor" to understand what these mean. Also, since n has file scope (ie not local), you don't need to pass it around as a macro proc parameter as you have done in a couple of places (see "variable scope" in the manual). Compile-time constants are a Good Thing as they help avoid hardcoding numbers everywhere in your program - They ease understanding and its a trivial one-liner to change the value later. To make it more obvious that this is a constant, there's a widely used convention in C/C++ to use upper case descriptive names for constants. So personally, I would use something like : macro expr NUM_ELEMENTS = 256; You'll need to change the next two lines in your program to signed 32 inp[NUM_ELEMENTS]; signed 32 out[NUM_ELEMENTS]; ...and the index values for both arrays will be 8 bit values, not 9 as you've been using, since they range from 0 to 255 inclusive. You will need to spend more time on correcting the bitwidth issues in your program - This is common when porting C to Handel-C. This hopefully should start you on your way : Good luck! Cheers, SteffanArticle: 46692
I have not been in touch with my disti on this as that is usually a slow process. Anyone know what the current story is on the CoolRunner XCR3384? I see them listed on the disti web sites, but there is nearly no inventory and the prices are way through the roof! The XCR3256XL-12FT256C is "only" $17, but the XCR3384XL-12FT256C is $60!!! This must be the early leadin price. Anyone know what the target price is for 3-5 months out, like in January? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46693
I was wondering what exactly quiescent/static/standby current are (if they are in fact different). I am planning to run an FPGA or CPLD (probably the Xilinx CoolRunnerII) off of a watch battery or two. The design has around four counters and some decoders, and the clock speed will be 32.768 kHz. Most watch batteries seem to be rated at about 50 mAh. The particular CoolRunnerII i have in mind has a quiescent current of 14uA. Does this mean that I will get about 50/.014=3571 hours of FPGA usage with one battery? Or will the actual current drawn be significantly more than the quiescent current? The CoolRunnerII family also claims to have a Static Icc of <100uA at all times. Is the static Icc what I should be looking at? Thanks in advance!Article: 46694
You will be alright with the CoolRunner current consumption. Don't forget that the published specifications in this particular area are usually "sandbagged", which means the parts are usually much better than the spec. The manufacturer inflates the spec, so that he never has to throw away a part for reasons of leakage current. Your challenge is the oscillator, which is a linear circuit and if you are not careful, you might exceed your current budget there. It is easy to drive non-multiplexed LCDs if you put an XOR in the data output and use the backplane voltage ( a ~kHz square wave between ground and Vcc) as the other XOR input. Peter Alfke, Xilinx Applications ====================== John wrote: > I was wondering what exactly quiescent/static/standby current are (if > they are in fact different). > > I am planning to run an FPGA or CPLD (probably the Xilinx > CoolRunnerII) off of a watch battery or two. The design has around > four counters and some decoders, and the clock speed will be 32.768 > kHz. > > Most watch batteries seem to be rated at about 50 mAh. The particular > CoolRunnerII i have in mind has a quiescent current of 14uA. Does this > mean that I will get about 50/.014=3571 hours of FPGA usage with one > battery? Or will the actual current drawn be significantly more than > the quiescent current? > > The CoolRunnerII family also claims to have a Static Icc of <100uA at > all times. Is the static Icc what I should be looking at? > > Thanks in advance!Article: 46695
John wrote: > > I was wondering what exactly quiescent/static/standby current are (if > they are in fact different). > > I am planning to run an FPGA or CPLD (probably the Xilinx > CoolRunnerII) off of a watch battery or two. The design has around > four counters and some decoders, and the clock speed will be 32.768 > kHz. > > Most watch batteries seem to be rated at about 50 mAh. The particular > CoolRunnerII i have in mind has a quiescent current of 14uA. Does this > mean that I will get about 50/.014=3571 hours of FPGA usage with one > battery? Or will the actual current drawn be significantly more than > the quiescent current? > > The CoolRunnerII family also claims to have a Static Icc of <100uA at > all times. Is the static Icc what I should be looking at? Static Icc and quiescent current are the same - both are non-clocked. The 100uA is a temp and production spread MAX, and the 14uA is a room temperature typical. You will need to also add to your power budget : - DC regulator for the core voltage ( and better than 5% regulation ) - Dynamic current mA/MHz ( eg at 73.5uA/MHz 32.768 -> 2.4uA ) - Load dynamic current - IP slew currents ( do NOT feed a 32Khz sine osc into the PLD ! ) IP buffers have appreciable linear currents, if not driven with fast edged/full supply waveforms. - Oscillator currents, plus Osc buffer/squarer currents ie all this indicates a 'build and measure' approach :) You could also look at the ATF1502ASVL from Atmel - we have measured sub 5uA Static-Icc on these. - jgArticle: 46696
Dr. Andy Nisbet wrote > Try looking into STREAMS-C compiler work ... > http://rcc.lanl.gov/Tools/Streams-C/ > > They have a freely downloadable C->VHDL compiler built on top of the > SUIF infrastructure that is also freely available. CSP, just like Handel-C :-)Article: 46697
rickman wrote: <snip> > I can understand Altera (or anyone else) wanting to protect their IP. > In fact, I think Altera makes the IP available with no royalties because > the idea is that you are paying for the royalty when you buy their chips > to put the design in. > > But they certainly don't have the same issue with the bitstream. I > understand that the court has ruled that ClearLogic must cease making > these parts. But as I said, I would expect to have full rights to my > own design. I am surprised that running it through Altera tools would > limit my rights. <snip> You absolutely have rights to your own design. But the bitstream isn't your design - it's the digested, processed, mapped, placed and routed version of your design. If Altera, Xilinx, et. al. had the ability to lose silicon revenue to the likes of ClearLogic, would they have the same motivation to improve the tools to the extent that they do? While I still don't believe either of those major brands have a tool suite that gets us to finished high speed or high density designs without significant hurdles, the tools haven't lost (significant) ground to the silicon. Your verilog code, your VHDL... it's all yours, even if you created it with their editors. The getting your design into their parts is what's proprietary. This is of course only a counter viewpoint to the "everything I produce is mine" view and I don't feel strongly on the issue. I'm just giving a little perspective to the less-than-clear situation from another user's standpoint.Article: 46698
Paul,
The original reply was to clarify two points, which may have been implied in
Prager's LINUX related post ,for whoever reads it :
1. Although Praeger tried using the Quartus II Windows product on Linux
using WINE, there is a full featured version of Quartus II 2.1 Linux which
runs natively on LINUX without the WINE layer.
2. That there is a complete Programmable Logic design flow for synthesis,
place and route and simulation tools running as Native Linux solutions using
tools from Altera and EDA vendors.
Having said that,
Could you clarify your statement "I really have given the native Quartus
2 synthesiser lots of outings" by specifying the version of Quartus II was
used ? The reply to Prager referred to Quartus II 2.1, and maybe you could
share your results for the quality of the HDL processing for Quartus II 2.1,
for your unmodified design with GENERICS.
Regards,
-ds
"Paul Baxter" <pauljnospambaxter@hotnospammail.com> wrote in message
news:3d770cbc$0$1285$cc9e4d1f@news.dial.pipex.com...
>
> "ds" <nospam@cwix.com> wrote in message
> news:O3yd9.82$WK.23254185@newssvr17.news.prodigy.com...
> > If a version of Leonardo is not available on Linux, Quartus II 2.1 on
all
> > platforms (Windows, Linux, Solaris, HP) has a much improved and very
> robust
> > HDL (VHDL and Verilog) extractor and synthesizer. ModelTech sells a
> > Modelsim simulator that works on Linux.
>
> Can we just get to the bottom of this claim. I really have given the
native
> Quartus 2 synthesiser lots of outings as the claim for improved synthesis
> keeps coming in.
>
> Lets ask some specifics:
>
> Does it now support generics fully (not just in megafunctions)?
>
> Has the parser been heavily updated such that it doesn't CRASH Quartus 2
> when it encounters certain syntax errors?
>
> Have you benchmarked typical designs (say a set of openly available cores
> would be nice) to backup these statements?
>
>
> And finally please can Altera employees PLEASE clearly state their name
and
> some sort of title associated with their company e.g. John Doe , Altera
FAE
> etc.
>
> Regards
>
> Paul Baxter
>
> PS Currently my design synthesises 30% smaller and 35% faster with
Leonardo
> (and thats after some painful conversion of generics back to hardwired
> constants for Quartus.
>
>
Article: 46699Modular design is a separate software option sold by Xilinx (I think it costs $995). If you want to use the modular design option in Synplify Pro, you should possess a copy of the modular design from Xilinx, apart from your ISE 4.x copy. Synplicity has an appnote on Modular Design flow - http://www.synplicity.com/literature/pdf/synmodflo.pdf but I suggest you also read Modular Design flow with Synplicity's Amplify to make things clearer http://www.synplicity.com/literature/amplify/amp_mod_des_app_note.pdf --Neeraj "Muthu" <muthu_nano@yahoo.co.in> wrote in message news:28c66cd3.0209050509.19fe0054@posting.google.com... > Hi, > > Basically the Modular design approach is to split a Big design in to > smallpieces and do the Backend design flow. > > "Synplify_pro" synthesis tool has a switch as 'Modular Design'. How > the synthesis tool will split the entire design. and What change will > be there in PAR. > > Is it possible to do Modular desing with the ISE4.1i ? > > I heard that, "modular design" is seperate software from xilinx... > > is that so? > > Thanks in advance. > > Best regards, > Muthu
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