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> Since JAM sometimes works, and it always works under MAXPLUS, it
> sounds like a timing problem.
>
> How did you program the timing loop? I believe this is something you
> need to port because every target is different.
>
> You might try slowing down the timing loop by half to see if it works
> any better.
>
> Alan Nishioka
> alann@accom.com
Hello!
My first attempt to solve that problem was to slowing down the timing
loop,too. There is one funktion which should be port to every target.
Here it is:
void jam_delay(long microseconds)
{
// microseconds = microseconds*5; /* slow down loop */
if (microseconds >= 10000)
usleep(microseconds);
else
ioctl(ISP_fd, DELAY_TWO, (unsigned long)microseconds);
}
As you can see if've tryed to slow the delayloop down by 5, but
without effect. I've used "usleep" for all delays above 10ms and i've
wrote a kernel-driver module to realize all delays under 10ms with
"udelay" in kernel-space, because the resolution of usleep is too bad
for short times.
While i was searching for the bug, i measured how often this jam_delay
function is called in one programming cyclus, because i thougt every
time i get a success programming the device the number of calls is the
same. BUT then i was surprised because when i program my devices 3
times consecutively with getting a success the number of calls of this
function was different. So I came to the conclusion that the
JAM-Player is doing something little different each time it is
started.
But now i'm running out of ideas, because I don't know where i could
look to trace this error.
Have you any idea what i could do??
> > yours
> > Schachinger Martin
> > schachinger@decomsys.com
> > VIENNA - AUSTRIA
Article: 46226The UK's Educational ECAD User Group is running its annual workshop as usual in September. The EEUG Workshop will be hosted at the Buckinghamshire Chilterns University College (BCUC), Chalfont St Giles Campus, UK on the 3rd and 4th of September 2002. The topic for the workshop is "Resarch, Application and Future Prospects in Educational ECAD of Field Programmable Arrays". Full information is available at the EEUG website <http://www.eeug.org.uk>, including a registration form and provisional programme. If you would like to attend the workshop, please email Richard Walters (r.walters@unl.ac.uk) for further regsitration information. -- Ian Grout Ian.Grout@ul.ie Department of Electronic & Computer Engineering, University of Limerick, Ireland Posted on behalf of the EEUG committeeArticle: 46227
maimuna wrote: > > thanx for the reply. but the case statment will not work since this > also will be lenthier. i want is there any option like table or > anything else which will reduce the design statements. if there is no > other option then i have to write code with if..else statement which > will be too longer. > plese help me out Is this homework ? ( sure looks like it ) Perhaps your tutor is looking for you to scan the logic, and find the overlaping / redundant instances, and so simplify it that way. Or, he may give more marks to someone who can extract the logic, and completely re-write, to create a much smaller expression ? - jgArticle: 46228
Here ist a quote from the Phillips Website that think is funny: "Purchase of Philips I²C components conveys a license under the Philips I²C patent to use the components of the I²C system" Make sure that the next time you purchase a patented pencil sharpener, make sure that the license to use it is included in the price. Here is what phillips believes: http://www.itworld.com/Man/2687/IDG011030philips/ Her ist Patent 4,689,740 http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=/netahtml/search-bool.html&r=1&f=G&l=50&co1=AND&d=pall&s1=''4,689,740''.WKU.&OS=PN/Article: 46229
I am interfacing virtex to a DSP over io port. The read process is as follows if(oe) then data=output(conv_integer(address_input)) else data=z This is fine in behavioral simulation(expected) but when I do a PR simulation, I see some of the data lines going to X before reaching the final value. How can I eliminate this. Also will this cause any problem in the hardware. Any help is appreciated AnjanArticle: 46230
Hi! > I need to use some Xilinx primitives in my VHDL, and they seem to be in > different libraries for use with ModelSim and Synplify. Here's what I have > so far... I always used library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; --pragma translate_off library UNISIM; use UNISIM.vcomponents.all; --pragma translate_on ... As far as I remember this worked for both programs. Regards, PatrickArticle: 46231
"Anjan" <anjanr@yahoo.com> wrote in message news:5a5faf7b.0208220112.6f795975@posting.google.com... > I am interfacing virtex to a DSP over io port. The read process is as > follows > > if(oe) then > data=output(conv_integer(address_input)) > else > data=z > > > This is fine in behavioral simulation(expected) but when I do a PR > simulation, I see some of the data lines going to X before reaching > the final value. How can I eliminate this. Also will this cause any > problem in the hardware. Any help is appreciated I guess it's a timing problem. If the tristate buffer is implemented in the pin and the OE signal is coming from the core, there is a long propagation delay from OE to the buffer. Hence there may be a difference between when OE changes and when the data changes. If you can register OE, then you can synchronise OE in the pin, as in Virtex there is a flip-flop in the pin for the tristate control line as well as for the data. You would need to describe your "if" statement in a clocked process to get that effect, and also make sure the P & R actually used the flip-flops in the pad. Alternatively, you should add a constraint to the P&R tools on the time from OE changing to the pin output to make it as small as possible. Regarding problems, you will get transient current if both the virtex and the DSP drive the bus at the same time - I don't know if this will do any permanent damage to the devices. regards AlanArticle: 46232
Hello all: I want to make a develop board for Xilinx's FPGA(SP-II). Where can get s simple design use these chips? I just want to design a most simple develop board for our lab( there are some LEDs and download/JTAG interface in this board).Article: 46233
"Deli Geng (David)" wrote: > > Hi, there, > > As you know, Phillips hold the patent of I2C bus. But I also found somewhere > said many of these patents had expired. However I still wondered if I design > an I2C interface on my FPGA/CPLD chip and use this chip only in my system, > do I have to buy their license? The designed FPGA/CPLD chip itself will not > be a commercial product but this system will be. > > Thanks a lot. > > David David, I am not working in the right department of Philips for this, but I asked a bit around and this seems to be the consent: * If your design contains a Philips chip with I2C, you are allowed to use the protocol and that also covers designing your own interfaces. * If you use an I2C device of another Manufacturer, it depends whether they have got the license. A good indicator is the use of the I2C logo in the datasheets. Some manufacturers implement a 2-wire bus which is I2C but they don't mention it. Using those devices may not automatically give you a license to use the bus for other things. * If you design a new device with I2C capabilities (like a new micro), you probably need a license. Some people seem to get away with it, by not calling it I2C, but they probably infringe Philips' rights one way or other. Please note that this is not an official statement. I am not authorized to speak for the company and the above may be completely wrong. If you want a legally binding statement, please contact Philips Intellectual Property & Standards. Kind regards, IwoArticle: 46234
Welcome back Peter, nice to have your expertise on-line again. Phil -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 46235
And it is portable to another synthesis tool ;-)
Patrick Loschmidt wrote:
> Hi!
>
> > I need to use some Xilinx primitives in my VHDL, and they seem to be in
> > different libraries for use with ModelSim and Synplify. Here's what I have
> > so far...
>
> I always used
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_unsigned.all;
>
> --pragma translate_off
> library UNISIM;
> use UNISIM.vcomponents.all;
> --pragma translate_on
>
> ...
>
> As far as I remember this worked for both programs.
>
> Regards,
> Patrick
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46236"Falk Brunner" <Falk.Brunner@gmx.de> ¼¶¼g©ó¶l¥ó news:ajrhvo$1dr9p3$1@ID-84877.news.dfncis.de... > "Ramakrishnan" <rxv20@po.cwru.edu> schrieb im Newsbeitrag > news:15cf85fc.0208190913.50dc29b4@posting.google.com... > > Hi, > > Can someone tell me whether it is possible to dynamically > > reconfigure the contents of the memory in FPGA ,without connecting to > > a external PROM or a host computer ?. > > So where will you store the configuration data? You can also use a uC + > FLASH. > > -- > MfG > Falk Can someone tell me Where can find the solution information of configuring FPGA with uC and FLASH ? FPGA (Spartan-II) + uC (8051) +Flash Thanks!Article: 46237
"Ray Liang" <lean26@ms54.hinet.net> schrieb im Newsbeitrag news:ak30rl$9eb@netnews.hinet.net... > > Can someone tell me > Where can find the solution information of configuring FPGA with uC and > FLASH ? > FPGA (Spartan-II) + uC (8051) +Flash Have a look at the Spartan-II datasheets. Serial slave configuration (which is the above scheme) is easy. You just need PROGRAMM, CCLK and DIN connected to 3 uC IO pins, write some lines of code, bitbang the bits into the fpga, apply some additional start clock to the FPGA, you'r done. -- MfG FalkArticle: 46238
> If you want a legally binding statement, > please contact Philips Intellectual Property & Standards. Thank you, Iwo, for taking the initiative to provide some information. Do you have the contact information for Phillips Intellectual Property & Standards? Regards, AustinArticle: 46239
"dross" <zjuzhou@yahoo.com.cn> schrieb im Newsbeitrag news:183113ed.0208220412.b2723e1@posting.google.com... > Hello all: > > I want to make a develop board for Xilinx's FPGA(SP-II). > Where can get s simple design use these chips? Why not buy one. They are cheap and ready to use. www.nuhorizon.com www.burched.com -- MfG FalkArticle: 46240
"Michael Schmidl" <mike@sysoc.de> schrieb im Newsbeitrag news:d8d31538.0208212225.54d2668b@posting.google.com... > Next try was to connect the "clock-tree" signals to pads of the XILINX > and to connect the in- and outputs within the testbench. VOILA, it > works! Now the ISE places the clock inputs as exspected to GCK pins > and uses BUFGPs to drive the "clock tree" clocking the logic connected > to it! Instanciate a global clock buffer, place the MUX in front of it, so that after the clock buffer there is just a normal looking clock signal. -- MfG FalkArticle: 46241
Hi, Is there a way i could download two bit streams to a single Xilinx FPGA board when starting up ?. and also is it possible for a controller to switch between the two bit streams while in operation?. Can someone give me more insight on this . Thanks, Ram.Article: 46242
Ray Liang wrote: > > Can someone tell me > Where can find the solution information of configuring FPGA with uC and > FLASH ? > FPGA (Spartan-II) + uC (8051) +Flash Famous XAPP058 (interesting is also XAPPP079, XAPP098, XAPP137, XAPP178, XAPP501)Article: 46243
--------------DCC987C896626121ACFBA526 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Agreeed, but to make it even simpler click on http://www.xilinx.com/xapp/xapp058.pdf http://www.xilinx.com/xapp/xapp079.pdf http://www.xilinx.com/xapp/xapp098.pdf http://www.xilinx.com/xapp/xapp137.pdf http://www.xilinx.com/xapp/xapp178.pdf http://www.xilinx.com/xapp/xapp501.pdf Peter Alfke ============================= emanuel stiebler wrote: > Ray Liang wrote: > > > > Can someone tell me > > Where can find the solution information of configuring FPGA with uC and > > FLASH ? > > FPGA (Spartan-II) + uC (8051) +Flash > > Famous XAPP058 > (interesting is also XAPPP079, XAPP098, XAPP137, XAPP178, XAPP501)Article: 46244
Is any of the three clocks enough faster than the other two that you can either run it through a register clocked by the fast clock and then use it as an internally generated clock, or design a digital edge detector clocked by the fast clock, use an instance for each slow clock input, and then use the result as a clock enable for everything previously clocked by the slow clocks but actually use the fast clock to drive all three clock inputs of the IP? If not, wait for someone more familiar with those FPGAs to tell you whether they can put clock inputs on non-GCK pins and then use them to drive clock buffers normally used only for internally generated clocks. "Michael Schmidl" <mike@sysoc.de> wrote in message news:d8d31538.0208212225.54d2668b@posting.google.com... > I have a customer using a XCV2000 and XCV800 where I have to integrate > an IP core. > > The PCB is already fixed so I can not change the pinning. This PCB has > only one GCK connected and all other pins available are normal IOs - > the other 3 GCKs are not connected and not accessible due to the ball > grid housing. > > The IP I try to integrate has three "clock inputs". One - connected to > the GCK2 - is used to clock the host interface to the controlling > processor. The other two "clock inputs" - connected to normal IOs - > are used to clock data streams in and out of the XILINX and are both > generated by an external component (it is a Ethernet IP core I am > talking about and the two clocks are the MII interface clocks > generated by an external PHY chip). > > The next odd thing is that the CORE I have to integrate uses a logic > to multiplex the two PHY clock inputs and brings this multiplexed > clocks to an OUTPUT wire of the core (they call this the > PRE-CLOCK-TREE signals). The actual clock driving all logic inside the > core is an INPUT wire of the core (called the POST-CLOCK-TREE > signals). So they are producing something like a CLOCKTREE (the core > is originally intended for ASIC or GATEARRAY designs). > > I tried to connect the pre- and post-clock-tree signal at my top level > just with a wire and use the same signal for driving my logic which > must run on the same clocks as the core. > > If I use ISE 4.2.03i/XST to produce a gatelevel model, it does not > work! I get strange misbehaviours that look like HOLD violations > between flip flops driven by the same clock. > > Before I generated the gatelevel model I used the CONSTRAINT EDITOR to > define the different clocks for the nodes detected as clocks. The > place and route tells me that these constraints have been meet and the > STA shows the some. But the gatelevel does not work. > > Next try was to connect the "clock-tree" signals to pads of the XILINX > and to connect the in- and outputs within the testbench. VOILA, it > works! Now the ISE places the clock inputs as exspected to GCK pins > and uses BUFGPs to drive the "clock tree" clocking the logic connected > to it! > > But unfortunatly I can not do this in reality. The GCKs are not > availabel so I have to find a solution for the "combinatorial clock" > to get a working design. > > ANY IDEA??? > > Any help is appreciated. > > With kind regards > _______________________________________ > Dipl.-Ing.(FH) Michael Schmidl > Prochintalstr. 5 > D-80993 München > Germany > Tel 089 / 143 20658 > Mobil 0179 / 673 0851 > Fax 089 / 2443 73489 > PGP-Key: www.mschmidl.de/mschmidl.asc > Info: www.mschmidl.deArticle: 46245
"Ramakrishnan" <rxv20@po.cwru.edu> schrieb im Newsbeitrag news:15cf85fc.0208220811.101ec55c@posting.google.com... > Hi, > Is there a way i could download two bit streams to a single Xilinx > FPGA board when starting up ?. and also is it possible for a > controller to switch between the two bit streams while in operation?. Sure. just store the two bitstreams in FLASH/RAM, and choose (and download) the appropiate to the FPGA. -- MfG FalkArticle: 46246
noArticle: 46247
Fyi that is www.nuhorizons.comArticle: 46248
Falk Brunner <Falk.Brunner@gmx.de> wrote: > Why not buy one. They are cheap and ready to use. > www.nuhorizon.com > www.burched.com And the XESS boards are EXCELLENT: www.xess.com I own both an XS-40 and XSA-100 Take care, -Chris -- /> Christopher Cole <\ <\ << Cole Design and Development \\ email: cole@coledd.com \\ \\ Computer Networking & Embedded Electronics \\ web: http://coledd.com >> \> \> </Article: 46249
"No" is the correct answer. The FPGA can only hold one configuration at any time. The newer Virtex devices allow partial configuration, i.e. you can, if you want, "patch up" the existing configuration by downloading only the "frames" that need changing. This does offer interesting new alternatives, but the basic answer to your question is still "No". And don't ask the other manufacturers, most of them cannot even do the partial reconfiguration that Virtex offers. ( I do not know the Atmel devices well enough to make this statement more absolut, but they definitely cannot hold multiple configurations). The question has some relevance, but any attempt in this direction always fizzled out for lack of market acceptance ( read: poor price/performance ratio).. Peter Alfke, Xilinx Applications Engineering ============================================= Ramakrishnan wrote: > Hi, > Is there a way i could download two bit streams to a single Xilinx > FPGA board when starting up ?. and also is it possible for a > controller to switch between the two bit streams while in operation?. > > Can someone give me more insight on this . > > Thanks, > > Ram.
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