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Hi, You asked this same question on 07/22/2002 What's wrong with the answers you got then? SH7 On Mon, 12 Aug 2002 11:32:31 +0800, "Reala" <manfield.chow@scoreconcept.com> wrote: >Hi, > >I wrote a verilog code. Then, I ran Modelsim to verify the design. >If I implement the design by Altera, I can use LeonardaSpectrum for >synthesis. >However, i want to implement the design by ASIC. What >information/software/library needed for this approach? Thank you. > >Reala > > > > >Article: 45951
Hello John, Thank you for replying :) Glad that there is someone who is trying to answer my query!! I still have my issues though!! Well, XPower does not seem to have the following good traits: a). It cannot recompute the node transition frequencies (that it has procured from a .vcd file) when I change the clocking frequency in the Xpowwr fields. b). It does not seem to have the capability of computing the activity factor of a gated clock. The gated clock is assigned the same toggle frequency as that of the input clock !! I have started manually computing the power dissipation based on the load capacitances reported by it. Thanks VikramArticle: 45952
Unless the original poster is doing a post P&R simulation, the
simulation should start in less than a few minutes even if he is using
ModelSim XE-Starter.
I will suspect there is something wrong with the design and/or the
simulation code.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
VhdlCohen wrote:
>
> >ModelSim (which came with the WebPack) does not produce any result or error
> >message. It just stands there consuming CPU.
> I understood that ModelSim that comes with WebPack is limited in the size of
> the program. If the program is too large, ModelSim has built-in stops to slow
> it down.
> Nothing in life is FREE!
> Ben Cohen
Article: 45953For experimental purposes, we are trying to synthesize a design with Symplify so that it does NOT use register internal resets and clock enables on the Virtex architecture. Any hints on how to do this? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 45954
I am not sure if you omitted when you posted the code, but I
don't see any "reg" for clk_100, clk_sd, reset_local, din, etc.
Also, you may want to synchronize the time to a positive edge of a
clock, if that's possible.
For example,
@ (posedge clk_1)
din <= #1 1'b1; // generate some input data to a parallel-serial
converter
You should use non-blocking statements instead of blocking statements
whenever possible, I think. (Not always possible. Sometimes, you need to
use blocking statements to stop the parallel execution signal
assignments.)
You may also want to repost this question at news:comp.lang.verilog if
the answers you got here aren't satisfactory.
You said you are using Spartan-IIE, but I hope you are aware
that Spartan-IIE isn't 5V tolerant. (You need an external resistor or a
voltage conversion chip to interface with a 5V signal. Spartan-II is 5V
tolerant, so you don't need them.)
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
"Børge Strand" wrote:
>
> Hi all,
>
> I'm trying to simulate a double handshake protocol in Verilog. My
> synthesizeable code is supposed to run in a SpartanIIe, the testbench
> simulates a PC's parallel port programmed in Linux.
>
> ModelSim (which came with the WebPack) does not produce any result or error
> message. It just stands there consuming CPU. The code worked when I
> simulated the PC being the master. But it fail when I simulate the PC
> answering the handshake.
>
> What happens is that the synthesizeable code writes a data word, sets
> "transmitting" high, waits for "pc_read" to get high, sets "transmitting"
> low, waits for "pc_read" to get low, then sends a new data word. So the
> below code that simulates the PC waits for "transmitting == 1", sets
> "pc_read" high, waits for "transmitting == 0", sets "pc_read" low.
>
>
> Regards,
>
> Børge
Article: 45955
Nicholas C. Weaver wrote:
> For experimental purposes, we are trying to synthesize a design with
> Symplify so that it does NOT use register internal resets and clock
> enables on the Virtex architecture. Any hints on how to do this?
-- For VHDL I would do something like:
architecture synth of some_entity is
begin
no_rst : process (clk)
begin
if rising_edge(clk) then
-- sequential statements here
end if;
end process no_rst;
end architecture synth;
-- Synplify will tie off the unused inputs.
-- Mike Treseler
Article: 45956
To disable use of the clock enables use the syn_useenables attribute, set it
to false.
For the resets, use a global reset signal to tie up the async clear inputs and
then drive that signal with a black-boxed instantiated ROC primitive
ROC component declaration
attribute syn_black_box of ROC:component is true;
attribute syn_useenables of flipflop_Q:signal is false;
begin
POC: ROC(0=> global_reset);
process(clk,global_reset)
begin
if global_reset='1' then
flipflop_Q<='0';
elsif rising_edge(clk) then
flipflop_Q<=flip_flop_d
"Nicholas C. Weaver" wrote:
> For experimental purposes, we are trying to synthesize a design with
> Symplify so that it does NOT use register internal resets and clock
> enables on the Virtex architecture. Any hints on how to do this?
> --
> Nicholas C. Weaver nweaver@cs.berkeley.edu
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45957Hi, On a Virtex-II, we have a LVPECL IBUFGDS and we need to detect if there is a clock or not at the pins. If no clock is present, both inputs are tied to ground on the PCB (2 flavours of PCB). Looking at the doc, the output of the IBUFGDS is 'X' when both inputs are at '0'. Is the output of the IBUFGDS stable to either '0' or '1' or can there be transitions that would cause the detection circuit (SRL16) to fail ?? Regards, YanickArticle: 45958
Hi, I really didn't understand what you meant in your post. Actually the number of memories for each and every application varies in my architecture, for example bandpass filter implementation required 12 memories of 4 elememts whereas cosine filter needed only 10 memories. So every time a new application is to be implemented, the whole architecture would have to some how be reset to reflect the exact number of memories. Thanks, Ram. "reply in the newsgroup" <deepfry.a.spammer.today@abuse.org> wrote in message news:<aj8mlp$i87$1@slb7.atl.mindspring.net>... > "Ramakrishnan" <rxv20@po.cwru.edu> wrote in message > news:15cf85fc.0208120735.1884e326@posting.google.com... > > Hi, > > I have a few questions with regard to Xilinx 4000 series FPGA. > > > [deleted] > > The problem i think would like in the fact that some of the > > applications that i choose to implement would use fewer memories in my > > VHDL architecture than others. So how would i be able to overcome this > > problem. > > > Then why not create a file for each memory not used in all the tests, that > loads this memory with random data, and use the resulting files to load any > memory not used in the current test so that all the memories end up > loaded?Article: 45959
Thanks. We'll try it and see how it works. Symplify is inserting the CEs in the mapping phase, since they appear in the EDIF but not in the internal structural view. Worst case, a little EDIF munging is in order. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 45960
Thanks. Although this is what we are already doing, the CEs are being added/inferred by symplify's mapping process. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 45961
billabloke@yahoo.com (Bill Diehls) wrote in message news:<4855d4d8.0208100958.304903e3@posting.google.com>... > There is an interesting product for the Gameboy that uses a Xilinx > Spartan FPGA. It costs $129 for the development kit and it looks like > a lot of fun to experiment with. It would be decidedly more fun if it didn't use an obsolete SpartanXL part that is not supported by WebPack. Achim.Article: 45962
http://www.xilinx.com/esp/technologies/wireless_networks/bluetooth.htm Sleep Mode wrote: > > Hi there! > > I am involved with a project regarding bluetooth protocol stack and I want > to move protocols of this stack to hardware (FPGA or even mController) -till > now I only have some very very complicated implementations in C++. > I am looking for references for such a task since I have little experience > on the subject yet (how to transfer a protocol layer effectively in vhdl for > instance). I also don't seem to find very explanatory details of the > interface provided by the bluetooth stack so as to interconnect it correctly > with hardware. > If you have any knowledge of such hardware, sample codes or references > please please tell me! > > HW rulez! :-)Article: 45963
Then you'll need a separate simulation for each configuation. I was assuming that you were using only one configuration, but not initializing all the sections in tests that weren't using them. "Ramakrishnan" <rxv20@po.cwru.edu> wrote in message news:15cf85fc.0208121403.b469915@posting.google.com... > Hi, > I really didn't understand what you meant in your post. Actually > the number of memories for each and every application varies in my > architecture, for example bandpass filter implementation required 12 > memories of 4 elememts whereas cosine filter needed only 10 memories. > > So every time a new application is to be implemented, the whole > architecture would have to some how be reset to reflect the exact > number of memories. > > Thanks, > > Ram. > > "reply in the newsgroup" <deepfry.a.spammer.today@abuse.org> wrote in message news:<aj8mlp$i87$1@slb7.atl.mindspring.net>... > > "Ramakrishnan" <rxv20@po.cwru.edu> wrote in message > > news:15cf85fc.0208120735.1884e326@posting.google.com... > > > Hi, > > > I have a few questions with regard to Xilinx 4000 series FPGA. > > > > > [deleted] > > > The problem i think would like in the fact that some of the > > > applications that i choose to implement would use fewer memories in my > > > VHDL architecture than others. So how would i be able to overcome this > > > problem. > > > > > Then why not create a file for each memory not used in all the tests, that > > loads this memory with random data, and use the resulting files to load any > > memory not used in the current test so that all the memories end up > > loaded?Article: 45964
Actually, it is a frequency counter. The first counter bank is counting a reference frequency, the second an unknown frequency all controled by a gate time of 1 kHz. I'm looking to implement all of the math in the FPGA rather than having to rely on an external processor, etc. I'll found a couple of helpful pages on the web, but nothing too in depth. Thanks for the tips, I've got a starting point at least. Jason "Ray Andraka" <ray@andraka.com> wrote in message news:3D544304.6A35CD03@andraka.com... > I haven't had the time to look at this too closely. My initial thought is that > you may not need to do an explicit divide since essentially you are looking for > the ratio of two counts. Look at frequency counters to get a better idea of how > this might be useful to you. > > Now, if you still want to do a real divide, then floating point actually makes > your job easier. FIrst step is to normalize your dividend and divisor, then you > can dispense with the extra precision in the resulting significand. For small > precisions, a look-up table can be used with quite good results. We did some > division in video where the data is only 8 bits and normalizing it first got use > down to a small LUT for the divide...most of the information is in the exponent > which is simply subtracted. If your 5digits are decimal digits, you'll need a > bit more for the divide on the significands. Since your data rate is low, and > the counts are presumably unsigned, you can get away with an iterative restoring > divider, which is little more than a subtractor, compare (another subtract) and > a state machine. Spend the $40 or so and pick up Isreal Koren's Computer > Arithmetic (available from the Amazon bookstore on my website, and if you order > there I get a small referral fee that helps to keep up the website). He goes > into considerable detail on the algorithms for division and square root, both > for fast parallel and sequential solutions. > > Finally, what you are looking for is a hardware solution to do the division: > that exists in many forms and the fpga is very capable of doing it much faster > than the 1Khz rate you need. The divider will occupy a small area. The > hardware solution has little to do with the VHDL. Keep in mind VHDL should be > used to express hardware. If you are to be successful using it, you will have > to visualize the hardware first then code to produce the structure you > visualize. > > Best of luck, and have fun learning! > > Jason Berringer wrote: > > > Hello FPGA and VHDL experts, > > > > I require a little assistance. I have done some searches and read through a > > few texts to see if the topic is covered and can't find the information that > > I'm looking for. I have two counter banks which are counting away. At 1 kHz > > I take the counts in both of the banks, generate an interrupt and pass off > > the values to a CPU where the floating point division of the counts BANK A > > divided by BANK B occurs along with some fancy DSP filtering. I use an ISA > > interface for the data transfer. What I'm looking to do is move the division > > inside of the FPGA. Can anyone point out a couple of examples so I can learn > > how to do this. I'm looking for floating point division with at least 5 > > digits of precision in my result. Then I can perform some fancy DSP > > filtering inside of the FPGA. > > Note, the counter banks are 24 bits each. > > > > Questions: > > > > 1. Can this be done as a VHDL module or do I have to embed a CPU type core > > for the division? > > 2. Does anyone know of an app note that might cover, and provide a small > > example of this type of VHDl code? > > 3. Am I crazy to try this (ie should I just let the CPU do the work)? > > > > If my question seems rather niave I appologize, I've only been working with > > VHDL and FPGAs for about a year so my knowledge is somewhat limited (so go > > easy with the shots please!). Any help is greatly appreciated. > > > > Thanks > > > > Jason Berringer > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 45965
firstly, don't say "program". it is not program, but "circuit" keep this in mind, you'll find that is not a question of VHDL but a problem of thougt Best Regards, Daryl "maimuna" <maimuna_a@nrsa.gov.in> wrote in message news:13bf39b3.0208120145.6bcf6c0d@posting.google.com... > the width of the array which i have used in my program changes with some inputs. > is there any way to set the width of the array according to the inputs. > if so please tell meArticle: 45966
In that case, you merely clock one counter with your unknown frequency, and a
second counter with your reference clock. Each time the reference counter rolls
over (pick the terminal count to be a convenient interval so that you don't have
to do any math), it produces a gate signal, which must be resynchronized to the
measurement clock domain. There, it synchronously copies the current
measurement count to a latch and resets the counter. The longer your measurement
interval (determined by the length of your gate counter), the more accurate your
measurement.
It fits in a very small number of CLBs. It basically consists of a pair of
counters, a synchronizer to get the gate signal neatly into the measurement
clock domain, and a register.
Jason Berringer wrote:
> Actually, it is a frequency counter. The first counter bank is counting a
> reference frequency, the second an unknown frequency all controled by a gate
> time of 1 kHz. I'm looking to implement all of the math in the FPGA rather
> than having to rely on an external processor, etc. I'll found a couple of
> helpful pages on the web, but nothing too in depth. Thanks for the tips,
> I've got a starting point at least.
>
> Jason
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3D544304.6A35CD03@andraka.com...
> > I haven't had the time to look at this too closely. My initial thought is
> that
> > you may not need to do an explicit divide since essentially you are
> looking for
> > the ratio of two counts. Look at frequency counters to get a better idea
> of how
> > this might be useful to you.
> >
> > Now, if you still want to do a real divide, then floating point actually
> makes
> > your job easier. FIrst step is to normalize your dividend and divisor,
> then you
> > can dispense with the extra precision in the resulting significand. For
> small
> > precisions, a look-up table can be used with quite good results. We did
> some
> > division in video where the data is only 8 bits and normalizing it first
> got use
> > down to a small LUT for the divide...most of the information is in the
> exponent
> > which is simply subtracted. If your 5digits are decimal digits, you'll
> need a
> > bit more for the divide on the significands. Since your data rate is low,
> and
> > the counts are presumably unsigned, you can get away with an iterative
> restoring
> > divider, which is little more than a subtractor, compare (another
> subtract) and
> > a state machine. Spend the $40 or so and pick up Isreal Koren's Computer
> > Arithmetic (available from the Amazon bookstore on my website, and if you
> order
> > there I get a small referral fee that helps to keep up the website). He
> goes
> > into considerable detail on the algorithms for division and square root,
> both
> > for fast parallel and sequential solutions.
> >
> > Finally, what you are looking for is a hardware solution to do the
> division:
> > that exists in many forms and the fpga is very capable of doing it much
> faster
> > than the 1Khz rate you need. The divider will occupy a small area. The
> > hardware solution has little to do with the VHDL. Keep in mind VHDL
> should be
> > used to express hardware. If you are to be successful using it, you will
> have
> > to visualize the hardware first then code to produce the structure you
> > visualize.
> >
> > Best of luck, and have fun learning!
> >
> > Jason Berringer wrote:
> >
> > > Hello FPGA and VHDL experts,
> > >
> > > I require a little assistance. I have done some searches and read
> through a
> > > few texts to see if the topic is covered and can't find the information
> that
> > > I'm looking for. I have two counter banks which are counting away. At 1
> kHz
> > > I take the counts in both of the banks, generate an interrupt and pass
> off
> > > the values to a CPU where the floating point division of the counts BANK
> A
> > > divided by BANK B occurs along with some fancy DSP filtering. I use an
> ISA
> > > interface for the data transfer. What I'm looking to do is move the
> division
> > > inside of the FPGA. Can anyone point out a couple of examples so I can
> learn
> > > how to do this. I'm looking for floating point division with at least 5
> > > digits of precision in my result. Then I can perform some fancy DSP
> > > filtering inside of the FPGA.
> > > Note, the counter banks are 24 bits each.
> > >
> > > Questions:
> > >
> > > 1. Can this be done as a VHDL module or do I have to embed a CPU type
> core
> > > for the division?
> > > 2. Does anyone know of an app note that might cover, and provide a small
> > > example of this type of VHDl code?
> > > 3. Am I crazy to try this (ie should I just let the CPU do the work)?
> > >
> > > If my question seems rather niave I appologize, I've only been working
> with
> > > VHDL and FPGAs for about a year so my knowledge is somewhat limited (so
> go
> > > easy with the shots please!). Any help is greatly appreciated.
> > >
> > > Thanks
> > >
> > > Jason Berringer
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45967
Yeah, it does that. If you look in the technology mapped view you'll see that
it used the ce's, where it doesn't show them in the RTL viewer. There is a
global setting for syn_useenables too, although I have not used it that way.
You shouldn't have to screw with the edif (I consider that a hack and avoid it
at all costs).
"Nicholas C. Weaver" wrote:
> Thanks. We'll try it and see how it works. Symplify is
> inserting the CEs in the mapping phase, since they appear in the EDIF
> but not in the internal structural view.
>
> Worst case, a little EDIF munging is in order.
> --
> Nicholas C. Weaver nweaver@cs.berkeley.edu
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45968
Depends on your board layout and signal integrity. In other words, I
would not count on it staying at either value. Small perturbations on the
differential current on the pins, or even on the input thresholds will
cause it to toggle inside. Rather than tying both to ground, why not tie
one high and one low.
Yanick wrote:
> Hi,
>
> On a Virtex-II, we have a LVPECL IBUFGDS and we need to detect if
> there is a clock or not at the pins. If no clock is present, both
> inputs are tied to ground on the PCB (2 flavours of PCB). Looking at
> the doc, the output of the IBUFGDS is 'X' when both inputs are at '0'.
>
> Is the output of the IBUFGDS stable to either '0' or '1' or can there
> be transitions that would cause the detection circuit (SRL16) to fail
> ??
>
> Regards,
>
> Yanick
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45969Hi SH7, Thank you for your reply. Yes, the questions are similar. I ask this question again because I find that the free systhesis tools always target to FPGA. If I design the chip by FPGA, then I change it to ASIC. I can find some vender to help me for conversion. However, if I want to design the chip directly. I guess that it is something difficult. (eg. what systhesis tools i can you? As the target is not a FPGA, what library used for systhesis?) Reala "Spam Hater" <spam_hater_7@email.com> wrote in message news:3d57e652.6164760@64.164.98.7... > > Hi, > > You asked this same question on 07/22/2002 > > What's wrong with the answers you got then? > > SH7 > > > > On Mon, 12 Aug 2002 11:32:31 +0800, "Reala" > <manfield.chow@scoreconcept.com> wrote: > > >Hi, > > > >I wrote a verilog code. Then, I ran Modelsim to verify the design. > >If I implement the design by Altera, I can use LeonardaSpectrum for > >synthesis. > >However, i want to implement the design by ASIC. What > >information/software/library needed for this approach? Thank you. > > > >Reala > > > > > > > > > > >Article: 45970
Hi can anybody tell me what is the assumption that xilinx trce makes wrt to the external capacitance when giving the pad to pad delay. AnjanArticle: 45971
Reala, For the library, you have to contact the fabrication house and find out which ones they have certified. For example, with TSMC or UMC, you can use Artisan or Virtual Silicon. There are dozens of FAB houses, and dozens of library makers. For synthesis, you can use Synplicity, Synopsys, or Ambit. There's probably more; those are the ones I have used. Just make sure the library has support. It's a 3-piece puzzle, that involves substantial time to solve. This is a non-trivial task. It takes work. No sane person is going to do this much work for free; serious money is usually involved. And you're probably unaware of the costs involved. I can put together a decent FPGA development station for $1,300.00 - that includes the prototype board and all the software. (Actually, you can build a Cypress development station, including HDL, for under $500.) The last ASIC I did, we used $2,000,000.00 worth of layout software, simulators, and synthesizers. And the 1st chip run cost $250,000.00 The FPGA maker makes their money on the chips; they practically give the software away. Yes, there are cheaper ways to do it. Take a class in ASIC design at a local university, and see how they do student runs. SH7 On Tue, 13 Aug 2002 14:11:55 +0800, "Reala" <manfield.chow@scoreconcept.com> wrote: >Hi SH7, > >Thank you for your reply. >Yes, the questions are similar. >I ask this question again because I find that the free systhesis tools >always target to FPGA. >If I design the chip by FPGA, then I change it to ASIC. I can find some >vender to help me for conversion. >However, if I want to design the chip directly. I guess that it is something >difficult. >(eg. what systhesis tools i can you? As the target is not a FPGA, what >library used for systhesis?) > >Reala > > >"Spam Hater" <spam_hater_7@email.com> wrote in message >news:3d57e652.6164760@64.164.98.7... >> >> Hi, >> >> You asked this same question on 07/22/2002 >> >> What's wrong with the answers you got then? >> >> SH7 >> >> >> >> On Mon, 12 Aug 2002 11:32:31 +0800, "Reala" >> <manfield.chow@scoreconcept.com> wrote: >> >> >Hi, >> > >> >I wrote a verilog code. Then, I ran Modelsim to verify the design. >> >If I implement the design by Altera, I can use LeonardaSpectrum for >> >synthesis. >> >However, i want to implement the design by ASIC. What >> >information/software/library needed for this approach? Thank you. >> > >> >Reala >> > >> > >> > >> > >> > >> > > > >Article: 45972
Hello, I am trying to chose some memory to store configuration files for Xilinx FPGAs and I've noticed that in previous designs when I created an FPGA configuration file, the RBT was usually 8 or 9 times bigger than the BIT file. In theory as Xilinx mentions in http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID= 1&getPagePath=14468 the RBT is a 'An ASCII version of the bit file'. Is the size different only because the compression algorithm is different? In that case what are the benefits of using RBT files if you need a bigger memory to store them? Is just that the header is readable with a simple editor? Thank you very much. -- Ulises HernandezArticle: 45973
Hi, I am working on survey paper for one of my Grad. classes on selecting FPGA based processors for embedded systems <br> I would like to hear how people decide on the following issues -Hardware and Software partitioning <br> -Selecting a processor solution Soft processor? or Hard processor? <br> - Design flow for hardware-software co-design. Are there any good books or websites discussing these topics. I would greatly appreciate your help. Thanks BillArticle: 45974
Hi! For a SOC I use both ROMs made of Block-RAMs and dual-ported Block-RAMs that are preloaded at reset. Currently I use CoreGen to generate these building blocks. I use Xilinx Foundation 4.1i XST and would much prefer to use inferred Block-RAMs. I know the Language Assistant VHDL examples for inferring Block-RAM, but they do not show how to preinitialize the RAMs. Any ideas? Kolja Sulimma
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