Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi, Given below is the method I use to estimate the number of ASIC gates my design might use. 1. 10000 logic elements used on EP20K1500E (Apex20KE). 2. 51480 LE's correspond to 1.5e+6 'FPGA' gates on EP20K1500E. 3. Hence each LE = 29.13 'FPGA' gates. 4. 10000 LE's = 291,300 'FPGA' gates. 5. ASIC gates = 291300/4 = 72,825 'ASIC' gates. Is this correct ? I understand this is a rough estimate. Would the gurus consider this pessimistic or optimistic if low gate counts was the goal ? Would there be a recommendation for a more correct solution similar to the above approach ? Thanks, PrashantArticle: 45901
Hi, I want to be able to configure Altera EPC2 devices over a ByteBlaster MV cable from a command-line script using a simple configuration tool. Altera's JAM Player seems to be the program for the job. However, I can't get it to work. I've tried it on two different computers, (Windows 98 and Windows XP with the driver), both of which are able to detect and program the EPC2 from the Quartus programmer. However, Jam (jbi.exe) won't detect the EPC2, reporting "Device #1 unable to read IDCODE." When I disconnect the EPC2 from the ByteBlaster and try JAM, it reports, "Device #1 IDCODE is FFFFFFFF. Unrecognized device." This would indicate that the ByteBlaster cable is at least sort of working, but I can't understand why the EPC2 isn't being detected. Has anyone used Jam this way and had any problems (or successes) with it? Thanks, Mike NeufeldArticle: 45902
Not as is anyway. There are an awful lot of people out there that pick those
up as a starting point. That is a mixed bag, because some of them are poor
implementations which make poor foundations for a design.
Richard Iachetta wrote:
> In article <d049f91b.0208081028.309454bd@posting.google.com>,
> kayrock66@yahoo.com says...
> > I suppose you might argue that this in turn reduces the cost of
> > consumer electronics goods for the whole world, but still, why on my
> > ticket? Put another way, why should Motorola (for example) be able to
> > my XYZ core back to me in the form of a cell phone ASIC?
> >
> > What do you think?
>
> I could be wrong but I doubt companies are really putting these cores into
> products.
>
> --
> Rich Iachetta
> iachetta@us.ibm.com
> I do not speak for IBM.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45903Hi Austin, I am at a university, but this would be for instrumentation in a particle physics experiment, not for teaching students. The XUP folks were helpful in getting me a PCI core, so I do know about them. However, my real question is: when it will be possible to actually buy say 1000 of these parts, and how much will they cost? Xilinx seems to sell the largest members of a new part family first, and gradually work their way down. It took several years for the XC2S15 to become available after the XC2S200. I think only the larger parts in the XC2V series are available. The XC2VP series has been advertised for over a year now, but none of them is in stock anywhere. Even if I could get an evaluation XC2VP4 from the university program, would it make sense to design it in to a board I want to produce in quantity in a year or two? It's great that Xilinx continues to advance FPGA technology, but it's no fun to see adverts and data sheets for a part that won't actually be available in any reasonable quantity for a couple more years. In article <3D53CF3E.7430002A@xilinx.com>, Austin Lesea wrote: >Paul, > >If you are part of a University program, please contact the Xilinx >University support folks at: > > http://www.xilinx.com/univ/index.htm > >Austin > >Paul Smith wrote: > >> Anyone actually managed to get one of these yet? Doesn't show up >> at findchips.com >Article: 45904
I haven't had the time to look at this too closely. My initial thought is that
you may not need to do an explicit divide since essentially you are looking for
the ratio of two counts. Look at frequency counters to get a better idea of how
this might be useful to you.
Now, if you still want to do a real divide, then floating point actually makes
your job easier. FIrst step is to normalize your dividend and divisor, then you
can dispense with the extra precision in the resulting significand. For small
precisions, a look-up table can be used with quite good results. We did some
division in video where the data is only 8 bits and normalizing it first got use
down to a small LUT for the divide...most of the information is in the exponent
which is simply subtracted. If your 5digits are decimal digits, you'll need a
bit more for the divide on the significands. Since your data rate is low, and
the counts are presumably unsigned, you can get away with an iterative restoring
divider, which is little more than a subtractor, compare (another subtract) and
a state machine. Spend the $40 or so and pick up Isreal Koren's Computer
Arithmetic (available from the Amazon bookstore on my website, and if you order
there I get a small referral fee that helps to keep up the website). He goes
into considerable detail on the algorithms for division and square root, both
for fast parallel and sequential solutions.
Finally, what you are looking for is a hardware solution to do the division:
that exists in many forms and the fpga is very capable of doing it much faster
than the 1Khz rate you need. The divider will occupy a small area. The
hardware solution has little to do with the VHDL. Keep in mind VHDL should be
used to express hardware. If you are to be successful using it, you will have
to visualize the hardware first then code to produce the structure you
visualize.
Best of luck, and have fun learning!
Jason Berringer wrote:
> Hello FPGA and VHDL experts,
>
> I require a little assistance. I have done some searches and read through a
> few texts to see if the topic is covered and can't find the information that
> I'm looking for. I have two counter banks which are counting away. At 1 kHz
> I take the counts in both of the banks, generate an interrupt and pass off
> the values to a CPU where the floating point division of the counts BANK A
> divided by BANK B occurs along with some fancy DSP filtering. I use an ISA
> interface for the data transfer. What I'm looking to do is move the division
> inside of the FPGA. Can anyone point out a couple of examples so I can learn
> how to do this. I'm looking for floating point division with at least 5
> digits of precision in my result. Then I can perform some fancy DSP
> filtering inside of the FPGA.
> Note, the counter banks are 24 bits each.
>
> Questions:
>
> 1. Can this be done as a VHDL module or do I have to embed a CPU type core
> for the division?
> 2. Does anyone know of an app note that might cover, and provide a small
> example of this type of VHDl code?
> 3. Am I crazy to try this (ie should I just let the CPU do the work)?
>
> If my question seems rather niave I appologize, I've only been working with
> VHDL and FPGAs for about a year so my knowledge is somewhat limited (so go
> easy with the shots please!). Any help is greatly appreciated.
>
> Thanks
>
> Jason Berringer
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45905Paul, Well, we are shipping to customers now. First shipments were in March of this year http://www.xilinx.com/prs_rls/silicon_vir/0204_v2p_main.html (prices listed) In Virtex II, the smallest members were available as the first samples (XC2V40 and 2V1000). I would still go through the University program, as they are tasked with taking care of this important part of the marketplace. I doubt seriously that you will find any sitting on a shelf unspoken for. That is just poor inventory management nowadays. Email me directly to tell me about your project, there may be some common interests here, and I am willing to look into it for you (I am the "champion" for UC Berkeley EECS and BWRC, and work with the "champion" for Standford -- I know, how strange can that be?). Austin Paul Smith wrote: > Hi Austin, > > I am at a university, but this would be for instrumentation in a particle > physics experiment, not for teaching students. The XUP folks were helpful > in getting me a PCI core, so I do know about them. > > However, my real question is: when it will be possible to actually buy say 1000 > of these parts, and how much will they cost? > > Xilinx seems to sell the largest members of a new part family first, and > gradually work their way down. It took several years for the XC2S15 to become > available after the XC2S200. I think only the larger parts in the XC2V series > are available. The XC2VP series has been advertised for over a year now, but > none of them is in stock anywhere. > > Even if I could get an evaluation XC2VP4 from the university program, > would it make sense to design it in to a board I want to produce in quantity > in a year or two? > > It's great that Xilinx continues to advance FPGA technology, but it's no fun > to see adverts and data sheets for a part that won't actually be available in > any reasonable quantity for a couple more years. > > In article <3D53CF3E.7430002A@xilinx.com>, Austin Lesea wrote: > >Paul, > > > >If you are part of a University program, please contact the Xilinx > >University support folks at: > > > > http://www.xilinx.com/univ/index.htm > > > >Austin > > > >Paul Smith wrote: > > > >> Anyone actually managed to get one of these yet? Doesn't show up > >> at findchips.com > >Article: 45906
> I think I figured out how to answer this, any other comments appreciated > tho! I need to use the "attribute iob : string;" statement in the > entity or architecture header, and then say > > attribute iob of <signal name> : signal is "false"; > > and that should fix my problem. > > Patience, persistence, truth, > Dr. mike > I'm not sure I understand what you've done: only external signals should be declared in the entity statement, internal signals are declared between the architecture and begin keyword. These last one are not instantiated as iob by any synthetizer I used (XST, leonardo). hth S.-Article: 45907
Hi everyone, I am new to this group, so I am all excited about joining this fountain og knowledge. I hope that a small query of mine can be answered....:) My issue is this: I am employing clock-gating on a Virtex-II FPGA using the BUFGMUX unit, in order to turn off idle functional units, for reducing dynamic power dissipation in my design. However, when I use XPower (the power estimator tool offered by Xilinx) to estimate the power dissipation, it does not report the correct activity rate for the gated clock. Infact, the switching frequency reported by it is the same as the global ungated clock. Does it mean that it does not take the activity rate of a clock into account? Is there any way that I can make Xpower understand the clock being gated?? Any help would be greatly appreciated. Thank you Vikram Chandrasekhar. Vikram Chandrasekhar Graduate Student Electrical and Computer Engg. Rice University Ph:(713)529 9819 (R) (713)348 2897 (O) www.ece.rice.edu/~cvikram/index.htmlArticle: 45908
There is a Xilinx app note on this: it's also in the "Virtex 2 User Guide" (which includes a VHDL template). You need to define the initialisation data TWICE: as generics for ModelSim, and as attributes for synthesis (no, it wasn't me that did it :) I ended up writing a C program to take a hex file, and write the VHDL from it. Philippe Bataille <philippe.bataille@sacet.com> wrote: :Hi, : :I'm using WebPack4.2 and I already developed some VHDL codes without any : :problem. Now I want to implement and simulate a VHDL block using Block :RAM (virtex-E 300). The synthesis phase seems to be good but the :simulation (with modelsim) in order to verify the content of the RAM :don't work and signal output when I try to read RAM always return 'U' :although RAM is initialized before. Could someone give me a solution to :resolve this problem ? thanks in advance for your :help! : :Regards : :Philippe :Article: 45909
Mike, I have heard that there may be some funny problems when you try and use Quartus for this. Do you have Max Plus II? If so, try that. You may have better success. -Xanatos "Mike Neufeld" <michaelsneufeld@yahoo.com> wrote in message news:aj18ph$308$1@nntp.itservices.ubc.ca... > Hi, > > I want to be able to configure Altera EPC2 devices over a ByteBlaster MV > cable from a command-line script using a simple configuration tool. Altera's > JAM Player seems to be the program for the job. However, I can't get it to > work. I've tried it on two different computers, (Windows 98 and Windows XP > with the driver), both of which are able to detect and program the EPC2 from > the Quartus programmer. However, Jam (jbi.exe) won't detect the EPC2, > reporting "Device #1 unable to read IDCODE." When I disconnect the EPC2 from > the ByteBlaster and try JAM, it reports, "Device #1 IDCODE is FFFFFFFF. > Unrecognized device." This would indicate that the ByteBlaster cable is at > least sort of working, but I can't understand why the EPC2 isn't being > detected. Has anyone used Jam this way and had any problems (or successes) > with it? > > Thanks, > Mike Neufeld > > >Article: 45910
Igor wrote: > I have Reed-Solomon decoder with polynom 391 (Intelsat standard), > whether probably to transform a signal encoded with polynom 285 (DVB > standard), and decode it by this decoder ? > If there's no errors you can convert code words directly. If there's errors to deal with, the math would get pretty hairy. So I'd guess yes "in principle" it should be possible. Patience, persistence, truth, Dr. mike -- Mike Rosing www.beastrider.com BeastRider, LLC SHARC debug toolsArticle: 45911
Jay <kayrock66@yahoo.com> wrote: > I suppose you might argue that this in turn reduces the cost of > consumer electronics goods for the whole world, but still, why on my > ticket? Put another way, why should Motorola (for example) be able to > my XYZ core back to me in the form of a cell phone ASIC? > > What do you think? Your argument will make sense to some people - others, like the OpenCores guys, are happy to give their stuff away without getting anything back financially. There are some interesting writings on this topic. Eric Raymond has some at http://www.tuxedo.org/~esr/writings/cathedral-bazaar/ ; in particular "Homesteading the Noosphere" addresses this topic from memory. Personally I have been contributing to Debian GNU/Linux for the past five years and have never made a cent from it (or even covered costs). It's not a problem for me that people are selling it and making money. I could even argue that Debian is the best of the Linux distributions because we don't have a bottom line to worry about. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 45912
Nahum Barnea <nahum_barnea@yahoo.com> wrote: > I have 2 registers RG1, RG2. > I do not care where they are placed in the fpga, I only want that the > distance between them will be less than "10" i.e inside the square > X0Y0:X9Y9 . > > I guess that RLOC RANGE & RLOC ORIGIN should be used, but I need an > example to see how this is combined. There's no way to allow them to be placed anywhere in the FPGA and less than 10 apart; the best you can do is (1) a fixed distance apart anywhere in the FPGA, or (2) a variable distance at a fixed location. For (1), Just use RLOC: INST RG1 RLOC = "X0Y0"; INST RG2 RLOC = "X9Y9"; They are locked relative to each other but can float anywhere in the chip. You can set an absolute location for the pair using RLOC_ORIGIN or a range with RLOC_RANGE. For (2), use an area group: AREA_GROUP my_ag RANGE = SLICE_XnYn:SLICE_XmYm; INST RG1 AREA_GROUP = my_ag; INST RG2 AREA_GROUP = my_ag; Both components will be placed within the group, but the absolute location of the group is fixed. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 45913
<posted & mailed> On Tuesday 09 July 2002 08:57 am, in comp.arch.fpga, Joeri Vankelst wrote: > Hi, > > I'm not sure if anyone here uses JHDL... > Would it be possible to define a State Machine using JHDL without > having to write the java? What i mean is, is there a tool (like Xilinx > has) you know of I can use to generate JHDL from the states I would > enter. JHDL has a built in FSM generator; you give it the states and it spits out state machines. It described pretty well in the JHDL users manual: http://www.jhdl.org/docs/docs/usersManual/fsm.html If you have more questions, try the to JHDL mailing list (click on "mailing list" from www.jhdl.org) -- it's read directly by JHDL developers and they are more than happy to answer any and all questions you may have. =) -- Wesley J. Landaker - wjl@icecavern.net OpenPGP FP: C99E DF40 54F6 B625 FD48 B509 A3DE 8D79 541F F830Article: 45914
I seek a FPGA developer, serious, motivated and having spare time able to be invested in an interesting challenge. Its work will have to be finished, at the latest, at the end of October. It's a voluntary job. Interested ? Contact me at damien_legieda@hotmail.com -- Use our news server 'news.foorum.com' from anywhere. More details at: http://nnrpinfo.go.foorum.com/Article: 45915
Hi all, There is an interesting product for the Gameboy that uses a Xilinx Spartan FPGA. It costs $129 for the development kit and it looks like a lot of fun to experiment with. The company (www.charmedlabs.com) promotes open-source development and encourages users to write their own FPGA bitstreams and software. Not your typical development system, but worth a look. Bill DiehlsArticle: 45916
Hi, I'm thinking about grabbing a bunch of samples of a burst analog event that will last maybe 100 ns or so. Maxim makes an ADC, the MAX104, that samples up to 1 GSPS and outputs alternate samples on two 8-bit PECL ports. So, is there any chance that the ADC data could be stuffed directly into an FPGA at, say, a sample rate of 800-1000 MHz, implying two 8-bit data ports running at 400-500 Ms/s each? We prefer the Xilinx parts, but would be curious if any of them, or somebody else's parts, can input data this fast. The application here would be sampling the time profile of a laser pulse and applying an algorithm (maybe in the FPGA itself) to optimize something the customer cares about. Thanks, JohnArticle: 45917
The LVDS specs on some of the faster chips will handle that, but the
internal design just to get the data reliably onto the chip is not
trivial, and involves treating the data as DDR data. VirtexII would make
this easier for you, but still a major PITA to pull it off. We did a
similar design earlier this year with an Atmel 8 bit 1GS/sec converter
plus a sister chip (also Atmel) that packed 4 samples into one 32 bit
word and transferred that at a much more manageble 240 MHz into a virtexE
over LVDS lines. That was a lot easier than trying to run at the hairy
edge using interface specs that were not directly compatible.
John Larkin wrote:
> Hi,
>
> I'm thinking about grabbing a bunch of samples of a burst analog event
> that will last maybe 100 ns or so. Maxim makes an ADC, the MAX104,
> that samples up to 1 GSPS and outputs alternate samples on two 8-bit
> PECL ports. So, is there any chance that the ADC data could be stuffed
> directly into an FPGA at, say, a sample rate of 800-1000 MHz, implying
> two 8-bit data ports running at 400-500 Ms/s each? We prefer the
> Xilinx parts, but would be curious if any of them, or somebody else's
> parts, can input data this fast.
>
> The application here would be sampling the time profile of a laser
> pulse and applying an algorithm (maybe in the FPGA itself) to optimize
> something the customer cares about.
>
> Thanks,
>
> John
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45918John Larkin wrote: > Hi, > > I'm thinking about grabbing a bunch of samples of a burst analog event > that will last maybe 100 ns or so. Maxim makes an ADC, the MAX104, > that samples up to 1 GSPS and outputs alternate samples on two 8-bit > PECL ports. So, is there any chance that the ADC data could be stuffed > directly into an FPGA at, say, a sample rate of 800-1000 MHz, implying > two 8-bit data ports running at 400-500 Ms/s each? We prefer the > Xilinx parts, but would be curious if any of them, or somebody else's > parts, can input data this fast. The Altera Stratix devices have ports that will operate up to 844MHz with a built-in LVDS deserializer. Using eight of those in parallel, demultiplexing them in-core, then doubling the data width to match the ~250MHz core RAM speed might do the trick. Each MegaRam block will hold 512Kbits, so that would be 64K samples max per block. This does require some sort of divide-by-eight clock from the ADC, but it is certainly possible. Drop me a note if you need more details. Best regards, BenArticle: 45919
In article <2002810-15296-214605@foorum.com>, Damien <damien_legieda@hotmail.com> wrote: > >I seek a FPGA developer, serious, motivated and having spare time able to be >invested in an interesting challenge. > >Its work will have to be finished, at the latest, at the end of October. > >It's a voluntary job. If you aren't gonna pay, you would be best saying what the job IS. >Interested ? Contact me at damien_legieda@hotmail.com > >-- >Use our news server 'news.foorum.com' from anywhere. >More details at: http://nnrpinfo.go.foorum.com/ -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 45920
Hi, In outlouk express,I configure the server as "comp.arch.fpga",but when I log on it,outlook express promts me that "the server could not be found". What's wrong with my configuration?How can I join the newsgroup and subscribe to the newsgroup? Thanks! Yx jiangArticle: 45921
Eric Smith wrote: > samg@codenet.net writes: > >>I agree that systematic RS system will have the data portion unchanged >>but the parity section will screw up the Syndrome generators that are >>trying to determine if there is an error. >>The reason being that the GF math logic will be slightly different for >>285 vs 301, right? >> > > The logic to transform the codes would be as complex as the > logic to simply decode and reencode. > If not more complex :-) -- Mike Rosing www.beastrider.com BeastRider, LLC SHARC debug toolsArticle: 45922
On Sat, 10 Aug 2002 19:09:22 -0700, "Yx jiang" <marcojyx@seu.edu.cn> wrote:
>Hi,
>
> In outlouk express,I configure the
>server as "comp.arch.fpga",but when I log on it,outlook express promts me that "the server could not be found".
> What's wrong with my configuration?How can I join the newsgroup and subscribe to the newsgroup?
>
> Thanks!
> Yx jiang
============= Standard how-to on reading and posting to comp.arch.fpga
The purpose of WWW.FPGA-FAQ.com is to be a repository for information from
the NEWS group comp.arch.fpga The archive contains ALL articles from
this news group since it started.
The comp.arch.fpga news group has several hundred readers/participants.
comp.arch.fpga is a NEWS group, not an email address or a mail list.
Access to all usenet news groups (there are about 35000 different topics)
is a self-subscription system. You access it your self, no one adds or
deletes you (which is how mail lists work).
The method to access any newsgorup depends on how you have access
to the internet.
If you currently can read news (by this I mean the day to day activity, not
the archive at www.fpga-faq.com) , then whatever program you are
using should also have a posting capability. ("posting" is how you send
a message to a news group for everyone else to read)
If you dont have news access, then the way to do it is different
for every site.
Most companies have a sys-admin or IT department, and they should be able
to set you up.
You might also want to start here:
http://www.islandnet.com/~tmc/html/articles/usentnws.htm
You can get to it via several web sites.
You can get news service by contacting several companies,
such as http://www.supernews.com/
Or try this:
http://groups.google.com/groups?hl=en&safe=off&group=comp.arch.fpga
Here are some other useful links
http://surfbest.net/~jbob@surfbest.net/nglinks1.htm#servers
http://www.newsfeeds.com/index.htm
Philip Freidin
Fliptronics
Article: 45923hamish@cloud.net.au wrote in message news:<3d54c066$0$31150$afc38c87@news.optusnet.com.au>... > Nahum Barnea <nahum_barnea@yahoo.com> wrote: > > I have 2 registers RG1, RG2. > > I do not care where they are placed in the fpga, I only want that the > > distance between them will be less than "10" i.e inside the square > > X0Y0:X9Y9 . > > > > I guess that RLOC RANGE & RLOC ORIGIN should be used, but I need an > > example to see how this is combined. > > There's no way to allow them to be placed anywhere in the FPGA and less > than 10 apart; the best you can do is (1) a fixed distance apart anywhere > in the FPGA, or (2) a variable distance at a fixed location. > > For (1), Just use RLOC: > > INST RG1 RLOC = "X0Y0"; > INST RG2 RLOC = "X9Y9"; > > They are locked relative to each other but can float anywhere in the > chip. You can set an absolute location for the pair using RLOC_ORIGIN or > a range with RLOC_RANGE. > > For (2), use an area group: > > AREA_GROUP my_ag RANGE = SLICE_XnYn:SLICE_XmYm; > INST RG1 AREA_GROUP = my_ag; > INST RG2 AREA_GROUP = my_ag; > > Both components will be placed within the group, but the absolute > location of the group is fixed. > > > Hamish Hamish, ThankX for this great help ! Concerning the 1'st solution, I understand the effect for RG1 and RG2, now I want similiar solution for RG3 and RG4 BUT I do'nt want to put any contraint between RG1-RG2 to RG3-RG4. Is it possible ? ThankX again NAHUM.Article: 45924
Kevin Brace wrote: > At least for Spartan-II, and for my application (A PCI IP core), I find > the existence of F5MUX, a mixed bag. > I doubt that you will see any kind of significant performance gain since > F5MUX's delay isn't that small compared to a 4-input LUT. > Using Floorplanner is probably better if you are trying to reduce the > overall delay. > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.) The trouble with the floorplanner approach is that it only works if the name of the object can be held stable. o.k. for FFs but hard for LUTs synthesised from a mass of combinational equations, muxes, etc. Even small logic changes can have big effects in the naming - to the extent that even if a name is preserved it might relate to an entirely different logic function.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z