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Howdy folks, I'm trying to learn VHDL so I can program a small Virtex2 with some test structures. After scanning some of the messages here, I'm not sure if I should use XST, Express, or something else. Is it possible to program each slice directly without having to use primitives like RAM16x1S? I think I can make the FPGA do what I want, but I'd like to grab the thing at a lower level. Any pointers or suggestions appreciated! Patience, persistence, truth, Dr. mike -- Mike Rosing www.beastrider.com BeastRider, LLC SHARC debug toolsArticle: 45001
Hakon, In the Virtex, Virtex E, Spartan II, and Spartan IIE, LOCKED may occasionally go low due to asynchronous gaps in the input clock, and then go high again. One has to catch the falling edge of LOCKED to be sure the DLL is not locked. If the input clock stops altogether, LOCKED stays high (it is a synchronous state machine). This was changed in Virtex II, and Virtex II Pro, so that once low, LOCKED can not go high again until it is RESET. If the clock in stops, the CLK_IN_STOPPED status bit goes high (LOCKED will stay high as in the previous families). If the CLKFX stops, the CLKFX_STOPPED status bit goes high until reset (and again, LOCKED stays high). So a healthy DCM = LOCKED AND NOT(CLK_IN_STOPPED OR CLKFX_STOPPED). Austin Hakon Lislebo wrote: > Hi, I mean that I have read that the Xilinx DCM - LOCKED output stays, > or goes high again after the DCM has lost lock. Is that correct? Does > anybody have a link to some documentation? > > Thank you > Regards > Hakon LisleboArticle: 45002
"Philip Pemberton" <philpem@despammed.com> wrote in message news:<agd0ni$kfjfd$1@ID-122086.news.dfncis.de>... > Hi, > I've been having a look at Xilinx's website and I'm trying to think of a > (low cost) way to start designing with FPGAs. Right now, I don't care who > makes them as long as said FPGA is reasonably cheap in 1-off quantities and > the devkit/software costs around GBP100 or less. > Anyone got any suggestions? > > Thanks. Have a look at http://www.al-williams.com/awce/pbx84.htm You might also enjoy the associated tutorials at http://www.al-williams.com/pictutor. Al Williams AWCArticle: 45003
If you want a flexible board that allows you to attach to a solderless breadboard or incorporate the chip into your own designs have a look at http://www.al-williams.com/awce/pbx84.htm -- works with Web Pack. You might also enjoy our related tutorials at http://www.al-williams.com/pictutor Al Williams AWCArticle: 45004
Hello, I'm trying to implement a LUT (16 deep, 8 bits wide), which should be able to be programmed its content while the data is been read. I know that I can't read data from a location while I'm writing to the same location - this could be a memory read-write violation. Obviously, using two of them and muxing the read and write is the easiest option. I'm trying to find out if there are any other ways of doing this. I'm wondering if the use of Distributed SelectRam (RAM16X1D) could help me. Any suggestions are greatly appreciated. Antony.Article: 45005
Stéphane Guyetant wrote: > > Say we have a SDRAM (Micron 256Mb) connected to a FPGA (Spartan II). > We want to keep the information in RAM after reconfiguration (obviously, > the SDRAM controller is the same). > > Is it sufficient to pull-down (10K) the CKE pin of the RAM chip to drive > it low during reconfiguration, as all other pins are in high impedance > state? > > If not, do you see any other solution than partial reconfiguration? > > Thanks, > Stephane I believe pulling the CKE pin low will do what you want. Pulling the CE- pin high will also do what you want, IIRC. In either case you need to pay attention to initialization of the SDRAM. I am not sure if initialization will affect the contents of the SDRAM, but to be safe, the controller will need to be modified to initialize only on a power on rather than when the FPGA is reconfigured. I assume you will need an external signal for this. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 45006
You have the right primitive, indeed. If you have a good synthesizer, you can infer the lookup as well. Synplify has been doing the distributed dual-ports for me nicely (as long as I define a write enable), even duplicating when I need more than one read channel (a tri-port?). IIRC, the Xilinx data sheets do a good job of illustrating the timing for the read-write violation. Antony wrote: > Hello, > > I'm trying to implement a LUT (16 deep, 8 bits wide), which should be > able to be programmed its content while the data is been read. I know > that I can't read data from a location while I'm writing to the same > location - this could be a memory read-write violation. > > Obviously, using two of them and muxing the read and write is the > easiest option. I'm trying to find out if there are any other ways of > doing this. I'm wondering if the use of Distributed SelectRam > (RAM16X1D) could help me. > > Any suggestions are greatly appreciated. > > Antony.Article: 45007
"Al Williams" <alw@al-williams.com> ha scritto nel messaggio news:a9835df1.0207090722.299f7f47@posting.google.com... > > I've been having a look at Xilinx's website and I'm > > trying to think of a > > (low cost) way to start designing with FPGAs. [...] > Have a look at http://www.al-williams.com/awce/pbx84.htm It doesn't look like a FPGA protoboard: /*********************************************************************** [...] But today design engineers use programmable logic devices -- devices like the Xilinx 9500 (specifically, the XC9572 and XC95108) series CPLDs (sometimes known as FPGAs). [...] ***********************************************************************/ CPLD and FPGA are two different things. XC9500 is a CPLD family. -- LorenzoArticle: 45008
Hello,
I am having a problem implementing a bi-directional bus within a
Xilinx virtex 2 part. I have read through the numerous postings and
have not found a clear answer. I have implemented a bus that works
fine in simulation, but when it is synthesized, fpga express says it
cannot determine the port type and replaces it with an output port
(FPGA-pmap-18). My architecture consists of a set of registers that
exist in separate vhdl blocks. The designs synthesizes normally and
functions normally on a virtex 2 demo board when the registers reside
in the same block. When I split them up, I run into the above
problem. I ran across someone else's post, that said I need to use a
mux to have an internal bi-directional bus, is this true? Also at one
point in the back-end xilinx tool I got a message asking me to set
XVK_MAP_ALLOW_BUS_CONTENTION environment variable. Any help would be
greatly appreciated. I have included a simplified sample of one of
the vhdl blocks.
Thanks in Advance,
Mike Schreiber
Hardware Engineer
mschreiber75@yahoo.com
entity SLAVE_1 is
port (
ADDR : in std_logic_vector (9 downto 0); --8-bit
address bus, temporarily 9-bit
DATA : inout std_logic_vector (15 downto 0); --8-bit
data bus
RD_N : in std_logic; --read signal, active-low
WR_N : in std_logic; --write signal, write is
active-low
RESET : in std_logic; --system reset
CLK : in std_logic; --system clock
BLOCK_SELECT_N : in std_logic --block select enable
);
end SLAVE_1;
--}} End of automatically maintained section
architecture BEH of SLAVE_1 is
signal DATA_IN : std_logic_vector(15 downto 0);
signal DATA_OUT : std_logic_vector(15 downto 0);
signal DUMMY_REG : std_logic_vector(15 downto 0);
--Internal Registers
signal REG1_DATA : std_logic_vector(15 downto 0);
signal REG2_DATA : std_logic_vector(15 downto 0);
--address range: 0x00 - 0x1f, block address: 1
constant REG1_ADDR : std_logic_vector := "0000000000"; --address of
described register
constant REG2_ADDR : std_logic_vector := "0000000001"; --address of
described register
begin
-- <<enter your statements here>>
DATA <= DATA_OUT when (RD_N = '0') else (others => 'Z');
DATA_IN <= DATA when (WR_N = '0') else DATA_IN;
process (CLK, RESET, ADDR, DATA) begin --read write process
if(RESET = '1') then
REG1_DATA <= (others => '0');
REG2_DATA <= (others => '0');
elsif(CLK'event and CLK = '1') then
if (WR_N = '0') then --bus write
case ADDR(9 downto 0) is
when REG1_ADDR =>
REG1_DATA(15 downto 0) <= DATA_IN;
REG2_DATA(15 downto 0) <= REG2_DATA(15 downto 0);
when REG2_ADDR =>
REG1_DATA(15 downto 0) <= REG1_DATA(15 downto 0);
REG2_DATA(15 downto 0) <= DATA_IN;
when others =>
REG1_DATA <= REG1_DATA;
REG2_DATA <= REG2_DATA;
end case;
elsif (RD_N = '0') then --bus read
case ADDR(9 downto 0) is
when REG1_ADDR =>
DATA_OUT <= REG1_DATA(15 downto 0);
when REG2_ADDR =>
DATA_OUT <= REG2_DATA(15 downto 0);
when others =>
DATA_OUT <= (others => 'Z'); --high imp.
data bus
end case;
else
DUMMY_REG <= DUMMY_REG;
end if;
end if;
end process;
end BEH;
Article: 45009Hi Mike, Make sure that all signals declared as bidirectional are actually used as both input and output. See (Xilinx Solution 3296) for more details. The above warnings usually occur when there are multiple three-state inferences driving the inout signal. Rather than choosing one three-state to place in the IOB, Express will place all the three-state using internal TBUFs then use a standard OBUF at the IOB. Examine your HDL to be sure the bidirectional structure is explicit. Hari. M Schreiber wrote: > Hello, > I am having a problem implementing a bi-directional bus within a > Xilinx virtex 2 part. I have read through the numerous postings and > have not found a clear answer. I have implemented a bus that works > fine in simulation, but when it is synthesized, fpga express says it > cannot determine the port type and replaces it with an output port > (FPGA-pmap-18). My architecture consists of a set of registers that > exist in separate vhdl blocks. The designs synthesizes normally and > functions normally on a virtex 2 demo board when the registers reside > in the same block. When I split them up, I run into the above > problem. I ran across someone else's post, that said I need to use a > mux to have an internal bi-directional bus, is this true? Also at one > point in the back-end xilinx tool I got a message asking me to set > XVK_MAP_ALLOW_BUS_CONTENTION environment variable. Any help would be > greatly appreciated. I have included a simplified sample of one of > the vhdl blocks. > Thanks in Advance, > Mike Schreiber > Hardware Engineer > mschreiber75@yahoo.com > entity SLAVE_1 is > port ( > ADDR : in std_logic_vector (9 downto 0); --8-bit > address bus, temporarily 9-bit > DATA : inout std_logic_vector (15 downto 0); --8-bit > data bus > RD_N : in std_logic; --read signal, active-low > WR_N : in std_logic; --write signal, write is > active-low > RESET : in std_logic; --system reset > CLK : in std_logic; --system clock > BLOCK_SELECT_N : in std_logic --block select enable > ); > end SLAVE_1; > > --}} End of automatically maintained section > > architecture BEH of SLAVE_1 is > signal DATA_IN : std_logic_vector(15 downto 0); > signal DATA_OUT : std_logic_vector(15 downto 0); > signal DUMMY_REG : std_logic_vector(15 downto 0); > --Internal Registers > signal REG1_DATA : std_logic_vector(15 downto 0); > signal REG2_DATA : std_logic_vector(15 downto 0); > --address range: 0x00 - 0x1f, block address: 1 > constant REG1_ADDR : std_logic_vector := "0000000000"; --address of > described register > constant REG2_ADDR : std_logic_vector := "0000000001"; --address of > described register > begin > -- <<enter your statements here>> > DATA <= DATA_OUT when (RD_N = '0') else (others => 'Z'); > DATA_IN <= DATA when (WR_N = '0') else DATA_IN; > process (CLK, RESET, ADDR, DATA) begin --read write process > if(RESET = '1') then > REG1_DATA <= (others => '0'); > REG2_DATA <= (others => '0'); > elsif(CLK'event and CLK = '1') then > if (WR_N = '0') then --bus write > case ADDR(9 downto 0) is > when REG1_ADDR => > REG1_DATA(15 downto 0) <= DATA_IN; > REG2_DATA(15 downto 0) <= REG2_DATA(15 downto 0); > when REG2_ADDR => > REG1_DATA(15 downto 0) <= REG1_DATA(15 downto 0); > REG2_DATA(15 downto 0) <= DATA_IN; > when others => > REG1_DATA <= REG1_DATA; > REG2_DATA <= REG2_DATA; > end case; > elsif (RD_N = '0') then --bus read > case ADDR(9 downto 0) is > when REG1_ADDR => > DATA_OUT <= REG1_DATA(15 downto 0); > when REG2_ADDR => > DATA_OUT <= REG2_DATA(15 downto 0); > when others => > DATA_OUT <= (others => 'Z'); --high imp. > data bus > end case; > else > DUMMY_REG <= DUMMY_REG; > end if; > end if; > end process; > end BEH;Article: 45010
I have no idea about Java, so I won't answer that part of the
question, but regarding EDIF, what you can do is you can synthesize a
Verilog or VHDL design, and look at the EDIF netlist generated.
EDIF's syntax isn't nice, but if you have some idea what the design
does, and understand what the library primitives do, you should be able
to understand what's going on.
When converting a design to an IP core, I often edit EDIF netlist with a
text editor because the synthesis tools I use (XST (Xilinx Synthesis
Technology) and LeonardoSpectrum-Altera) don't support automatic FF
duplication needed for IOB (Xilinx) or IOE (Altera) inclusion that well.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Joeri Vankelst wrote:
>
> Hi,
>
> I'm not sure if anyone here uses JHDL...
> Would it be possible to define a State Machine using JHDL without
> having to write the java? What i mean is, is there a tool (like Xilinx
> has) you know of I can use to generate JHDL from the states I would
> enter.
>
> I'm also looking for information on the EDIF syntax. Does anyone here
> know where I can find a tutorial or white papers? www.edif.org wasn't
> very helpfull in providing information on the syntax.
>
> tnx!
>
> joeri Vankelst
> swinger667@yahoo.com
Article: 45011MikeJ wrote: <snip> > My trick is to instantiate all the counters / adders / muxers etc I need and > then use the floorplanner to place them. Use UCF flow, . . . </snip> I'm going that direction. I hate trying to write my HDL with primitives. I was hoping to avoid this. This morning I started putting together my own "A gt B" module (trying out some Verilog2001) and I may have to do the same [expletive] thing with my adders. As a designer, I don't want to have to sit down and think about whether I have simple signals for each bit in a compare or if there's combinatorial logic in the front end that could be "cleaner" (fewer levels of logic) if it's brought into the compare. A simple compare be implemented as 1 to 4 inputs in each stage of a carry chain (4 bits and a constant or 2 bits vs 2 bits max). I want the synthesizer to come up with the best configuration for my needs. Same arguement goes for my accumulators, adders, and counters which Synplify seems to be getting worse at with age; it's been dicey. How many times has the carry-in gone haywire when you *know* it can easily be implemented in the least significant bit? - John_HArticle: 45012
Hallo Steven, Check out the Altera University program (http://www.altera.com/education/univ/unv-kits.html). The basic board has both an SRAM-based FPGA (10K20) and a CPLD (MAX7128). These boards (plus software) are available for really low prices for university students. You can do quite a few things with that board. If it seems to do what you want it to, you can order it in germany by going to the following web page: http://www.altera.com/education/univ/program_regions/unv-germany.html Best regards, BenArticle: 45013
If you want to keep SDRAM contents across reconfiguration for debug purposes on the bench I think this will work okay, but it the product's operation depends on it I don't think this will work. The SDRAM needs to have all of its rows refreshed every 64ms, which is probably too quick to do a reconfiguration. If you are doing a distributed refresh where you refresh single rows at regular time intervals, there will be some row in the SDRAM micro-seconds away from needing to be refreshed when reconfig starts. The refresh spec is very conservative, especially at room temperature, so the refresh issue is probably not a problem on the bench, but will hurt over temperature and voltage. jeff Stéphane Guyetant <sguyetan @nospam.irisa.fr> wrote in message news:<3D2AA288.2D59B3C4@nospam.irisa.fr>... > Say we have a SDRAM (Micron 256Mb) connected to a FPGA (Spartan II). > We want to keep the information in RAM after reconfiguration (obviously, > the SDRAM controller is the same). > > Is it sufficient to pull-down (10K) the CKE pin of the RAM chip to drive > it low during reconfiguration, as all other pins are in high impedance > state? > > If not, do you see any other solution than partial reconfiguration? > > Thanks, > StephaneArticle: 45014
Thanks for the xc_map feature - it certainly makes the LUT instantiation issue easier to deal with when we have to resort to drastic measures. In the example you gave below, where the reference might be xor_lut MyLut ( .z(MyLutOut), .a(ina), .b(inb) ); rather than assign MyLutOut = ina ^ inb; is there a reason the Synplify created LUT in the assign couldn't be named MyLutOut in the first place? Register primitives are named the same as the nets they drive, why not simple combinatorial elements? It's been a burning question of mine for - oh - three or four years now. Thanks, - John_H Ken McElvain wrote: > What you should do is to instantiate the luts. Synplify has a nice > way to do this where you create a verilog module with the attribute > xc_map. > > module xor_lut(z, a, b); // synthesis xc_map=lut > output z; > input a, b; > assign z = a ^ b; > endmodule > > Then your instantiations of xor_lut should be passed through synthesis > unchanged. This is a much clearer way of instantiating LUTS than > trying to figure out the hex programming code. > > John_H wrote: > > > My initial attempts appear to be producing ugly results - any guidance > > is appreciated. > > > > I'm trying to RLOC three adders (two adders feeding the third) in a > > Spartan-II device along with associated input and output registers. I'm > > synthesizing my Verilog code with Synplify but I'm trying to apply all > > the RLOC information in the UCF. Since Synplify dynamically renames > > combinatorial primitives, I'm left trying to imply the locations through > > the registers. > > > > Is there a better way? > > > > I'd hate to implement my adders as dedicated modules. I may have to go > > there to explicitly define all the elements and keep MAP happy. > > > > What is needed to get a carry chain - LUTs, MUXCYs, XORCYs - and > > optional output registers to place with the RLOCs? I tried specifying > > the registers associated with the carries but didn't quite get the > > chains to accompany the registers in the manner I expected. > > > > It seems the RLOC_RANGE attribute is intended for all RLOC elements > > within a module and is an absolute row/column reference. While the > > RLOC_RANGE allows wildcards, it doesn't appear that the RLOC allows a > > wildcard. Would I be able to wildcard the (probable) base name that > > Synplify gives the chain and provide an RLOC list? Since > > "LOC=Y19,AA17,AB21" is a valid form of the LOC command, perhaps a list > > would work for RLOC. > > > > For "assign A_gt_B = A > b;" perhaps: > > > > INST A_gt_B_* RLOC=R0C0.S0,R1C0.S0,R2C0.S0,R3C0.s0; > > > > ?? > > > > I envision MAP complaining about too much going into one slice; I'll > > find out in the morning. Any experiences in getting the mapper and P&R > > to cooperate (given the synplify front end) would be helpful. > > > > Thanks, > > John_H > >Article: 45015
I got an email asking me to check out this new technology which is a cross between NP's and FPGAs to address high performance communication processing needs. Just curious if anyone else got a solicitation email to check them out (Cradle Technologies www.cradle.com ) ?? -Guy -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 45016
Guy Schlacter wrote: > > I got an email asking me to check out this new technology which is a > cross between NP's and FPGAs to address high performance communication > processing needs. > > Just curious if anyone else got a solicitation email to check them out > (Cradle Technologies www.cradle.com ) ?? Nice try at a subtle spam job!Article: 45017
> It doesn't look like a FPGA protoboard: > CPLD and FPGA are two different things. XC9500 is a CPLD family. Of course, you are correct. But my point here -- for the beginner -- is that the same process is true of both CPLDs and FPGAs. The internal arrangment is different and there are some differences at the design level, but the essential process is the same and can be lumped into a general "programmable logic" umbrella (at least, at this simple level). Al Williams AWCArticle: 45018
Dear all, I would like to design a 32 bit multiplier (16bit X 16bit) for MCU. The multiply operation for MCU is one cycle only. Normally, the multiply operation is about 4 cycles. It is a difficult task for me. Is there any special method to make a smaller size multiplier with single cycle do this? Moreover, if i write this by verilog, can the complier take care this kind of task? or depend on the source file of my design? or must do this by schematic design? Anyone have idea to do this? Thank a lot. RealaArticle: 45019
Virtex-II from Xilinx has such multipliers ( actually up to 18 x 18 bits, 2s complementary notation, with 36 outputs ) and has been available for well over a year. the number of multipliers is the same as the number of BlockRAMs, although the two functions share no connections ( except in the case of a 512 x 36 BlockRAM, where some connections are common). Peter Alfke, Xilinx Applications ============================== Reala wrote: > Dear all, > > I would like to design a 32 bit multiplier (16bit X 16bit) for MCU. > The multiply operation for MCU is one cycle only. > Normally, the multiply operation is about 4 cycles. It is a difficult task > for me. > Is there any special method to make a smaller size multiplier with single > cycle do this? > Moreover, if i write this by verilog, can the complier take care this kind > of task? or depend on the source file of my design? or must do this by > schematic > design? > > Anyone have idea to do this? Thank a lot. > > RealaArticle: 45020
"Mark" <Mark@HVWTech.com> wrote in message news:MPG.1793c76ad481b3e49896ec@news.telusplanet.net... > In article <agd0ni$kfjfd$1@ID-122086.news.dfncis.de>, > philpem@despammed.com says... > > Hi, > > I've been having a look at Xilinx's website and I'm trying to think of a > > (low cost) way to start designing with FPGAs. Right now, I don't care who > > makes them as long as said FPGA is reasonably cheap in 1-off quantities and > > the devkit/software costs around GBP100 or less. > > Anyone got any suggestions? > > > > Altera -not Xilinx- but really easy to use: > > http://www.hvwtech.com/intro-fpga.htm Hmm... Very interesting. Shame they don't seem to have any UK distributors. The import duty and VAT on the kit would bring it up to about GBP100... OTOH, I can pull out my Press-N-Peel kit and make a PCB for the Xilinx ISP adapter and build that for roughly cost-of-parts only (already got a fair bit of PCB material), same thing for a simple development board. Shouldn't cost more than GBP25, well within my price range. Later. -- Phil. philpem@despammed.com <<-- Yes, this address is real... http://www.philpem.dsl.pipex.com/Article: 45021
Peter, Thank you for your help. Let me check this from Xilinx. ^_^ Reala "Peter Alfke" <palfke@earthlink.net> wrote in message news:3D2BB73E.2D8E3CE1@earthlink.net... > Virtex-II from Xilinx has such multipliers ( actually up to 18 x 18 bits, 2s > complementary notation, with 36 outputs ) and has been available for well > over a year. the number of multipliers is the same as the number of > BlockRAMs, although the two functions share no connections ( except in the > case of a 512 x 36 BlockRAM, where some connections are common). > > Peter Alfke, Xilinx Applications > ============================== > Reala wrote: > > > Dear all, > > > > I would like to design a 32 bit multiplier (16bit X 16bit) for MCU. > > The multiply operation for MCU is one cycle only. > > Normally, the multiply operation is about 4 cycles. It is a difficult task > > for me. > > Is there any special method to make a smaller size multiplier with single > > cycle do this? > > Moreover, if i write this by verilog, can the complier take care this kind > > of task? or depend on the source file of my design? or must do this by > > schematic > > design? > > > > Anyone have idea to do this? Thank a lot. > > > > Reala >Article: 45022
Hi, I am struggling with a post map simulation of a Xilinx design with a bidirectional I/O port. The I/O port has an output register, input register and tristate control all defined with the IOB attribute. Looking at the map results the I/O implementation seems match what I expect. However, the mapping processes does issue warnings that IOBUF's are being added and that a simulation mismatch may occur - and my testbench does just this. Looking at the simprims logic it seems that the I/O port is implemented internally to the device as the pullup primitive, input register, output register are connected one level in from the actual chip I/O signal. This chip I/O signal has an X-BUF and X-TRI buf inserted before the output pin - making it now purely an output? I can't see why this is as the registered input is used all over (so cannot be removed) and the functional simulation works fine. Anthony.Article: 45023
On Tue, 09 Jul 2002 13:18:13 -0400, rickman <spamgoeshere4@yahoo.com> wrote: >Stéphane Guyetant wrote: >> >> Say we have a SDRAM (Micron 256Mb) connected to a FPGA (Spartan II). >> We want to keep the information in RAM after reconfiguration (obviously, >> the SDRAM controller is the same). >> >> Is it sufficient to pull-down (10K) the CKE pin of the RAM chip to drive >> it low during reconfiguration, as all other pins are in high impedance >> state? >> >> If not, do you see any other solution than partial reconfiguration? >> >> Thanks, >> Stephane > >I believe pulling the CKE pin low will do what you want. Pulling the >CE- pin high will also do what you want, IIRC. CE high is a NOP, which is different to self refresh mode (which requires CKE low). >In either case you need >to pay attention to initialization of the SDRAM. I am not sure if >initialization will affect the contents of the SDRAM, but to be safe, >the controller will need to be modified to initialize only on a power on >rather than when the FPGA is reconfigured. I assume you will need an >external signal for this. I haven't had any problems with SDRAM contents changing due to reinitialisation. I'm fairly sure (although the data sheets don't guarantee this) that the initialisation only affects the interface, and not the contents of the ram. Regards, Allan.Article: 45024
Thank you Austin, that was just what I wanted to know. I also am curious about one more thing: When to DCM's or DLL's are cascaded, Xilinx have introduced a SRL16 shift register between LOCKED on the first DLL to RST on the second. Does that mean that the clock coming out from the first DLL is not completely OK when its LOCKED output goes high? Hakon Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3D2AF5DB.39F513A@xilinx.com>... > Hakon, > > In the Virtex, Virtex E, Spartan II, and Spartan IIE, LOCKED may > occasionally go low due to asynchronous gaps in the input clock, and then > go high again. One has to catch the falling edge of LOCKED to be sure the > DLL is not locked. If the input clock stops altogether, LOCKED stays high > (it is a synchronous state machine). > > This was changed in Virtex II, and Virtex II Pro, so that once low, LOCKED > can not go high again until it is RESET. If the clock in stops, the > CLK_IN_STOPPED status bit goes high (LOCKED will stay high as in the > previous families). If the CLKFX stops, the CLKFX_STOPPED status bit goes > high until reset (and again, LOCKED stays high). > > So a healthy DCM = LOCKED AND NOT(CLK_IN_STOPPED OR CLKFX_STOPPED). > > Austin > > Hakon Lislebo wrote: > > > Hi, I mean that I have read that the Xilinx DCM - LOCKED output stays, > > or goes high again after the DCM has lost lock. Is that correct? Does > > anybody have a link to some documentation? > > > > Thank you > > Regards > > Hakon Lislebo
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