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Messages from 49350

Article: 49350
Subject: Altera MAX7000E (EPM7128ELC84) - programmer?
From: "Philip Pemberton" <philpem@btinternet.com>
Date: Sun, 10 Nov 2002 16:23:31 -0000
Links: << >>  << T >>  << A >>
Hi,
    I've just bought an Altera EPM7128ELC84-10 EPLD for the knock down price
of 5 at a radio rally (hamfest). Does anyone know of a suitable programmer
for this thing? Altera's datasheet says it can't be programmed in-system -
does this mean I can't program it with a Byteblaster?
    Has anyone tried to program a MAX7000E series FPGA with a Byteblaster? I
really don't fancy spending 400 on a programmer for a 5 chip...

Thanks.
--
Phil.
philpem@despammed.com  <<-- Yes, this address is real...
http://www.philpem.dsl.pipex.com/



Article: 49351
Subject: Re: LU-decomposition
From: fireball <sensen@swirvemail.com>
Date: Sun, 10 Nov 2002 08:44:10 -0800
Links: << >>  << T >>  << A >>
I'm trying to solve a 3 variable linear equation using matrix (LU-decomposition method). Anybody can shed light on how to do this in FPGA hardware?

Can FPGA do floating point?

Article: 49352
Subject: CLB numbers for various ops?
From: devnull@mighty.morphism.org
Date: Sun, 10 Nov 2002 17:58:10 +0000 (UTC)
Links: << >>  << T >>  << A >>
I'm starting to do some research into reconfigurable computing for my
MSc directed study.  One of my applications involves string processing.

Given a bitvector of length 28 and the CLB from a Spartan-IIE family
FPGA, can anybody estimate (off the top of their head) roughly how many
CLB's it would take to implement an operation to count the number of 1's
as well as an operation to produce a 5-bit number indexing the first bit
that is set to a 1?  These operations are essential for traversing trie
data structures quickly in hardware.

Latency isn't an issue, so we can assume the design constraint is minimal
area. 

Thanks,
Brian

Article: 49353
Subject: Re: CLB numbers for various ops?
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sun, 10 Nov 2002 20:12:28 +0100
Links: << >>  << T >>  << A >>
<devnull@mighty.morphism.org> schrieb im Newsbeitrag
news:aqm6ni$2ngc$1@news2.engin.umich.edu...
> I'm starting to do some research into reconfigurable computing for my
> MSc directed study.  One of my applications involves string processing.
>
> Given a bitvector of length 28 and the CLB from a Spartan-IIE family
> FPGA, can anybody estimate (off the top of their head) roughly how many
> CLB's it would take to implement an operation to count the number of 1's
> as well as an operation to produce a 5-bit number indexing the first bit
> that is set to a 1?  These operations are essential for traversing trie
> data structures quickly in hardware.
>
> Latency isn't an issue, so we can assume the design constraint is minimal
> area.

Hmm, for a quick estimation I would say.

2 LUTs can count then number of 1' in 1 4 bit vector (its just a simple 16x2
Bit ROM)

-> 14 LUTs

Then, these 7 results must be summed up, which could be done in a 3 level
tree structure, consisting of 4 + 2 + 1 = 7   4-bit adders, which can be
easyly pipelined.
One 4.bit adder takes 4 LUTs

-> 42 LUTs for the bit counting

For the detection of the first bit, it could be done also in a kind of
decicion tree, similar to a barrel shifter. The first level checks the
upper/lower 14 bits for unequal to zero. One LUT can check up to 4 inputs,
the carry chain could be used for summing the results (its just a big OR
function)

-> 2 x 4 LUTs

The next stage must decide for the upper/lower 7-bit "nibble" on the right
word if it is /=0 or not. again 2 x 4 LUTs
This repeats until we have a singe bit

28 -> 14 -> 7 -> 3/4 -> 2        so 5 stages  -> 5 x 8 LUTs = 40 LUTs

5 LUTs are required to select the propper result in each stage. Also a
structure which can be very easy pipelined.

--
MfG
Falk





Article: 49354
Subject: Re: LU-decomposition
From: "Jan Gray" <jsgray@acm.org>
Date: Sun, 10 Nov 2002 11:45:00 -0800
Links: << >>  << T >>  << A >>
"fireball" <sensen@swirvemail.com> wrote in message
news:ee7a3b8.3@WebX.sUN8CHnE...
> I'm trying to solve a 3 variable linear equation using matrix
(LU-decomposition method). Anybody can shed light on how to do this in FPGA
hardware?
> Can FPGA do floating point?

Is this course work?

(Muzaffer Kal and Glen Herrmannsfeldt already gave good answers, as does
http://www.google.com/search?q=fpga+floating+point
http://groups.google.com/groups?q=fpga+floating+point)

You will have to take the algorithm, carefully note what sequence of
operations it applies, and then figure out how to implement that sequence of
operations in hardware, as a datapath and/or as some kind of sequential
machine.

It is also important to determine which elements of your specific problem
domain are *fixed* or *rarely changing* -- that can lead to massive savings
due to precomputation or strength reduction of operators.

An FPGA can do floating point, but it is rarely done.  In my opinion,
implementing floating point in an FPGA is considerably more work than
implementing an equation solver GIVEN an FPGA floating point implementation.
There are also some references to FPGA floating point papers at
fpgacpu.org/usenet/fp.html.

There are other number systems that may apply, but even there, some of the
numeric operators in LU decomposition may be a bit of work to implement.

I suspect it misses the point, but the simplest thing to do that addresses
the letter of your question, is get a Nios or Microblaze dev kit (first
checking they do indeed have floating point software or hardware libraries)
and compile the C code in section 2.3 of Numerical Recipes in C.  For both
Xilinx and Altera's DSP design environments, it may make sense to be able to
drop in a lightweight soft CPU core to handle arbitrary code blocks.

(As I understand it, Altera's Code:DSP
(http://www.altera.com/solutions/dsp/dsp-code_dsp.html) goes the other
way -- it allows you to design and implement Nios instruction set extensions
and/or peripherals via MATLAB/Simulink.  But similarly and recursively, you
may wish to stick a small CPU core into your Simulink signal processing
pipeline to do more general purpose signal processing.)

Jan Gray, Gray Research LLC



Article: 49355
Subject: Re: CLB numbers for various ops?
From: hmurray@suespammers.org (Hal Murray)
Date: Sun, 10 Nov 2002 20:22:09 -0000
Links: << >>  << T >>  << A >>
>Hmm, for a quick estimation I would say.
>
>2 LUTs can count then number of 1' in 1 4 bit vector (its just a simple 16x2
>Bit ROM)

Ray keeps reminding us to consider bit serial.  Might be a good fit
for this problem.  [Weird, once I started thinking that way I couldn't
figure out how to do it your way.]

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 49356
Subject: Re: CLB numbers for various ops?
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sun, 10 Nov 2002 21:52:27 +0100
Links: << >>  << T >>  << A >>
"Hal Murray" <hmurray@suespammers.org> schrieb im Newsbeitrag
news:ustfvhjnld8794@corp.supernews.com...
> >Hmm, for a quick estimation I would say.
> >
> >2 LUTs can count then number of 1' in 1 4 bit vector (its just a simple
16x2
> >Bit ROM)

uups.. I guess this more a 16x3 bit ROM, since the result can be 0,1,2,3,4
When I look at my posting, Iam afraid I was a little bit too quick.

We need 3 LUTs / 4bit conting + 7 3-Bit Adders -> 3*7 + 3*7 = 42 LUTs, same
number, different distribution.

Hmm, again the magic 42 . . . .

>
> Ray keeps reminding us to consider bit serial.  Might be a good fit
> for this problem.  [Weird, once I started thinking that way I couldn't

Not at all. ;-)
"that is set to a 1?  These operations are essential for traversing trie
data structures quickly in hardware."
This sounds to me that speed is important.

--
MfG
Falk




Article: 49357
Subject: Re: VersaRing
From: "John_H" <johnhandwork@mail.com>
Date: Sun, 10 Nov 2002 21:41:34 GMT
Links: << >>  << T >>  << A >>
A mention I got from a support person a couple years backs was that - at the
time - it seemed to be more marketing vapor than real "point a finger at
that and say wow" kind of feature. In the Virtex family (isn't that where
Versa-ring started?) there are the horizontal and vertical long lines and
the associated hex lines that go along each side. In the FPGA_EDITOR you can
see that these lines can connect to each other (directly or indirectly) in
the corners making it something of a ring. I've gone in to manually do some
routes that were poorly implemented (better results by driving one long line
into the many hex lines for a very wide fanout). While I can see where a
"marketing advantage" might have been seen by this topology, the reality is
probably that it's just decent routing resources and not the big advantage
someone once envisioned it to be.

"hristo" <hristostev@yahoo.com> wrote in message
news:b0ab35d4.0211100456.56c3bc53@posting.google.com...
> any input here Please
>
> --Hristo
> hristostev@yahoo.com (hristo) wrote in message
news:<b0ab35d4.0211051151.417f419b@posting.google.com>...
> > Hello,
> > Could someone please explain more the VersaRing utility?
> > i know it is the routing ressources which allow connecting the IOBs to
> > CLBs
> > is it so performant and quick such that i don't have to bother myself
> > too much about the design padding
> >
> > thanks



Article: 49358
Subject: Re: functional test for Xilinx virtex II Pro
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Sun, 10 Nov 2002 23:04:13 +0000 (UTC)
Links: << >>  << T >>  << A >>
Peter Alfke <peter@xilinx.com> wrote:
: Max, why do you want to test the chip yourself ? Xilinx has done that for
: you, throwing millions of test vectors at the chip. Test development is a
: major, major design effort, and I do not understand why you want to
: duplicate it. Do like all other customers, trust us...:-)
: BTW, would you ever consider testing a Pentium chip???

If as a manufacturere of a board I solder Pentium chips to a board, I think
I should check that everything got soldered and there are no shorts or opens.

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 49359
Subject: rs encode
From: Zhenglin <zdzlin@163.com>
Date: Sun, 10 Nov 2002 17:27:18 -0800
Links: << >>  << T >>  << A >>
Who has the RS encode core, I want to buy one for my friends?

Article: 49360
Subject: Re: LU-decomposition
From: "glen herrmannsfeldt" <gah@ugcs.caltech.edu>
Date: Mon, 11 Nov 2002 02:59:56 GMT
Links: << >>  << T >>  << A >>

"fireball" <sensen@swirvemail.com> wrote in message
news:ee7a3b8.3@WebX.sUN8CHnE...
> I'm trying to solve a 3 variable linear equation using matrix
(LU-decomposition method).
> Anybody can shed light on how to do this in FPGA hardware?
>
> Can FPGA do floating point?

OK, only 3 variables, so you have a chance.

Why do you want to do it in an FPGA?  Do you need to
do this operation 100 million times/second?

I would only try to do it in an FPGA if I really needed to do
many of them in a row, in a short amount of time.

If I didn't need so many done, I would design a simple processor
and program that processor with the algorithm.   Depending on
the available hardware (money) and how fast the result is needed
will determine how the design should be done.

-- glen



Article: 49361
Subject: Re: rs encode
From: "Kevin Neilson" <kevin_neilson@removethistextattbi.com>
Date: Mon, 11 Nov 2002 03:52:21 GMT
Links: << >>  << T >>  << A >>
Memec Design Services:
www.memecdesign.com

"Zhenglin" <zdzlin@163.com> wrote in message
news:ee7a44f.-1@WebX.sUN8CHnE...
> Who has the RS encode core, I want to buy one for my friends?



Article: 49362
Subject: EDIF generation from XST of ISE 5.1i
From: "Young-Su Kwon" <yskwon@vslab.kaist.ac.kr>
Date: Mon, 11 Nov 2002 13:39:49 +0900
Links: << >>  << T >>  << A >>

Is there anyone who have used ISE 5.1i?
I have used ISE 4.2i previosly and succeeded to generate EDIF from XST,
but XST of ISE 5.1i does not generate EDIF file.
Does anyone know how to generate EDIF from XST of ISE 5.1i?


--

*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
Young-Su Kwon,
E-mail : yskwon@vslab.kaist.ac.kr
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*




Article: 49363
Subject: Re: VersaRing
From: kayrock66@yahoo.com (Jay)
Date: 10 Nov 2002 21:27:02 -0800
Links: << >>  << T >>  << A >>
Marketing hype.

President, Quadrature Peripherals
Altera, Xilinx and Digital Design Consulting
email: kayrock66@yahoo.com
http://fpga.tripod.com
-----------------------------------------------------------------------------hristostev@yahoo.com (hristo) wrote in message news:<b0ab35d4.0211100456.56c3bc53@posting.google.com>...
> any input here Please
> 
> --Hristo
> hristostev@yahoo.com (hristo) wrote in message news:<b0ab35d4.0211051151.417f419b@posting.google.com>...
> > Hello,
> > Could someone please explain more the VersaRing utility?
> > i know it is the routing ressources which allow connecting the IOBs to
> > CLBs
> > is it so performant and quick such that i don't have to bother myself
> > too much about the design padding
> > 
> > thanks

Article: 49364
Subject: Re: FPGA convert to ASIC
From: Muzaffer Kal <kal@dspia.com>
Date: Mon, 11 Nov 2002 06:20:20 GMT
Links: << >>  << T >>  << A >>
On 4 Nov 2002 08:43:53 -0800, prashantj@usa.net (Prashant) wrote:

>Jay,
>That was very informative and I had a question for you. When you say
>"a large FPGA design into a small ASIC and 4x speedup", are there any
>constraints to it OR will all designs of FPGA result into such a
>speedup and area reduction. I understand why the area reduction and
>speedup occur. Its just the factor by which they occur that I'm not
>sure about. What would you say for a design that uses 20,000 LEs in an
>Altera Apex20K1500E device and about 40,000 bits of internal RAM
>working @ 40 MHz ? Would such a design speed up 4 times when converted
>to ASIC ? I understand that the speed up numbers would vary from
>design to design. But there must be a minimum and maximum possible
>numbers ? Interested in your comments.

In my experience the scale is from 3 to 5 times speed increase and it
depends on what you can get from the fpga. With Apex20 and 40 MHz, it
is very likely that you can get at least 150MHz with a .25u process
and 200 MHz from a .18u process. It also is limited by the maximum
speed one can get from a SC (standard cell) methodology. With .25u
that's more or less limited to 300MHz unless you do very small blocks
and do manual placement etc etc so it is very difficult to get a 4x
improvement for any fpga design above 80 MHz. With .18u the maximum is
around 400 MHz. These are again assuming designs done by "regular"
designers. If design is RLOC'ed to the limit with only one close LUT
between two flops then probably you can't make it more than 2x faster.
It also depends on what process the fpga is running. Virtex II is done
with a .13u copper process so any SC flow above .25u won't be too
competitive. If you do full custom with dynamic circuit design, of
course, all bets are off. Intel and AMD had designs running at 1GHz on
their .25u processes.


Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations

Article: 49365
Subject: Re: Which PCI-IO-Chip manufacturer to prefer?
From: Markus Wolfgart <xx_markus.wolfgart@dlr.de>
Date: Mon, 11 Nov 2002 07:21:27 +0100
Links: << >>  << T >>  << A >>
Hi Steen,

thanks for your reply on my posting.
Concerning some emails i get on this topic and
the other answers in the german news group electronics.sci.de
the best choice probably would by the PLX9054 for my
purpose. In the beginning of my quest for a suitable pci-io-chip
I would like to take the PLX9030 (bigger buffers, more regs,
greater serial config prom, pci 2.2 compliant, but unfortunately 
a smaller case and smaller pitch, so that soldering would by more 
difficult by hand.

I will take a look on www.tech-forge.com to see your prototype.

best regards

markus

Article: 49366
Subject: Re: Compiling Altera Nios Designs
From: Prager Roman <rprager@frequentis.com>
Date: Mon, 11 Nov 2002 07:30:35 GMT
Links: << >>  << T >>  << A >>
Thomas Pollischansky <polly@rz.fh-augsburg.de> wrote:
> Thanks for the answer - I'm using the apex20ke200 on the nios
> evaluation board - but the problem is in the compiling stage. When I'm
> compiling a NIOS design (with nothing but a processor) the compiler
> reports, that it has used about 1800 LEs but 0 RAM bits.
> Thomas
Have you tried to synthesize the demo projects? All the ones with "minimal"
in the project name use internal RAM. Lets have a look whether they work.

Roman

Article: 49367
Subject: Re: Unexplained signal interaction
From: kayrock66@yahoo.com (Jay)
Date: 10 Nov 2002 23:32:31 -0800
Links: << >>  << T >>  << A >>
All the pins share a supply bus.  If your output is driving an
excessive load, or your I/O supply bus is not sufficiently bypassed,
then you could be glitching the supply.  For an input, the threshold
is related (roughly proportional) to the supply so as you pull the
positive supply down, it could be moving the threshold enough to cause
a false clock transition.

Regards

President, Quadrature Peripherals
Altera, Xilinx and Digital Design Consulting
email: kayrock66@yahoo.com
http://fpga.tripod.com
-----------------------------------------------------------------------------"Stevenson" <NOSPAMstevenson@infinito.it> wrote in message news:<hNnz9.12125$8E3.360158@twister2.libero.it>...
> Dear all,
> some week ago I built a prototype board for an experimental setup using an
> FPGA Xilinx XC4003E (yes, I know, it's a quite old part! But it was
> sufficient for our sake...).
> I noticed that certain configuration I used presented a strange behaviour
> related to some I/O pin. In particular I used pin 51 (that is an I/O, SGCK3,
> GCK5) as input for a clock signal (with a BUFGS) and pin 72 (that is an I/O,
> SGCK4, GCK6 and DOUT) as an output for serial data.
> The unexpected fact was that every time on pin 72 there was a transition in
> the data stream from 0 to 1 the circuit implemented seemed to respond as a
> clock pulse was received.
> I tried many different configurations, but all presented this behaviour (if
> pin 51 and 72 was used).
> 
> It exists some kind of link between these pins?
> It is possible to avoid this effect?
> 
> Thanks to all.
> 
> Stevenson

Article: 49368
Subject: Re: Quicklogic PAsic problem
From: kayrock66@yahoo.com (Jay)
Date: 10 Nov 2002 23:42:46 -0800
Links: << >>  << T >>  << A >>
Speaking generally, for a combinational output, there is no guarantee
of constant output before the circuit has settled after each clock
edge.  Most likely your glitch is being generated by the different
propagation delays thtough your combinational logic.  If you want to
guarantee a non-glitching output, you need to register it.

Regards

President, Quadrature Peripherals
Altera, Xilinx and Digital Design Consulting
email: kayrock66@yahoo.com
http://fpga.tripod.com
-----------------------------------------------------------------------------
paul.lee@sli-institute.ac.uk (Paul) wrote in message news:<9aeb7852.0211060920.46c03e31@posting.google.com>...
> Hi all
> 
> I am trying to understand a problem with one of my output in my
> design. I am currently using a PASIC 1 device with 84 pins. When I
> probed one of the pins which is normally high it gave a 50 ns low
> pulse. I have tried simulating the condition in Modelsim but I don't
> seem to be able to get the similar result.
> 
> The signal is produced by small combinatorial and sequential logic and
> then before the output port, the result from the logic have to be
> inverted. I have removed the inverter and change some of the logic and
> this seem to have remove the 50 ns pulse.
> 
> Could someone please explain this condition.
> 
> Regards
> 
> Paul

Article: 49369
Subject: How much to build this? xvga to ntsc uhf broadcaster
From: whimsica@aol.com (dan)
Date: 11 Nov 2002 00:00:48 -0800
Links: << >>  << T >>  << A >>
I want to take a 1920x1440 rgb output, Break it up into 9 640x480
pieces, and broadcast each piece to a separate uhf channel.

How much would it cost to build something like that.
What kinds of skills would a person need to have?

It's for a science project


Daniel Savage
lakeside school district

Article: 49370
Subject: Re: FPGA convert to ASIC
From: kayrock66@yahoo.com (Jay)
Date: 11 Nov 2002 00:01:40 -0800
Links: << >>  << T >>  << A >>
Those are rule of thumb numbers so people can get some idea of what
reality is instead of saying something nebulous like "speeds and
densities in conversions will vary so I'm not going to tell you
anything specific".  That always drives me nuts when I get that kind
of smoke blowing.

President, Quadrature Peripherals
Altera, Xilinx and Digital Design Consulting
email: kayrock66@yahoo.com
http://fpga.tripod.com
-----------------------------------------------------------------------------

prashantj@usa.net (Prashant) wrote in message news:<ea62e09.0211040843.77bc0a81@posting.google.com>...
> Jay,
> That was very informative and I had a question for you. When you say
> "a large FPGA design into a small ASIC and 4x speedup", are there any
> constraints to it OR will all designs of FPGA result into such a
> speedup and area reduction. I understand why the area reduction and
> speedup occur. Its just the factor by which they occur that I'm not
> sure about. What would you say for a design that uses 20,000 LEs in an
> Altera Apex20K1500E device and about 40,000 bits of internal RAM
> working @ 40 MHz ? Would such a design speed up 4 times when converted
> to ASIC ? I understand that the speed up numbers would vary from
> design to design. But there must be a minimum and maximum possible
> numbers ? Interested in your comments.
> 
> Thanks,
> Prashant
> 
> 
> 
> kayrock66@yahoo.com (Jay) wrote in message news:<d049f91b.0211011522.4fd5cec2@posting.google.com>...
> > I've done a few FPGA prototypes of designs that we knew in advance
> > were going to be ASICs.  We used TSMC and IBM.  I never heard the
> > price on the TSMC and I think IBM was charging something like $400k
> > for chip #1.  However, expect foundries to be very agreeable these
> > days on account of the surplus capacity.  The results went fine,
> > because usually, by the time you've worked out all the bugs to get the
> > FPGA to work in the lab, you've solved most of your problems. Also
> > FPGA use sort of forces a certain level of simplicity with repect to
> > clocking.   A BIG FPGA turns into a small ASIC because of the
> > difference in area efficiency.  Also, expect about a 4X speed-up going
> > to ASIC.  And of course, yes you can hand place, super pipeline,
> > embedded multiplier, etc your FPGA to get a faster design, but I'm
> > speaking in general for random logic writen by your average ASIC
> > designer, not spending all the time to get so deep into the
> > implimentation details.
> > 
> > President, Quadrature Peripherals
> > Altera, Xilinx and Digital Design Consulting
> > email: kayrock66@yahoo.com
> > http://fpga.tripod.com
> > -----------------------------------------------------------------------------
> > 
> > 
> > 
> > "alla" <alng23@hotmail.com> wrote in message news:<aps669$cdd$1@tilde.itg.ti.com>...
> > > Just want see anyone here has any experience of converting a Xilinx FPGA
> > > design into an ASIC implementation. If so, which vendor did you use? What's
> > > the cost? Are you happy with the result? We are using the Virtex series and
> > > considering this option. Thanks

Article: 49371
Subject: Re: LU-decomposition
From: fireball <sensen@swirvemail.com>
Date: Mon, 11 Nov 2002 00:04:08 -0800
Links: << >>  << T >>  << A >>
Basically i'm doing a per pixel calculation for the whole panel. Each pixel will a 3x3 matrix coefficient whereby i'll need to solve for let's say variable x,y,z.

DSP could be an alternative but the processing cannot be done in parallel with localized memory for each pixel.

fixed point is fine with me as long as i know how to scale an offset to it.

For start, i don't need to do it really fast but if i have a dynamic data being fed to the system, then panel will need to be refresh quickly.

I'm a newbie using xilinx so i don't know what is nios about. i've ordered a normal virtex-II dev board. i didn't use a normal uC as there is not enought I/Os available.

i guess if LU-decomposition is that hard then i'll do it the long way of solving inverse matrix A by calculating the cofactors..etc. Is this advisable?

Right now i'm figuring how to use the block selectRAM to store the coef. Anybody has experience or simple example of doing this?

Any other suggestions is most welcomed. Thanks.

Article: 49372
Subject: Re: Quicklogic PAsic problem
From: hmurray@suespammers.org (Hal Murray)
Date: Mon, 11 Nov 2002 08:19:28 -0000
Links: << >>  << T >>  << A >>
>Speaking generally, for a combinational output, there is no guarantee
>of constant output before the circuit has settled after each clock
>edge.  Most likely your glitch is being generated by the different
>propagation delays thtough your combinational logic.  If you want to
>guarantee a non-glitching output, you need to register it.

I think Xilinx used to guarantee no glitches on their LUTs if you
only changed one input at a time.  That is if you change one input,
the output will either stay the same or make a clean transition.

[Makes sense if they use a tree of 2 input MUXes and take some care
with the basic MUX.]

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Article: 49373
Subject: Re: Altera MAX7000E (EPM7128ELC84) - programmer?
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 11 Nov 2002 08:41:13 +0000
Links: << >>  << T >>  << A >>
"Philip Pemberton" <philpem@btinternet.com> writes:

> Hi,
>     I've just bought an Altera EPM7128ELC84-10 EPLD for the knock down price
> of 5 at a radio rally (hamfest). Does anyone know of a suitable programmer
> for this thing? Altera's datasheet says it can't be programmed in-system -
> does this mean I can't program it with a Byteblaster?

I believe that in-situ programming started with the 7000S series, so
unfortunately you can't.  It hasn't got the right pins for a
ByteBlaster :-(

Sorry!

Martin

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt

Article: 49374
Subject: Re: Xilinx POS Power On Surge Current
From: "Jock" <ian.mcneil@uk.thalesgroup.com>
Date: Mon, 11 Nov 2002 09:33:03 -0000
Links: << >>  << T >>  << A >>

"Geoffrey Furman" <geoff_furman@iisvr.com> wrote in message
news:urdv6qkh82hlfb@corp.supernews.com...
> Does anyone have real world experience with this.  The spec is outrageous
> for the SpartanII / IIE /Virtex families.
> I could get no detailed information from Xilinx which helped.
> I build low power systems with very tight packaging constraints and don't
> believe that it is possible to power up one of these devices.
>
> Please comment on your successes and failures.  This issue needs to be
> brought out in the open
>

Has anyone had the same problem on Altera Flex 6000 series? I'm getting a
Reset current in excess of 250mA.






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