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Hi all, I'm using an FPGA board with an APEX20K1500E on it. My design produces 60,000 output values whch are stored in an external to FPGA on-board RAM. Then these values are read out onto the PC using the serial port. The production of the 64000 values is a repetitive process. When the data has been read onto the PC, I find one of the 60,000 values to be incorrect. But the index of the incorrect value changes everytime I rerun the code on the board. for e.g. in one run the 32,010th value could be wrong and the next run could have the 1,784th value could be wrong. The code is the same and so are the input values. The output should remain the same, but instead has an erroneous value for one of the 60,000 values. I dont think the code is wrong since the error is not consistent and sometimes not there. (But I'm still working on it as if something's wrong with the code). Anyone have any ideas on what could be wrong ? I understand I may not be giving enough information, but I thought I would give it a try, in case anyone had a similar (wierd) problem earlier. Thanks, PrashantArticle: 49576
ted wrote: > > > For example time taken (say as a proportion) for paper design, coding > and simulation. > > How much time should be allocated to simulation? > I think for high-end designs, the time that you spend for simulation should be 3 or 4 times the time that you spent for coding. -- Tullio Grassi ====================================== Univ. of Maryland - Dept. of Physics College Park, MD 20742 - US Tel +1 301 405 5970 Fax +1 301 699 9195 ======================================Article: 49578
"Prashant" <prashantj@usa.net> schrieb im Newsbeitrag news:ea62e09.0211151314.37041ecb@posting.google.com... > Hi all, > > I'm using an FPGA board with an APEX20K1500E on it. My design produces > 60,000 output values whch are stored in an external to FPGA on-board > RAM. Then these values are read out onto the PC using the serial port. > The production of the 64000 values is a repetitive process. > > When the data has been read onto the PC, I find one of the 60,000 > values to be incorrect. But the index of the incorrect value changes > everytime I rerun the code on the board. for e.g. in one run the > 32,010th value could be wrong and the next run could have the 1,784th > value could be wrong. A lot of things can go wrong. Is the design fast enough to reach your clocking spped? Timing analyzer. Is it a clean synchronous design? On the connection to the external (SD)RAM, there might be signal integrity issues. Ringing, Ground Bounce?? Is the error introduced on the way to the PC via RS232?? Run you RS232-FPGA connection in a endless loop and feed it with a PRBS sequence, preferably a long one (2^15-1 or bigger) Compare the incomming bitsequence with the expected (calculated) values. If this runs fine, extend your data-loop to other regions of the circuit (data handling etc.) until everything (also the RAM) is inside the data-loop. -- MfG FalkArticle: 49579
> > I also believe this ability is somewhat tool specific? Are the mapping and > > placement abilities of HDLs cross tool abilities? > > > Is there a schematic file format that crosses tool boundaries? I believe there are some schematic translators, and possibly EDIF, but not really seamlessly, as it is an acknowledged deficiency of schematic tools. That was the point I was making about HDLs, that, depending on how much "tool specific" things your design contains/relies on, that then becomes the same issue to some degree. AustinArticle: 49580
Hi I create a schmatic symbol in ECS in foundation 3.1i, synthesize is passed, but when i simulate it in MODELSIM an error occured that is it can not find vertex_macro library, but when i map the library in FPGA library manager, i cannot find this library in it, there are only simprim and unisim and logibox library, if the file of fpgavender_xilinx.tcl is outdated? thanks xieArticle: 49581
In one of my early designs I remember being confused by inconsistent results. I forgot to deal with an asynchronous event properly when I wrote some control values into a register with a different clock than the system clock. The control register most often got all the bits on the same clock, but sometimes the bits straddled the clock edge leaving some new bits and some old bits in the register. Check for anything that's asynchronous to your clock and make sure you properly deal with transferring data into your clock domain(s). "Prashant" <prashantj@usa.net> wrote in message news:ea62e09.0211151314.37041ecb@posting.google.com... > Hi all, > > I'm using an FPGA board with an APEX20K1500E on it. My design produces > 60,000 output values whch are stored in an external to FPGA on-board > RAM. Then these values are read out onto the PC using the serial port. > The production of the 64000 values is a repetitive process. > > When the data has been read onto the PC, I find one of the 60,000 > values to be incorrect. But the index of the incorrect value changes > everytime I rerun the code on the board. for e.g. in one run the > 32,010th value could be wrong and the next run could have the 1,784th > value could be wrong. > > The code is the same and so are the input values. The output should > remain the same, but instead has an erroneous value for one of the > 60,000 values. I dont think the code is wrong since the error is not > consistent and sometimes not there. (But I'm still working on it as if > something's wrong with the code). > > Anyone have any ideas on what could be wrong ? I understand I may not > be giving enough information, but I thought I would give it a try, in > case anyone had a similar (wierd) problem earlier. > > Thanks, > PrashantArticle: 49582
Hello, after reading the app notes about the DLL i am a little bit confused(i am speaking about Virtex-e). I believe that the DLL does NOT minimise the clock skew, in fact, this is dealt with the dedicated clock routing ressources. the DLL eliminates the delay between the the external input port to the individual clock load ? but just wondering is this really important? i always taught that the important thing is to have a very low clock skew . any explanations? also in many app notes they refer to the resolution ~200ps, what this stand for? a general remark, i see such paragraphs in app notes so misleading "DLL can eliminate clock skew by monitoring the input clock and the distributed clock, by automatically adjusting a clock delay element"Article: 49583
If you define skew as the delay between the clock input to flops across the chip, then no, the DLL doesn't eliminate skew. Although that sort of skew is really low anyway because the Xilinx clock tree has been designed very well to minimize this. The DLL, like you say, subtracts the delay due to the clock tree, so that the clock arrives at the flop at the same time it arrives at the clock input pin. -Kevin "Anonymous4" <nicemanYep@yahoo.co.uk> wrote in message news:f9028e31.0211151808.22a129b9@posting.google.com... > Hello, > after reading the app notes about the DLL i am a little bit confused(i > am speaking about Virtex-e). > > I believe that the DLL does NOT minimise the clock skew, in fact, this > is dealt with the dedicated clock routing ressources. the DLL > eliminates the delay between the the external input port to the > individual clock load ? > > but just wondering is this really important? i always taught that the > important thing is to have a very low clock skew . > > any explanations? > also in many app notes they refer to the resolution ~200ps, what this > stand for? > > a general remark, i see such paragraphs in app notes so misleading > "DLL can eliminate clock skew by monitoring the input clock and the > distributed clock, by automatically adjusting a clock delay element"Article: 49584
In article <f9028e31.0211151808.22a129b9@posting.google.com>, Anonymous4 <nicemanYep@yahoo.co.uk> wrote: >Hello, >after reading the app notes about the DLL i am a little bit confused(i >am speaking about Virtex-e). > >I believe that the DLL does NOT minimise the clock skew, in fact, this >is dealt with the dedicated clock routing ressources. the DLL >eliminates the delay between the the external input port to the >individual clock load ? Correct. The clock tree is designed so that every point on the clock net sees (effectively) the same skew. The DLL is designed so that the relative skew between the internal clock tree and the external clock source is effectively 0, by digitally delaying the clock. >but just wondering is this really important? i always taught that the >important thing is to have a very low clock skew . Both are important. Absolute skew is important within the fabric, but the interface really depends on skew between the internal clock and the external. >any explanations? >also in many app notes they refer to the resolution ~200ps, what this >stand for? DLLs have "jitter", where the clock edge may move forward and backwards by 200ps relative to the input clock. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 49585
>I believe that the DLL does NOT minimise the clock skew, in fact, this >is dealt with the dedicated clock routing ressources. the DLL >eliminates the delay between the the external input port to the >individual clock load ? > >but just wondering is this really important? i always taught that the >important thing is to have a very low clock skew . You need/want something like a DLL in order to reduce the clock to output to the external world if the specs are written relative to the clock input pin. For example, consider the PCI specs. Similarly, a DLL reduces the input hold time requirements at the first FF for getting data into a chip. (Older Xilinx chips had an explicit delay in the IOB input path to cover the clock distribution so the specs could say 0 hold time, and then an option to bypass it for cases where they had lots of hold time but didn't have enough setup time. Your comment about the skew is also important. You need the skew between (say) FFs next to eachother but connected to different branches of the clock tree to be low enough so that the worst case clock-out covers the worst case hold time when you have worst case skew. The DLL doesn't help that. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 49586
Hal, > You need/want something like a DLL in order to reduce the clock > to output to the external world if the specs are written relative > to the clock input pin. For example, consider the PCI specs. BZZZZZZZZZ...ZZZZZZZ...ZZZT. Lost your thinking cap, I see ;-) Consider the PCI spec all right, it wants the clock to go down to DC, and if I don't miss my guess, the DLLs won't work in that range... AustinArticle: 49587
>BZZZZZZZZZ...ZZZZZZZ...ZZZT. Lost your thinking cap, I see ;-) Consider >the PCI spec all right, it wants the clock to go down to DC, and if I don't >miss my guess, the DLLs won't work in that range... Good catch. Thanks. Didn't they "fix" that in some rev? I think the reasoning was to allow PLLs. There is also the complication of spread spectrum clocking. I think that stuff is now reasonably well standardized so the DLL/PLL just needs to be agile enough to track the dancing clock. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 49588
Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote: > Has Xilinx said anything about future versions of WebPack being able > to support the 2VP4? It seems a shame that it doesn't support at > least one part that actually contains a PowerPC processor. The number Why wouldn't you buy the tools if using such a high-end part? Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 49589
At a recent Xilinx seminar one of the presenters showed a slide describing PicoBlaze and CoolBlaze simple 8 bit cores for Xilinx products. Looking at the XIlinx site, I only find a mention about Picoblaze, no mention at all about CoolBlaze. Google produced no results whatsoever. Is Coolblaze a real product? If not why was it shown on the slides? PS we have a need for such a product, hence the asking! theoArticle: 49590
It is usually good (either for schematic design and for board routing) to "group" similar signals - buses, enables and so on - as they are placed on adjacent pins of CPLD/FPGA. Is there some 'automatic' way to do this? As far as I have seen, with the constraints editor you can define groups with common timing restrictions, but there is nothing able to tell ISE something like: "this is a group of pins, you can place them where you like but they must be as ordered and adjacent as possible". -- LorenzoArticle: 49591
Hi all, I am relatively new to fpga design, and I am experiencing a problem with global clock routing. I am using ISE v5.1 targeting a Xilinx x2v500fg456 device. The point is that my design uses some (slow) signals to edge-trigger different internal registers. When it comes to the place & route phase, the tool tries to consider all those signals as global clocks and fails the routing. Apart from modifying the design by avoiding edge-triggering on those signals, is it possible to force the P&R tool not to route the signals as global clocks? By the way, the signals are internally generated, they are not external inputs. Thanks in advance, best regards. Mirko Scarana PhD Student "La Sapienza" University of Rome -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 49592
Mirko Scarana <mirko.scarana@tiscali.it> wrote: : Hi all, : I am relatively new to fpga design, and I am experiencing a problem with : global clock routing. : I am using ISE v5.1 targeting a Xilinx x2v500fg456 device. : The point is that my design uses some (slow) signals to edge-trigger : different internal registers. : When it comes to the place & route phase, the tool tries to consider all : those signals as global clocks and fails the routing. : Apart from modifying the design by avoiding edge-triggering on those : signals, is it possible to force the P&R tool not to route the signals : as global clocks? : By the way, the signals are internally generated, they are not external : inputs. : Thanks in advance, best regards. There is no such things as "(slow) signals" inside the chip. Every gate switches at maximum speed. If the registers that you switch with your "slow" signal have somehow a feedback path the input of another register clocked with the same clock, you will need the clock signal routed with the global network or otherwise different clock routing delays to the different registers will break your design (register 1 has changed the output and therefore the input to register 2 before the register 2 has seitched). Clocking register 1 and 2 with a fast clock and using the slow signal as clock enable is one possible way to circumvent this problems. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 49593
This is not good synchronous design practice. Instead, consider clocking
all your logic from a common clock, and then use a synchronous edge detect
(signal and'd with inverted signal delayed by 1 clock) as a clock enable to
the register you were previously clocking with a logic signal.
Mirko Scarana wrote:
> Hi all,
> I am relatively new to fpga design, and I am experiencing a problem with
> global clock routing.
> I am using ISE v5.1 targeting a Xilinx x2v500fg456 device.
> The point is that my design uses some (slow) signals to edge-trigger
> different internal registers.
> When it comes to the place & route phase, the tool tries to consider all
> those signals as global clocks and fails the routing.
> Apart from modifying the design by avoiding edge-triggering on those
> signals, is it possible to force the P&R tool not to route the signals
> as global clocks?
> By the way, the signals are internally generated, they are not external
> inputs.
> Thanks in advance, best regards.
>
> Mirko Scarana
> PhD Student
> "La Sapienza" University of Rome
>
> --
> Posted via Mailgate.ORG Server - http://www.Mailgate.ORG
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49594"Hal Murray" <hmurray@suespammers.org> wrote in message news:utbr6h65fg6sd9@corp.supernews.com... > >BZZZZZZZZZ...ZZZZZZZ...ZZZT. Lost your thinking cap, I see ;-) Consider > >the PCI spec all right, it wants the clock to go down to DC, and if I don't > >miss my guess, the DLLs won't work in that range... > > Good catch. Thanks. Hey, Hal...no problem! > Didn't they "fix" that in some rev? Of the PCI spec of the Xilinx part ;-) > I think the reasoning was to allow PLLs. There is also the complication > of spread spectrum clocking. I think that stuff is now reasonably well > standardized so the DLL/PLL just needs to be agile enough to track > the dancing clock. In reality, no system on the market that I am aware of (embedded not included) ever stops the clock. I have seen some systems have the PCI clock be based on some multiple of the memory clock...but that's established before the system is powered on, so it doesn't change. Regards, AustinArticle: 49595
Falk Brunner wrote: > > "rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag > news:3DD4AEEE.F91B76D3@yahoo.com... > > It has been awhile since I have looked at any of the numbers for FPGA FF > > metastability. Can anyone point me to data on the XC2S family, Spartan > > II? I believe this can be boiled down to a simple graph for a given > > clock rate product (or input change rate and FF clock rate) and a graph > > of the particular FFs in question. I know there is also an equation, > > but a graph is so simple to use and can help to explain it to others. > > > > Is there any difference in coefficients between the internal CLB FFs, > > the shift register FFs, the IOB FFs and any others that I may have > > missed? Have all of these been characterized for metastability? > > Have a look at the latest techXclusive from Peter Alfke, where he provides > numbers and graphs for Virtex-IIPRO. As far as I remember there is also a > graph with the 4 k Series, so Spartan-II should be somewhere inbetween. I am not familiar with the techXclusive, can you provide a URL? I found the chart for the 4K, but have seen nothing more recent. I remember Peter saying he would be measuring some of the more current parts. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 49596
>I am not familiar with the techXclusive, can you provide a URL? http://support.xilinx.com/support/techxclusives/metas-techX32.htm -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 49597
>> Didn't they "fix" that in some rev? > >Of the PCI spec of the Xilinx part ;-) I thought they updated the PCI spec to allow PLL clock buffers. I might be thinking of something else. What's a good example that many people will be familiar with to illustrate needing a fast clock-out where a DLL would help? >In reality, no system on the market that I am aware of (embedded not >included) ever stops the clock. I have seen some systems have the PCI clock >be based on some multiple of the memory clock...but that's established >before the system is powered on, so it doesn't change. What does Xilinx do in their PCI core? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 49598
hi :-), I read that the Virtex family constitutes the 4th Xilinx FPGA generation. My first guess is that: 1- The 1st generation comprises Xc2k,Xc3k and (Xc5k?). 2- The 2nd generation consists on the Xc4k. 3- The 3rd generation consists on the Xc6k (fine grain architecture ) 4- The 4th generation consists on the Virtex family (owing SoC implementation) Can anyone please highlight what was the " jump on the built-in features" between two successive generations ? can really the Xc5k be considered among the 1st category members? where Spartan family position lies on? can we consider the Virtex-Pro the 5th generation? thanks ;-)Article: 49599
> >In reality, no system on the market that I am aware of (embedded not > >included) ever stops the clock. I have seen some systems have the PCI clock > >be based on some multiple of the memory clock...but that's established > >before the system is powered on, so it doesn't change. > > What does Xilinx do in their PCI core? I haven't checked what they would do in a Virtex...but I do nothing, just take the timing into account in my TIMESPECs. Regards, Austin
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