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Greetings This is semimonthly announcement of Verilog FAQ. Verilog FAQ is located at http://www.parmita.com/verilogfaq/ Alternate Verilog FAQ is an attempt to gather the answers to most Frequently Asked Questions about Verilog HDL in one place. It also contains list of publications, services, and products. Alternate Verilog FAQ is divided into three logical parts. Part 1 : Introduction and misc. questions Part 2 : Technical Topics Part 3 : Tools and Services What's New section outlines the changes in different versions and announcements. Links connects you to related informative links in internet. Your suggestions to make this FAQ more informative are welcome. Rajesh Bawankule (Also Visit Verilog Center http://www.parmita.com/verilogcenter/index.html )Article: 49401
Mike Treseler wrote: > > Phil Hays wrote: > > > Austin Franklin wrote: > > >>That's simply not true. The Alpha CPUs were designed using schematic capture > > > ... by a large building full of designers. > > Who no longer work for Digital Equipment Corp. Yea. But fairness requires me to point out that schematic entry wasn't the reason why DEC failed. -- Phil HaysArticle: 49402
Hi folks, Does anybody have any experience, stories, or thoughts to share regarding the implementation of small associative memory (AM) arrays in FPGAs? For example designing a memory management unit to support virtual memory on a softcore processor - a modest-sized bank of AM to support the page table lookup would be a good thing. On a similar note, I was speculating last night about multiported RAM banks in Xilinx FPGAs - am I right in thinking that you could just string several dual-port RAMs in parallel and do some trickiness with muxing the address/data lines for the "two sides" of each DP RAM? Regards, JohnArticle: 49403
"RTL" stands for Register Transfer Level. As opposed to gate level or transistor level. I think a lot of people might make a statement like "I used a Hardware Description Language to code my design at the Register Transfer Level." Of course that statement is a bit redundant, because the idea of coding at the gate level or transistor level using an HDL doesn't make much sense. -Stan "Anonymous4" <nicemanYep@yahoo.co.uk> wrote in message news:f9028e31.0211111347.2bc4c99c@posting.google.com... > Hello, > Basic Question i know but confused on: > what is the difference between Hardware Description Language (HDL) and Register > Transfer Logic(RTL) > ThanksArticle: 49404
Fully associative memory is probably not needed for a memory management unit. Try putting, say, four memories in parallel, and let the page match to any one of the four. Or two or eight or three, or any number for that matter. The improvement in hit rate going from four-way "set associative" to the same number of entries but fully associative is probably not measurable, yet a heck of a lot easier to implement. -Stan "John Williams" <j2.williams@qut.edu.au> wrote in message news:3DD05E2E.8D42E035@qut.edu.au... > Hi folks, > > Does anybody have any experience, stories, or thoughts to share > regarding the implementation of small associative memory (AM) arrays in > FPGAs? > > For example designing a memory management unit to support virtual memory > on a softcore processor - a modest-sized bank of AM to support the page > table lookup would be a good thing. > > On a similar note, I was speculating last night about multiported RAM > banks in Xilinx FPGAs - am I right in thinking that you could just > string several dual-port RAMs in parallel and do some trickiness with > muxing the address/data lines for the "two sides" of each DP RAM? > > Regards, > > JohnArticle: 49405
Sorry to go so far off topic, but you did it first. The Pentium problem was a DESIGN bug. This thread is about testing for MANUFACTURING defects! -Stan "rk" <stellare@NOSPAMPLEASE.erols.com> wrote in message news:Xns92C0D5BCB4E0Erk@199.184.165.240... > Peter Alfke wrote: > > [ snip ] > > > Do like all other > > customers, trust us...:-) BTW, would you ever consider testing a > > Pentium chip??? > > Couldn't resist: > > http://www.ku.edu/cwis/units/IPPBR/pentium_fdiv/pentgrph.html > > Now back to our regularly scheduled program. > > -- > rk, Just an OldEngineer > "A good engineer gets stale very fast if he doesn't keep his hands > dirty." -- Wernher von Braun, 1964 >Article: 49406
If you want to test for soldering and other board-level defects, use JTAG -that's what it's for. -Stan "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:aqmolc$h39$1@news.tu-darmstadt.de... > Peter Alfke <peter@xilinx.com> wrote: > : Max, why do you want to test the chip yourself ? Xilinx has done that for > : you, throwing millions of test vectors at the chip. Test development is a > : major, major design effort, and I do not understand why you want to > : duplicate it. Do like all other customers, trust us...:-) > : BTW, would you ever consider testing a Pentium chip??? > > If as a manufacturere of a board I solder Pentium chips to a board, I think > I should check that everything got soldered and there are no shorts or opens. > > Bye > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 49407
Sure. Figure out how you'd do it by hand. Then implement the steps using hardware primitives like addition and multiplication. Division can be done with a sequential circuit... alternatively, approximate division can be done by taking a reciprocal and multiplying. If your precision allows it, reciprocals can be done in a ROM lookup. "fireball" <sensen@swirvemail.com> wrote in message news:ee7a3b8.-1@WebX.sUN8CHnE... > Hi anyone, > > I'm trying to do a LU-decomposition with xilinx FPGA. It's inside matlab but it's not in the xilinx blockset which mean i cannot implement it using sysgen, any idea?Article: 49408
Any reason you claim matrix ops are "usually" done in floating point? And emulating floating point isn't particularly difficult, I designed a floating point processor entirely in hardware my first job out of school! -Stan "glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:As1z9.21176$og.39069@rwcrnsc52.ops.asp.att.net... > > "Muzaffer Kal" <kal@dspia.com> wrote in message > news:k1snsug5p01kul7bbcqfpn50l03p6g8dmo@4ax.com... > > On Fri, 08 Nov 2002 14:06:15 +0200, Utku Ozcan > > <utku.ozcan@netas.com.tr.SPAMELA> wrote: > > > > > > > >> Hi anyone, > > >> > > >> I'm trying to do a LU-decomposition with xilinx FPGA. > > >> It's inside matlab but it's not in the xilinx blockset > > >> which mean i cannot implement it using sysgen, any idea? > > > > > >Is the "decomposition" the one related to logic theory? > > >Is it an academic research? Would you please more specific? > > > > > >Utku > > > > LU-decomposition is a matrix manipulation technique where a matrix A > > is generated by multiplying two matrices L, U: > > Matrix operations are usually done in floating point, which is inefficient > on FPGA's. > > If you can do it in fixed point, then you might have better luck. > > I would look at systolic array algorithms, though I don't know if > it can be done that way. > > -- glen > >Article: 49409
The more appropriate question is, can YOU do floating point? No but seriously, it's not hard, do it the same way you do it on paper. -Stan "fireball" <sensen@swirvemail.com> wrote in message news:ee7a3b8.3@WebX.sUN8CHnE... > I'm trying to solve a 3 variable linear equation using matrix (LU-decomposition method). Anybody can shed light on how to do this in FPGA hardware? > > Can FPGA do floating point?Article: 49410
The numeric operations in LU decomp are (drum roll) addition, subtraction, multiplication and division. -Stan "Jan Gray" <jsgray@acm.org> wrote in message news:aqmd93$umf$1@slb5.atl.mindspring.net... > "fireball" <sensen@swirvemail.com> wrote in message > news:ee7a3b8.3@WebX.sUN8CHnE... > > I'm trying to solve a 3 variable linear equation using matrix > (LU-decomposition method). Anybody can shed light on how to do this in FPGA > hardware? > > Can FPGA do floating point? > > Is this course work? > > (Muzaffer Kal and Glen Herrmannsfeldt already gave good answers, as does > http://www.google.com/search?q=fpga+floating+point > http://groups.google.com/groups?q=fpga+floating+point) > > You will have to take the algorithm, carefully note what sequence of > operations it applies, and then figure out how to implement that sequence of > operations in hardware, as a datapath and/or as some kind of sequential > machine. > > It is also important to determine which elements of your specific problem > domain are *fixed* or *rarely changing* -- that can lead to massive savings > due to precomputation or strength reduction of operators. > > An FPGA can do floating point, but it is rarely done. In my opinion, > implementing floating point in an FPGA is considerably more work than > implementing an equation solver GIVEN an FPGA floating point implementation. > There are also some references to FPGA floating point papers at > fpgacpu.org/usenet/fp.html. > > There are other number systems that may apply, but even there, some of the > numeric operators in LU decomposition may be a bit of work to implement. > > I suspect it misses the point, but the simplest thing to do that addresses > the letter of your question, is get a Nios or Microblaze dev kit (first > checking they do indeed have floating point software or hardware libraries) > and compile the C code in section 2.3 of Numerical Recipes in C. For both > Xilinx and Altera's DSP design environments, it may make sense to be able to > drop in a lightweight soft CPU core to handle arbitrary code blocks. > > (As I understand it, Altera's Code:DSP > (http://www.altera.com/solutions/dsp/dsp-code_dsp.html) goes the other > way -- it allows you to design and implement Nios instruction set extensions > and/or peripherals via MATLAB/Simulink. But similarly and recursively, you > may wish to stick a small CPU core into your Simulink signal processing > pipeline to do more general purpose signal processing.) > > Jan Gray, Gray Research LLC > >Article: 49411
> Unfortunately, sometimes you DO need it. But I would place these things in > Quartus, since it is really dependent on the actual device, and it is only > relevant for place&route, so I would not include it in my VHDL- code > > Roman I can't understand the meanning of inserting LCELL buffer. Could someone tell me when we insert LCELL in design?Article: 49412
Ray Andraka wrote:
<Lots of good stuff snipped>
In levels of abstraction, think a range. Start with FPGAEditor. At
this end, every detail must be specified by the designer. A fair amount
of effort to do a simple design. But if the designer is careful, a very
good answer, in terms of minimum FPGA resources and highest clock rate
can be the reward for the effort. Personal opinions noted in {}; IMNHO
YMMV SRA SDD PDCC. I'm not sure how Jbits would play into this, so I'll
suggest that anyone interested can tell us if they want.
Every detail must be specified by the designer.
FPGAEditor, also XDL {XDL isn't very "novice friendly"}.
Move to schematic/netlist(draw program/VHDL) with full placement
information. (XDL?)
Next is schematic/netlist(draw program/VHDL/Verilog).
Next is RTL (VHDL/Verilog) {The place were Verilog is slightly
better.}
Next is behavioral (VHDL/Verilog/HandelC/SystemC) {Verilog is weak
here} {HandelC is slightly better as a language than the alternatives
here, however VHDL/Verilog tools are more mature.}
Next is algorithmic or HLL level (C or Java or ??).
At this end, almost every detail is generated by a program. If that
program isn't too dumb, then the results will also not be too dumb.
{I'm not convinced that any of these tools is worth using yet.}
At this end of the range, results will be not as good. That's a given.
However the design effort should be rather less, {key point} as long as
the required level of performance isn't pushing the technology. If it
is, the best way to proceed is often to move up the list, to lower
levels of abstraction. This is one of the strong points of VHDL, by the
way, one can rewrite the code into a different level of abstraction
(usually lower) and {key point} not need to change languages.
If you were to learn a single language, VHDL would be a good choice. If
I was teaching a class in FPGA design, and didn't have access to
something like FPGAEditor, I would start with netlist level VHDL, move
to RTL level and then to behavioral level.
(Almost a different subject)
--------------------------------
I went to Xilinx's web page to find more about Xilinx's "Forge" product,
when the C language support is added, and the web site doesn't give a
schedule, as this product might be interesting. However, the
information given to support performance claims is very lame:
http://www.xilinx.com/ise/advanced/forge_results.htm
The triple DES. This is perhaps a best case, and it shows up ok when
compared with a student project. {I don't think that's a very strong
case.}
Then there is a pointer to an academic paper that compares different
implementations of a 74181 ALU.
http://www.sussex.ac.uk/Users/tapu9/publications/uk_acm_sigda_02.pdf
Different implementations, very different implementations, for among
other differences the HandelC produces 7-segment outputs, and the other
implementations don't. {I wonder why HandelC "lost" the comparison? If
nothing else the review of examples was weak.} And this: "the logic
synthesis tools are not able to detect the purely combinational
implementation of the ALU 74181," maybe that's true for Forge Java, but
is not true for HandelC or for VHDL{!!!} And HandelC isn't a pure
software HLL, as it has an implied clock, and in HandelC all operations
will be scheduled to occur in specific clock cycles, unless you
specifically code them so as to be purely combinational. But enough of
that.
The conclusion of the paper is that VHDL is best, which might be true,
and that Forge Java might be useful, which again might be true. But the
real point of the paper is:
{READ THIS}
"An interesting conclusion of this study on description languages is
that even when using a high-level language, the developer needs to have
a good background in hardware design, in order to help the compiler to
infer proper and efficient hardware constructors. Using general-purpose
programming techniques in a hardware-based application will certainly
result in too many gates and a highly inefficient circuit."
This is a good statement to explain why the "dusty deck" dream is and
will stay a dream for quite a while at least. But that doesn't mean
that HLLs are not potentially very useful.
--
Phil Hays
Article: 49413On Mon, 11 Nov 2002 08:19:28 -0000, hmurray@suespammers.org (Hal Murray) wrote: >>Speaking generally, for a combinational output, there is no guarantee >>of constant output before the circuit has settled after each clock >>edge. Most likely your glitch is being generated by the different >>propagation delays thtough your combinational logic. If you want to >>guarantee a non-glitching output, you need to register it. > >I think Xilinx used to guarantee no glitches on their LUTs if you >only changed one input at a time. That is if you change one input, >the output will either stay the same or make a clean transition. > >[Makes sense if they use a tree of 2 input MUXes and take some care >with the basic MUX.] http://www.xilinx.com/xapp/xapp024.pdf on page 13-20 says "...there can never be a decoding glitch when only one select input changes." I have been assured by Peter A. that this still applies to modern Xilinx FPGA families. Regards, Allan.Article: 49414
polly@rz.fh-augsburg.de (Thomas Pollischansky) wrote in message news:<6b0e63fc.0211060947.186ef2b0@posting.google.com>... > Has anyone got experiance in using Nios 1.1 together with Quartus II > 2.11. > My Nios processor designs are not completely compiled. Half of the > NIOS processor is missing on the FPGA (no internal memory..). > Has anyone had problems like that or know what might be the reason > (forgotten Options in Quartus...)? Thanks for any answers! Two things to try 1. in Project->General Setting->Library, make sure you have an entry pointing to the directory where your nios stuff was built, ie. directory where nios.ptf, nios.v, cpu.v, etc reside. There are a bunch of black boxes in the nios design that Quartus will need to find, like boot_rom_lane0.v, ram lanes, etc and mifs that go inside those internal rams. 2. Make sure you dont have any synthesis directives inside any of the files Quartus reads. Quartus 2.1 has started respecting synthesis directives like "synthesis syn_black_box=1", "synthesis translate off", etc. If you have any of these in any of the files Quartus reads in, then Quartus will leave the blackbox as is and will not insert the contents of the black box. Let me know (thru this newsgroup) if any of these help. PS: The Project->General Setting->... part might be slightly off. I dont have Quartus here to check the correct menu options to get to there.Article: 49415
One can code at the primitive level using an HDL, in which case it is
generally not regarded as RTL. The reasons for doing so include
instantiating features that do not get correctly inferred, and instantiating
a particular structure for performance or placement reasons or to avoid a the
'pushing on a rope' that can often accompany an RTL design when there is a
particular structure desired.
Stan wrote:
> "RTL" stands for Register Transfer Level. As opposed to gate level or
> transistor level.
>
> I think a lot of people might make a statement like "I used a Hardware
> Description Language to code my design at the Register Transfer Level."
>
> Of course that statement is a bit redundant, because the idea of coding at
> the gate level or transistor level using an HDL doesn't make much sense.
>
> -Stan
>
> "Anonymous4" <nicemanYep@yahoo.co.uk> wrote in message
> news:f9028e31.0211111347.2bc4c99c@posting.google.com...
> > Hello,
> > Basic Question i know but confused on:
> > what is the difference between Hardware Description Language (HDL) and
> Register
> > Transfer Logic(RTL)
> > Thanks
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49416On Tue, 12 Nov 2002 02:35:27 GMT, "Stan" <vze3qgji@verizon.net> wrote: >The more appropriate question is, can YOU do floating point? No but >seriously, it's not hard, do it the same way you do it on paper. -Stan Depends on how you define floating point. A full & correct implementation of IEEE 754 standard is notoriously complicated. Even Intel messed up one implementation at some point. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 49417
"Stan" <vze3qgji@verizon.net> wrote in message news:LMZz9.5630$6Z.3255@nwrddc01.gnilink.net... > Any reason you claim matrix ops are "usually" done in floating point? > Because they are usually done for scientific applications that have a wide range of magnitudes. For these kinds of problems, it probably doesn't matter much. If there isn't enough precision, too much will be lost in intermediate results. Look at IMSL, or Numerical Recipes. All matrix algorithms are in floating point, usually double precision. > And emulating floating point isn't particularly difficult, I designed a > floating point processor entirely in hardware my first job out of school! It isn't hard to do in hardware, it is the hardware that the FPGA gives you that makes it hard, and the fact that you usually want a pipelined design. Prenormalization and postnormalization require a barrel shifter which takes a lot of CLB. Now, I have suggested before that hex based floating point would be much easier to do, and is probably fine for most problems. That is, the exponent is powers of 16 instead of 2. The barrel shifter is much smaller, and the precision and range are about the same. A byte or bit serial floating point unit should be easy, but it won't be much better than implementing the algorithm on a commonly available processor, probably a DSP. You use FPGA's when you need it to be a really fast, highly parallel implementation. -- glenArticle: 49418
"Muzaffer Kal" <kal@dspia.com> wrote in message news:dq41tusn3ejiqmeph9if7h86liag1v8uh2@4ax.com... > On Tue, 12 Nov 2002 02:35:27 GMT, "Stan" <vze3qgji@verizon.net> wrote: > > >The more appropriate question is, can YOU do floating point? No but > >seriously, it's not hard, do it the same way you do it on paper. -Stan > > Depends on how you define floating point. A full & correct > implementation of IEEE 754 standard is notoriously complicated. Even > Intel messed up one implementation at some point. Yes, I would agree. My choice would be IBM's hex based floating point. Much simpler, and the barrel shifters are much smaller. -- glenArticle: 49419
>I'm a complete newbie to FPGA design. I've got a Matlab routine that I'd >like to port to an FPGA. It does some array operations and makes use of an >FFT. How do I ballpark the size of FPGA I'll need to do this? You basically have to do a rough design in order to make an estimate. Do you have time to do your array processing one element at a time (loop) or do you have to do things in parallel? Do you need floating point? That makes things much bigger, and much more complicated. How big are your numbers? How many bits? Each bit takes a filp-flop (or a slot in a RAM) so your design will get bigger if you need more bits per word (more accuracy) in each number/register. What are you doing with the array? How big is it? Some FPGAs have blocks of RAM. Will it fit? How is the data getting into the array? Vendors usually have FFT cores that you can purchase. The documentation probably gives you some sample space/speed numbers. Might be worth hiring a consultant for an afternoon or taking a class. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 49420
"Stan" wrote > The numeric operations in LU decomp are (drum roll) addition, subtraction, > multiplication and division. -Stan Sarcasm? I know LU decomposition, it says so right here in the fine print on my math degree. In case it wasn't obvious, I went to some pains to be vague in certain points, so as to avoid spelling out every detail of how to do what appeared to be school work. Jan Gray, Gray Research LLCArticle: 49421
In comp.lang.vhdl Justin A. Kolodziej <jkolodzi@students.uiuc.edu> wrote: Only synchronous, only std_logic types, only RTL... That should get you pretty far. regards, juza : Does anyone have a pointer to a canonical list of things to do and avoid : doing when you want to write VHDL that has a good chance of actually : synthesizing correctly in Leonardo? : I only know that what I do tends to work better than what my students do : (I have the unfortunate task of TAing a class in embedded systems and : reprogrammable logic), but I admit that I don't have such a list of rules : that will guarantee that VHDL works when it is synthesized, even if it : works in simulation. : Certainly someone out there must have a list... and I don't mean the : "Synthesizable VHDL" subset, because even if the synthesis tools gives no : warnings or anything, things can break horribly when additional processes : are added, it seems. -- JuzaArticle: 49422
Thanks for your help! Comment of Altera'a Support: Nios 1.1.1 and Nios 1.1 were designed to work with Quartus II 1.1. Designs generated in Nios 1.1 and 1.1.1 contain syntheis translate on and off directives which were not recognized by Quartus II 1.1. Therefore Quartus II 1.1 would correctly synthesize the cores. However, in Quartus II 2.1 we have a new synthesis engine which recognized syntheis directives. The best solution to your problem would be to upgrade to Nios 2.11 as this version of Nios was intended to work with Quartus II 2.1. Alternatively you could use Quartus II 1.1 with your current version of Nios. I'll look for the correct versions and hope that's the solution to the problem! ThomasArticle: 49423
I am very new at this, but I'll take a stab at it ( and quite possibley be wrong in the process) Assuming you have the bit vector clockable a bit at a time. 8 bits will require a 5 bit counter. A quick look at the xilinx documentation reveals that 5 bit resetable counter will require about 5 slices. So if you can clock the counter and the bitstream from the same clock and use the bitstream as the enable on the counter the I would estimate 3 CLB's Ralph <devnull@mighty.morphism.org> wrote in message news:aqm6ni$2ngc$1@news2.engin.umich.edu... > I'm starting to do some research into reconfigurable computing for my > MSc directed study. One of my applications involves string processing. > > Given a bitvector of length 28 and the CLB from a Spartan-IIE family > FPGA, can anybody estimate (off the top of their head) roughly how many > CLB's it would take to implement an operation to count the number of 1's > as well as an operation to produce a 5-bit number indexing the first bit > that is set to a 1? These operations are essential for traversing trie > data structures quickly in hardware. > > Latency isn't an issue, so we can assume the design constraint is minimal > area. > > Thanks, > BrianArticle: 49424
Thank you for your reply, Austin. What I'm trying to find out is if it is possible to ignore CS and WE by connecting them to ground, and to configure the device using a "controlled" CCLK (i.e., not free-running). Does the power-up/clear-config-mem/... work with CS,WE tied to ground? Thank you, Andy Austin Lesea <austin.lesea@xilinx.com> wrote: > Andreas, > INIT going high tells you that the device is ready to be configured. If > you attempt to configure before it is ready, you will not succeed. > Austin > Andreas Schweizer wrote: >> Hi all, >> >> I'm new to this list and have a question about >> configuring a Virtex-II FPGA. >> >> In the design I'm working on, we use a second FPGA to >> configure a larger Virtex-II FPGA using the SelectMAP mode. >> The second, smaller FPGA loads the data from a connected >> memory chip. >> >> Now, I'm not sure when to pull down #CS and #WRITE. Can I do >> this right from the beginning (together with #PROGRAM), or do >> I have to wait until #INIT='1' (or are these signals ignored >> until #INIT='1'?) >> >> Thank you for your help, >> Andy
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