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"Klemen" <nec4b@email.si> wrote in message news:aq6mj6$nda$1@planja.arnes.si... > Hi! > > I'm new to FPGAs and i don't know in which language should i begin to > design( vhdl, verilog, c). I currently have Webpack 4.1. My understanding is that if you like C you should use Verilog, if you like Pascal or Ada you should use VHDL. -- glenArticle: 49326
"Muzaffer Kal" <kal@dspia.com> wrote in message news:k1snsug5p01kul7bbcqfpn50l03p6g8dmo@4ax.com... > On Fri, 08 Nov 2002 14:06:15 +0200, Utku Ozcan > <utku.ozcan@netas.com.tr.SPAMELA> wrote: > > > > >> Hi anyone, > >> > >> I'm trying to do a LU-decomposition with xilinx FPGA. > >> It's inside matlab but it's not in the xilinx blockset > >> which mean i cannot implement it using sysgen, any idea? > > > >Is the "decomposition" the one related to logic theory? > >Is it an academic research? Would you please more specific? > > > >Utku > > LU-decomposition is a matrix manipulation technique where a matrix A > is generated by multiplying two matrices L, U: Matrix operations are usually done in floating point, which is inefficient on FPGA's. If you can do it in fixed point, then you might have better luck. I would look at systolic array algorithms, though I don't know if it can be done that way. -- glenArticle: 49327
Hi, Just wondering if anyone can direct me to some information on the LUTs inside the Xilinx CLBs. I know they are SRAM based, but what is the circuitry involved ? Does anyone know ? Are there any circuit diagrams available anywhere ? Thanks, FiArticle: 49328
>Just wondering if anyone can direct me to some information on the LUTs >inside the Xilinx CLBs. I know they are SRAM based, but what is the >circuitry involved ? Does anyone know ? Are there any circuit diagrams >available anywhere ? What level of detail are you looking for? Roughly, it's a "ROM", that is a bank of FFs followed by a tree of two input muxes. The FFs in the ROM are the SRAM part. They get loaded during configuration. You can think of the input bits to the LUT as the address of a ROM. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 49329
"Saffary" <a.saffary@wanadoo.fr> writes:
> If somebody know, if i can use spartan(1) chips with ISE WebPack?.
No. But Xilinx recently made something called "ISE Classic" available
for download. It supports the Spartan, Spartan XL, and XC4000 families,
and is based on ISE 4.2i. However, it doesn't include design entry,
so you'll need a third party compiler like Synopsys, Synplify, or
Leonardo. It can be found at:
http://www.xilinx.com/webpack/classics/spartan_4k/index.htm
If you don't have money to spend on software, you're much better
off using the Spartan II or Spartan IIE chips instead.
Article: 49330"Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> schrieb im Newsbeitrag news:Gn0z9.5944$8o1.968125@news.xtra.co.nz... > "emanuel stiebler" <emu@ecubics.com> wrote in message > news:3DCAB8BC.4030909@ecubics.com... > > Peter Alfke wrote: > > > > It's called BIT-SLICE Microprocessor Design by Mick and Brick > > > published by McGraw Hill , ISBN 0-07-041781-4 in 1980 > > > > > > also you might want to look at Bit Slice Design:Controllers and ALU's > > > by Donnamaie E. White ISBN 0-8240-7103-4 ( known as the white book ! ) > > > > And if you really don't have it in your bookshelf, at least the second > > one is online. Just google around for Donnamaies webpage. > > Thanks for the pointer, lead me to this > > http://www10.dacafe.com/book/parse_book.php?article=BITSLICE/index.html > > This is exactly the kind of stuff I was looking for. Very useful in a fgpa > with lots of block ram. > > Is this the way most CISC is implemented? > > Now off to hook up a array of 40 PROM ;-) > Hello Ralph, old memories waked up. I was involved in a bit slice technology microprocessor system in 1979 during my last year at university. We used the MC10800 ECL bit slices from Motorola. At the same time, AMD had its Am2900 TTl chips on the market. We build a 16bit processor using a 128bit wide micro program and depth was 1k?. I don't remember exactly. These days, people can do that all in one FPGA. I tried Google with bit slice computer and got many hits. A few aexamples are: http://www.cs.clemson.edu/~mark/uprog.html http://www.dacafe.com/DACafe/EDATools/EDAbooks/BitSlice/bitslcId.html http://www-inst.eecs.berkeley.edu/~cs150/fa00/CS150.F00/Lectures/08-CompOrg. ppt Best Regards HelmutArticle: 49331
I have a 60 day evaluation of ISE 4.2 which includes the Core gen interface. How do I stand (legally) if I use some of the free included modules in my design? It is not for commercial use - just an assignment for college. Cheers, BobArticle: 49332
Hello Ladies & Gentlemen, i have the following problem: I wish to program my spartan IIe via JTAG commands by the TAP controller. The JTAG fsm is well known, but the device does not accept any bitstream i send. The first steps are entering the TEST-RUN/IDLE and the reset state, then writing the CFG_IN command to the SHIFT-IR. After that the configuration data is load by an Mitsubishi M16C microcontroller (TMS, TCK and TDI are generated by driven port pins). So the data is written to the corresponding DR. At last the JSTART command is written. But the device does not react. For test purpose i have also written a test pattern (from xilinx xapp139.pdf) and tried to read it back by CFG_OUT. But this procedure has also been failed. Can anybody help me, please? T. Bartzick.Article: 49333
The LUTs are the least interesting part of FPGAs. The most common circuit I have seen is 16 SRAM cells feeding a 16-1 mux (a 4 deep tree of 2-1 pass transistor muxes). On the 4 inputs signals there will be inverters (for the complementary pass transistors) and possibly drivers (amplifiers). Of course, something more is going on in modern LUTs with shift register and distributed RAM functionality. But the genius is in the programmable interconnect -- how do signals from all over the device wend their way to the four inputs of this particular LUT? > Are there any circuit diagrams > available anywhere ? Two books that have such circuit diagrams, and that might be in your local university library (or perhaps on the bookshelf of your coolest CS/EE professor acquaintance). 1. Steve Trimberger, Field Programmable Gate Array Technology, Kluwer, 1994. ISBN 0-7923-9419-4. (Mine is lent out -- I think it had circuit diagrams.) 2. Vaughn Betz et al, Architecture and CAD for Deep-Submicron FPGAs, Kluwer, 1999. ISBN 0-7923-8460-1. In particular, in (2), p. 215, Figure B.9, is a schematic of a 4-LUT. "The area of this 4-LUT is 96 (SRAM cells) + 30 (multiplexer tree) + 41 (input buffers and complementers) = 167 minimum-width transistor areas." There are also the proceedings of the ACM FPGA conferences (see http://fpga2003.ece.ubc.ca/). There you can read more about actual and proposed FPGA architecture than you'll ever care to know. Ah, you say, I neglected to attend the last 10 years of the FPGA Conference, so I don't have any of those proceedings on my bookshelves. And neither does my poor excuse for a library! Fear not. Here's a plug for the ACM (Association for Computing Machinery). If you join ACM and subscribe to the appropriate SIGs (here, SIGDA), and take the digital library option, (all totaled, several hundred dollars per year), you can pull up any of the papers in the proceedings of FPGA'95 through FPGA'02 as PDF files. I have also seen good detailed FPGA circuit implementation papers in IEEE Trans VLSI and other such places. This kind of detail is also probably present in various patent descriptions. Jan Gray, Gray Research LLCArticle: 49334
On Mon, 4 Nov 2002 21:51:07 +0100, "Klemen" <nec4b@email.si> wrote: >Hi! > >I'm new to FPGAs and i don't know in which language should i begin to >design( vhdl, verilog, c). I currently have Webpack 4.1. > >regards > To quote RK, schematics. JohnArticle: 49335
John Larkin wrote: > On Mon, 4 Nov 2002 21:51:07 +0100, "Klemen" <nec4b@email.si> wrote: > >I'm new to FPGAs and i don't know in which language should i begin to > >design( vhdl, verilog, c). I currently have Webpack 4.1. > To quote RK, > > schematics. I'd suggest: FPGAEditor. To be fairly good designing FPGAs requires understanding them at several different levels of abstraction. The minimum lowest level is the LUT/FF/PIP/IOB/clocktree/Carrychain/etc level. The correct tool in the Xilinx world is FPGAEditor, and it's not in Webpack, but if I was teaching a class in design using FPGAs the first lab assignment would be to design and verify some simple logic using FPGAEditor or similar. Without using autoroute. The reason is you need to learn what's in the FPGA first. I don't think you can get good with FPGA design without a good understanding of the internals of the parts. Understanding a bit about transisitor design, device physics, layout, IC fab, semiconductor test, etc would be useful, but I don't think it is required. Schematic level, done with pictures or text, would be next. -- Phil HaysArticle: 49336
You can use less LUTs if you do a serial implimentation of your long adders, of course you'd need to consume the result serially other wise you're going to use 16 flops to hold the result anyway. Regards "Sanjay Patil" <sanjay@cg-coreel.com> wrote in message news:<aqcmjd$8onjd$1@ID-164436.news.dfncis.de>... > Hi, > We are using Virtex-2 device for one of the applications and We have > observed that the LUT utilization for a 16 + 16 bit adder is 16LUTs and also > 16 + 1bit adder is also 16LUTs. The above is because the Carry chains are > routed through LUTs. Is there any possibility of reducing the LUTs in case > where unequal number of bits are added to less than the Max number of input > vector. i.e. if say 24bits are added with 1bit, then can the logic can be > such that it utilizes less than 24 LUTs > > Can anyne help me. > Regards, > SanjayArticle: 49337
> Thanks for the answer - I'm using the apex20ke200 on the nios > evaluation board - but the problem is in the compiling stage. When I'm > compiling a NIOS design (with nothing but a processor) the compiler > reports, that it has used about 1800 LEs but 0 RAM bits. Never have such errors. IMHO you should upgrade to Nios 2.0 (this one with SOPC Builder) and correct Leonardo version (don't know why but not all versions of Quartus/SOPC Builder/ /Leonardo work together correctly). When I was making upgrade, all these programs were changed. jerryArticle: 49338
FPGA on-chip memory is great, but probably not voluminous enough for storing bitmapped images. -Kevin "lpm" <lmicken@eng.morgan.edu> wrote in message news:fd38b8a3.0211081421.670cdaa9@posting.google.com... > Hello all, > > I'm graduate student (and a FPGA newbie) designing a image processing > system using a Spartan-II FPGA and have a question regarding where I > should store the images that I'll be processing. Should I use an off > board memory chip, and if so what's the best way to interface to it? > Or, should I just store the image on the FPGA? Thanks for any > assistance. > > -LisaArticle: 49339
> John Larkin wrote: > >>On Mon, 4 Nov 2002 21:51:07 +0100, "Klemen" <nec4b@email.si> wrote: > > >>>I'm new to FPGAs and i don't know in which language should i begin to >>>design( vhdl, verilog, c). I currently have Webpack 4.1. >> > >>To quote RK, >> >>schematics. > Phil Hays wrote: > > I'd suggest: > > FPGAEditor. > Not in the WebPACK. FPGAEdit only exists in the for-money releases of the software. When I asked about this, the impression I got was that they (Xilinx) thought that WebPACK is already plenty big to download. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." abuse@xo.com uce@ftc.govArticle: 49340
All, does anyone know of a free pci core written in either verilog or vhdl? I am looking for more then just a 30 day evaluation but rather the complete rtl to incorporate into a hobby project using a Xilinx FPGA. Thanks JArticle: 49341
I instanciate some components, such as OPNDRN, TRI, LCELL ...etc (defined in MAXPLUS II) in my vhdl code. The VHDL declaration of these component is build in Altera library and package. When I use these component in VHDL, it need the follow two lines in code --- LIBRARY ALTERA; USE ALTERA.MAXPLUS2.ALL --- The code will pass compilation on MAXPLUS II. But when I need to synthesize my design using synopsys FPGA compiler II. The synthesis tool will not identify these components, so program report error. How do I modify my code so that FC II can synthesize it?Article: 49342
Hello every body I'm in an odd problem.I've a design that contains a timer that is initialized at the reset time. I simulate in with Modelsim5.6a and there is no problem. But after I synthesize it and Implememnt with ISE4.2i and then I simulate its SDF file with modelsim I receive awfull results. The oddest point is that my timers are not initialized!I've checked it with the FPGA and in the FPGA they are initailized! I don't know if it's the problem with my softwares or not and if there is any solutions for it. Thanks for any help G.SohrabArticle: 49343
Dear all, some week ago I built a prototype board for an experimental setup using an FPGA Xilinx XC4003E (yes, I know, it's a quite old part! But it was sufficient for our sake...). I noticed that certain configuration I used presented a strange behaviour related to some I/O pin. In particular I used pin 51 (that is an I/O, SGCK3, GCK5) as input for a clock signal (with a BUFGS) and pin 72 (that is an I/O, SGCK4, GCK6 and DOUT) as an output for serial data. The unexpected fact was that every time on pin 72 there was a transition in the data stream from 0 to 1 the circuit implemented seemed to respond as a clock pulse was received. I tried many different configurations, but all presented this behaviour (if pin 51 and 72 was used). It exists some kind of link between these pins? It is possible to avoid this effect? Thanks to all. StevensonArticle: 49344
Any one has multi-stage digital decimation filter's vhdl code to share? I hardly get it anywhere from net.Article: 49345
golchehreh sohrab wrote: > Hello every body > I'm in an odd problem.I've a design that contains a timer that is > initialized at the reset time. I simulate in with Modelsim5.6a and > there is no problem. But after I synthesize it and Implememnt with > ISE4.2i and then I simulate its SDF file with modelsim I receive > awfull results. The oddest point is that my timers are not > initialized!I've checked it with the FPGA and in the FPGA they are > initailized! I don't know if it's the problem with my softwares or not > and if there is any solutions for it. > Thanks for any help > G.Sohrab Are you sure your reset is getting through to your logic? Did you forget to drive the GSR and GTS signals defined in the Gate level netlist top-level? DaliArticle: 49346
"Jim Antone" <jantone@austin.rr.com> wrote in message news:<uDjz9.299642$8o3.8792912@twister.austin.rr.com>... > All, > > does anyone know of a free pci core written in either verilog or vhdl? I am > looking for more then just a 30 day evaluation but rather the complete rtl > to incorporate into a hobby project using a Xilinx FPGA. > > Thanks > > J Check out OpenCores (www.opencores.org) they have a complete FREE PCI Bus IP core. Cheers, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - NEW ! 5 New Free IP Cores this months (so far :*) FREE IP Cores --> http://www.asics.ws/ <--- ----- ALL SPAM forwarded to: UCE@FTC.GOV -----Article: 49347
Altogether_Andrews <juglugs@hotmail.com> wrote in message news:<2D_y9.1660$R5.1398953@nnrp1.ptd.net>... > Lattice seem to have the best SERDES, and don't try to hide behind the > Marketroid BS like others do. > > Altera's GX seems close, but no cigar... Hmm, interesting. So do you have real live comparison numbers for the equivalent from Xilinx and Altera ? I would really like to see those ! And please tell us that you are not working for Lattice ! So far your statement looks like one of the many marketing blurps ! rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - NEW ! 5 New Free IP Cores this months (so far :*) FREE IP Cores --> http://www.asics.ws/ <--- ----- ALL SPAM forwarded to: UCE@FTC.GOV -----Article: 49348
amyks@sgi.com (Amy Mitby) wrote in message news:<2d2a8f5d.0211081403.a6db63c@posting.google.com>... > I'd like answers to the following questions: > > 1) Are there significant benefits (in terms of resource > use and performance, not just saving time) to using some > of Xilinx's Core Gen components, or are they not much > better than a hand-design? > > 2) Have there been a lot of problems with buggy cores, or > cores that cause resource issues (timing / area conflicts), > etc? > > 3) Are there certain cores that you would recommend absolutely > not using (bad experiences), or some that are particularly good? > > 4) Have there been any problems in using cores when migrating to > different Xilinx tool versions? Inferring low level cores, prevents synthesis tools from optimizing your code. I personally don't like "black box" netlists. I like to have the source code as well. Portability to other vendors and/or asics is a big problem (for me at least). Mega-functions, e.g. large blocks are obviously better optimized that your push-buttong synthesis and P&R will be. However, if you sit down and spend some time with the floorplanner you can get the same or even better results. Just my personal feelings ! Cheers, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - NEW ! 5 New Free IP Cores this months (so far :*) FREE IP Cores --> http://www.asics.ws/ <--- ----- ALL SPAM forwarded to: UCE@FTC.GOV -----Article: 49349
any input here Please --Hristo hristostev@yahoo.com (hristo) wrote in message news:<b0ab35d4.0211051151.417f419b@posting.google.com>... > Hello, > Could someone please explain more the VersaRing utility? > i know it is the routing ressources which allow connecting the IOBs to > CLBs > is it so performant and quick such that i don't have to bother myself > too much about the design padding > > thanks
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