Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
While an FPGA on wirewrap can be done if extreme attention is paid to
both the wirewrap and the design of the timing of the I/O, I hardly
recommend it, especially to the beginner. Edge speeds on modern
devices make it very difficult to avoid signaling problems. Do
yourself a big favor and either use one of the many pre-fabricated
boards, or make a proper PWB (at least 4 layers, please!) and save
yourself many hours of grief.
Markus Wolfgart wrote:
> Hi Jay,
>
> sorry to hear, that the old Spartan family are not supported by
> the free web-pack, as I had already ordered two pieces of it :-(
> My consideration was to play around first with a part in a plcc84
> case in order to use a plcc84 socket to move my fpga to different
> test boards with hardware wired together by simple thin wire ;-)
>
> Thanks for your reply and I would take in account all hints for
> my next steps in fpga programming.
>
> Bye
>
> Markus
>
> ============================================
>
> Markus Wolfgart
>
> DLR
>
> ============================================
> PS.: remove the xx_ from email adr. to reply
> ============================================
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49851
That, and bipolar saturation to an arbitary (odd) limit could be done in one
column of luts in 4K. You need 2 slices in virtex because you need to use the
LUTs in front of the carry chain in order to use the carry chain. Yes, I miss
the carry structure of the 4K architecture, but I would't trade away the BRAM or
SRL16's to get it back.
glen herrmannsfeldt wrote:
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3DD2FBB9.76B321B@andraka.com...
> (snip)
> >
> > In the 4000/spartan series parts you basically needed the LUT to get at
> the bit
> > outputs from the carry chain, so unless you weren't using particular bits,
> you
> > still had to use the LUTs there. The advantage the 4K carry chain had was
> that if
> > you were only using the output at the end of the carry chain, perhaps as a
> > subtractive comparator, then the LUTs were available for other things with
> the
> > restriction that a few of the inputs were shared with the carry chain.
> That made
> > certain functions more compact than can be done in Virtex, but not your
> case.
>
> One that I used to like was a MAX(x,y) function, to select the maximum of
> two numbers.
> The carry chain does the compare, and the LUTs do the mux to select the
> maximum
> (or minimum) value. Someday I will have to see how to do this in Virtex.
>
> -- glen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49852
You know the saying: there's an exception to every rule. Even here, a composite
structure using carry chains in the latter levels gets a more compact and faster
design.
glen herrmannsfeldt wrote:
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3DDB109D.D0CD8056@andraka.com...
>
> (big snip)
>
> >
> > The bottom line is that carry save adder trees DO NOT MAKE SENSE for FPGAs
> > that have dedicated adder resources.
>
> How about for adding a large number of very small numbers.
>
> Say for adding 32 one bit numbers, for example?
>
> -- glen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49853"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:arjelo$itkou$1@ID-84877.news.dfncis.de... > "Leon Heller" <leon@heller123.freeserve.co.uk> schrieb im Newsbeitrag > news:aripp2$ifk$1@newsg2.svr.pol.co.uk... > > > One big advantage with the old devices is that they come in PLCC, making > > prototyping very easy. > > You sissy!! ;-)) > > Serious, one can also hand solder a 0.5mm pin pitch QFP, its easier than it > sounds. Also, the old part is worthless when the free tools dont support it > (any more) as it is the case with Spartan. Also, the old parts are quite > expensive. You can't use wire-wrap or point-to-point wiring, though. That was the point I was making, although I have heard of one or two people attaching wires to small devices with 0.5 mm pitch leads, like the AD9850 DDS. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 49854
This is a multi-part message in MIME format.
------=_NextPart_000_000B_01C29225.DA6591D0
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
hi all.
I'm currently implementing an image processing algorithm in hardware.
The ip algorithm requires that I compute logarithms. This can prove =
quite a computationally expensive operation, but I only need accuracy =
down to around 4/5 significant figures.
Currently, as binary floats are represented as m*2^e, where m is a =
number between 1-2, I have approximated the log function between 1-2 =
with a cubic polynomial. I then just scale the base2 exponent and add =
it to the result of the poly.
This method is inexpensive but gives limited accuracy. Operations shown =
below
z =3D a + b*mant + c*mant^2 + d*mant^3;
if (e ~=3D 0)
z =3D z + exp * C1;
end;
This requires 6* and 4+.
Unfortuately, adding extra terms to the poly increases the accuracy =
slowly.
So.... Does anyone know of a better way of computing the logarithm of a =
base2 fp number?
I have examined the c library log function (given below), though i don't =
see quite how it works.
It says it's using Newtons method but it isn't iterative. Could it have =
been used to generate the polynomial prior to use in this algorithm. In =
which case, how, ... so I can develope a less costly algorithm.
Thanks very much for your time.
Tim
Tim Nicolson
Reseach Engineer
QinetiQ
Malvern
UK
t.nicolson@signal.qinetiq.com
here's the c code!
/* Get the exponent and mantissa where x =3D f * 2^N. */
f =3D frexpf (x, &N);
z =3D f - 0.5;
if (f > __SQRT_HALF)
z =3D (z - 0.5) / (f * 0.5 + 0.5);
else
{
N--;
z /=3D (z * 0.5 + 0.5);
}
w =3D z * z;
/* Use Newton's method with 4 terms. */
z +=3D z * w * (a[0]) / ((w + 1.0) * w + b[0]);
if (N !=3D 0)
z =3D (N * C2 + z) + N * C1;
if (ten)
z *=3D C3;
return (z);
}
Article: 49855
Hi,
this means that the library element you're referencing (ofdx from the unisim
library) doesn't have the gsr and gts ports
hence the simulator can't find the correct representation.
You can easily verify that by having a look at the unisim source code.
----- CELL OFDX -----
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library IEEE;
use IEEE.VITAL_Timing.all;
-- entity declaration --
entity OFDX is
generic(
-- some generics are normally placed her
);
port(
Q : out STD_ULOGIC;
D : in STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC);
attribute VITAL_LEVEL0 of OFDX : entity is TRUE;
end OFDX;
By the way you should recode your ff
mux : process(clk, reset_i)
begin
if (reset_i = '0') then
q <= '0';
elsif clk'event and clk = '1' then
if sel = '1' then
q <= b;
else
q <= a;
end if;
end if;
end process mux;
I'm not sure if it's save to remove the ports from your synthesized netlist.
You should also check the xc homepage they do have a design guide which
might further help you.
HTH
Ansgar
--
Attention please, reply address is invalid, please remove "_xxx_" ro reply
"Michael Winter" <Michael.Winter@gmx.net> schrieb im Newsbeitrag
news:arimn7$i1u@netnews.proxy.lucent.com...
> Hello,
> I have a problem when I want to simulate my synthesized project with
> Modelsim 5.6a. First I wrote a little VHDL programm with FPGA-Advantage
5.3:
>
> -- This is only a test-programm and didn't make any sense.
> LIBRARY ieee;
> USE ieee.std_logic_1164.all;
> USE ieee.std_logic_arith.all;
>
> ENTITY uut IS
> port(
> clk : in std_logic;
> a : in std_logic;
> b : in std_logic;
> sel : in std_logic;
> q : out std_logic
> );
> END uut ;
>
> ARCHITECTURE design_rtl OF uut IS
> BEGIN
> mux : process(clk)
> begin
> if clk'event and clk = '1' then
> q <= a;
> if sel = '1' then
> q <= b;
> end if;
> end if;
> end process mux;
> END design_rtl;´
>
> Then I synthesized the code with Leonardo Spectrum and got a *.vhd file
> containing the following code:
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.all;
> library unisim ;
> use unisim.all ;
>
> package vcomponents is
> component IBUF
> port (
> O : OUT std_logic ;
> I : IN std_logic) ;
> end component ;
> component OFDX
> port (
> Q : OUT std_logic ;
> C : IN std_logic ;
> D : IN std_logic ;
> CE : IN std_logic := '1' ;
> GSR : IN std_logic := 'Z' ;
> GTS : IN std_logic := '0') ;
> end component ;
> component BUFG
> port (
> O : OUT std_logic ;
> I : IN std_logic) ;
> end component ;
> end vcomponents ;
>
> package body vcomponents is
> end vcomponents ;
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.all;
> library unisim ;
> use unisim.all ;
>
> entity uut is
> port (
> clk : IN std_logic ;
> a : IN std_logic ;
> b : IN std_logic ;
> sel : IN std_logic ;
> q : OUT std_logic) ;
> end uut ;
>
> architecture design_rtl of uut is
> signal clk_int, a_int, b_int, sel_int, nx6: std_logic ;
> begin
> sel_ibuf : unisim.vcomponents.IBUF port map ( O=>sel_int, I=>sel);
> b_ibuf : unisim.vcomponents.IBUF port map ( O=>b_int, I=>b);
> a_ibuf : unisim.vcomponents.IBUF port map ( O=>a_int, I=>a);
> reg_q : unisim.vcomponents.OFDX port map ( Q=>q, C=>clk_int, D=>nx6,
> CE=>
> OPEN, GSR=>OPEN, GTS=>OPEN);
> clk_ibuf : unisim.vcomponents.BUFG port map ( O=>clk_int, I=>clk);
> nx6 <= (a_int and not sel_int) or (b_int and sel_int) ;
> end design_rtl ;
>
> Now I want to simulate this code. But when I try to compile it I receive
the
> following error message:
> ERROR:
>
D:/projekte/FPGA-Advantage/simu/ls/uut_design_rtl/netlists/uut_design_rtl.vh
> d(64): Unknown identifier: gsr.
> ERROR:
>
D:/projekte/FPGA-Advantage/simu/ls/uut_design_rtl/netlists/uut_design_rtl.vh
> d(64): Unknown identifier: gts.
>
> What did I wrong? The librarys unisim and simprim I compiled with a *.tcl
> script from Xilinx to use them with Modelsim and I defined these libraries
> as Standard Libraries in FPGA-Advantage.
> Note: Simulation after Place&Route works perfectly.
>
> Thanks for any help
> Michael
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
Article: 49856
See my quick and dirty log published on dsp-guru.com at
http://www.dspguru.com/comp.dsp/tricks/alg/quicklog.htm
Start with a normalized binary floating point. The exponent
scaled gets you within 6db. Then use the top few bits
(dropthe leading '1' bit, it is a constant) to address a
small look-up table containing logs of the mantissa. Using
4 bits of the mantissa will get you to about a 1/2dB, 5 bits
to 1/4db. These small tables fit nicely in the LUT
structure of an FPGA. Then, add log due to the mantissa to
the log due to the exponent, and you are done.
Tim Nicolson wrote:
> hi all. I'm currently implementing an image processing
> algorithm in hardware. The ip algorithm requires that I
> compute logarithms. This can prove quite a
> computationally expensive operation, but I only need
> accuracy down to around 4/5 significant
> figures. Currently, as binary floats are represented as
> m*2^e, where m is a number between 1-2, I have
> approximated the log function between 1-2 with a cubic
> polynomial. I then just scale the base2 exponent and add
> it to the result of the poly. This method is inexpensive
> but gives limited accuracy. Operations shown below z = a
> + b*mant + c*mant^2 + d*mant^3;
>
> if (e ~= 0)
> z = z + exp * C1;
> end; This requires 6* and 4+. Unfortuately, adding extra
> terms to the poly increases the accuracy slowly. So....
> Does anyone know of a better way of computing the
> logarithm of a base2 fp number? I have examined the c
> library log function (given below), though i don't see
> quite how it works.It says it's using Newtons method but
> it isn't iterative. Could it have been used to generate
> the polynomial prior to use in this algorithm. In which
> case, how, ... so I can develope a less costly
> algorithm. Thanks very much for your time. Tim Tim
> NicolsonReseach
> EngineerQinetiQMalvernUKt.nicolson@signal.qinetiq.com here's
> the c code! /* Get the exponent and mantissa where x = f
> * 2^N. */
> f = frexpf (x, &N); z = f - 0.5; if (f >
> __SQRT_HALF)
> z = (z - 0.5) / (f * 0.5 + 0.5);
> else
> {
> N--;
> z /= (z * 0.5 + 0.5);
> }
> w = z * z; /* Use Newton's method with 4 terms. */
> z += z * w * (a[0]) / ((w + 1.0) * w + b[0]); if (N !=
> 0)
> z = (N * C2 + z) + N * C1; if (ten)
> z *= C3; return (z);
> }
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin
Franklin, 1759
Article: 49857Thanks Joe, I like your neat solution. The chance of 2 changing together is very low in my case so I've ignored it but I'll keep your suggestion for future use. Best regards PhilArticle: 49858
On 21 Nov 2002 17:16:10 -0800, stevetshannon@yahoo.com (Steve T Shannon) wrote: >So, I'm trying to build an optical transceiver, and I was reading up >on data encoding schemes. Sure enough, 8B/10B looks like what I want, >and low and behold, there are lots of reference implementations of it >made available by xilinx (through coregen and Xapp336). However, I'm >worried about the IBM patent -- by my calculations, it should have >expired in 2001, yet the xilinx app note from 2002 still has the scary >patent warning. > >Any thoughts? Is xilinx just covering themselves, or are there still >patents related to this encoding scheme i should be worried about? If >so, has anyone had any success with other schemes for encoding to >optical? > Hummm. Publication date of 1984, priority date June 30, 1982. I was working on a digital video system using an 8B10B code before that date. Not necessarily the exact same code, and it was implemented in a single ROM (pair of ??) rather than broken down into smaller coders. Therefore it may not count as "prior art" for the specific patent cited. Therefore unless you are using the exact same codec approach, it would surprise me if there were patent concerns. Caveat: I haven't looked at the reference implementations to see if they do. Given the availability of BlockRams it wouldn't surprise me if a direct implementation of the code wasn't simpler anyway. - BrianArticle: 49859
There are some manufacturers that don't publish the footprints of their devices. That would be an appreciated use of the blank pages. I could have a look at the pinout and figure out what is missing, eg which 4 pins are missing on 672 BGA, since 26^2 is 676. Is that asked too much to have a page describing the foot print ? Or is there some hidden knowledge, that everything is clear ? Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 49860
"Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag news:3DDE242D.43726E9@andraka.com... > While an FPGA on wirewrap can be done if extreme attention is paid to > both the wirewrap and the design of the timing of the I/O, I hardly > recommend it, especially to the beginner. Edge speeds on modern > devices make it very difficult to avoid signaling problems. Do > yourself a big favor and either use one of the many pre-fabricated > boards, or make a proper PWB (at least 4 layers, please!) and save > yourself many hours of grief. 200% ack!!! This should become a BIG point in the FAQ?! -- MfG FalkArticle: 49861
Hi, I'm using conversion functions such as CONV_STD_LOGIC_VECTOR and CONV_SIGNED in my design code (VHDL). Would these cause any problems in synthesis or anywhere in the future OR can they be used freely wihtout any worries ? Thanks, PrashantArticle: 49862
Vikram wrote: > I am not sure if this will help, but try putting the following in your > UCF file for the input clock "GCK0" - > > NET "GCK0" LOC=p80; > NET "GCK0" TNM_NET="GCK0"; > TIMESPEC "TS_GCK0" = PERIOD "GCK0" 48 MHz HIGH 50 %; > INST DLL_INST LOC="DLL0"; > > Vikram. Hello, If i create a new project with same design and INST DLL_INST LOC="DLL0", then the synthesis or mapping will be stopped by an error. (DLL_INST is a name of module (example clkdll)) error is like : "...Unable to combine the following symbols into a single GCLKIOB component: .... Each of the following constraints specifies an illegal physical site for a component of type GCLKIOB:...." (x) But if i delete all the "inst dll_inst LOC="DLL0" lines, then xilinx the synthesis, mapping and programming are possible (without any error message). If if i insert the lines after it (x), then the syntheis, mapping and programming are possible (without any error message). Sadly there are no clocksignal after clk0. I will be glad, if i can get any informations or answers. with kind regards StefanArticle: 49863
Rene Tschaggelar napisal(a): >There are some manufacturers that don't publish the footprints >of their devices. That would be an appreciated use of the blank >pages. I could have a look at the pinout and figure out what >is missing, eg which 4 pins are missing on 672 BGA, since 26^2 is >676. >Is that asked too much to have a page describing the foot print ? >Or is there some hidden knowledge, that everything is clear ? On Altera web page there are PCB files and gerbers of BGA packages. -- Pozdrowienia, Marcin E. Hamerla "Spiżowy król spoglądał z niesmakiem na zwożonych autokarami ludzi, z ich pracowicie przygotowanymi kukłami, trumienkami, krzyżami, szubienicami i innymi wiecowymi gadzetami."Article: 49864
Use the IEEE numeric_std conversions instead. Those are a true
standard, where the synopsis std_logic functions are not (there are
differences between tools that could cause the design to work on one
tool and not on another). Numeric_std also avoids the type conflicts
inherent in the std_logic functions.
Prashant wrote:
> Hi,
>
> I'm using conversion functions such as CONV_STD_LOGIC_VECTOR and
> CONV_SIGNED in my design code (VHDL). Would these cause any problems
> in synthesis or anywhere in the future OR can they be used freely
> wihtout any worries ?
>
> Thanks,
> Prashant
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49865"Leon Heller" <leon@heller123.freeserve.co.uk> schrieb im Newsbeitrag news:arlte9$gqk$2@newsg4.svr.pol.co.uk... > You can't use wire-wrap or point-to-point wiring, though. That was the point The are universal PCBs for QFP packages. -- MfG FalkArticle: 49866
Marcin E. Hamerla wrote: > Rene Tschaggelar napisal(a): > > >>There are some manufacturers that don't publish the footprints >>of their devices. That would be an appreciated use of the blank >>pages. I could have a look at the pinout and figure out what >>is missing, eg which 4 pins are missing on 672 BGA, since 26^2 is >>676. >>Is that asked too much to have a page describing the foot print ? >>Or is there some hidden knowledge, that everything is clear ? > > > On Altera web page there are PCB files and gerbers of BGA packages. Ah, I found the footprints - somewhat odd to not have them in the datasheets. But there were no gerbers and no pcb files. Thanks anyway. ReneArticle: 49867
"Kevin Brace" <kevinbraceusenet@hotmail.com> wrote in message
news:d134a01690d324cf64b16af0371b5f51.52472@mygate.mailgate.org...
> Speedy Zero Two wrote:
<SNIP>
Thanks Kevin,
Given what you have said I think I should be able to convince the bean
counters to grant me two shekels for the spec :-)
There are too many issues to ignore it.
I have probably spent more time trying to save money but starting from
scratch, I feel I now have a good understanding.
I doubt that I have posted my last PCI question.
Most appreciated,
Dave
Article: 49868Rene Tschaggelar napisal(a): >>>There are some manufacturers that don't publish the footprints >>>of their devices. That would be an appreciated use of the blank >>>pages. I could have a look at the pinout and figure out what >>>is missing, eg which 4 pins are missing on 672 BGA, since 26^2 is >>>676. >>>Is that asked too much to have a page describing the foot print ? >>>Or is there some hidden knowledge, that everything is clear ? >> >> >> On Altera web page there are PCB files and gerbers of BGA packages. > >Ah, I found the footprints - somewhat odd to not have them in the >datasheets. But there were no gerbers and no pcb files. Try again: https://www.altera.com/support/software/download/gerber/dnl-gerber.jsp -- Pozdrowienia, Marcin E. Hamerla "What is it about audio that brings out all the idiots?"Article: 49869
You're welcome Phil. I just thought of a possible problem:
It will not work if two signals change at same time.
>> toggling_output <= A xor B xor C ..........
If A and B change at the same time, you don't have any chances
in the output.
So you will have to store the last status of all signals
before the clock stop.
Status(n downto 0) <= A & B & C ..........;
process(clk, reset) -- Store the value when clock is active
begin
if reset='1' then
LastStatus <= (others=>'0');
elsif clk'event and clk='1' then
LastStatus <= Status;
end if;
end process;
-- Produce falling edge
falling_edge_only <= '0' when (LastStatus/=Status) else '1';
-- Or if you need to make sure that the fallign edge won't happen
-- when clock is on
-- falling_edge_only <= '0' when (LastStatus/=Status)
-- and clock_is_off='1' else '1';
Joe
Article: 49870Thanks for the good ideas! I did a quick check on one particular simulation and it looked like the range of x values was quite small. Even though the range is small I should definately get an idea of how sensitive the system is to these values first. I do like the idea of an upshift followed by multiplication by a constant and as Jay mentioned would be easy to add into the model. At this stage I am working with a simulink model and will be using system generator to compile the design into vhdl just because it is a quick and easy approach and I can easily verify the functionality of the design. Obviously for getting the most use of the fpga I will eventually move away from system generator approach work in VHDL. Upon thinking of a way of maximizing the number of neurons I could simulate in one device and also most efficiently using the hardware I think that eventually I will probably create some sort of "neuron processor" around each multiplier that I have in a Virtex 2. There is only a small number of operations that I need to perform the numerical integration required to solve the system. I think a custom cpu capable of the following operations (load, store, mult, add/sub, (maybe a few more)) could be created and the code to implement many neurons loaded into the 18kbit block ram associated with each multiplier. I've kind of been stuck on the idea of custom processors in fpgas ever since I spent a lot of time playing around with Jan's XSOC and successfully got a vhdl implementation of xr16 working. This application seems like a good one for having a large number of custom processors running in a single fpga. Under this scenario it would definately be helpful to have an algorithm for finding exp() that doesn't take many clock cycles (like the taylor series approach did), so thanks for the helpful ideas. The shift operations could be occuring at a much faster rate than the 100Mhz clock to the multipliers. The other place I might run into a little trouble is a single divide is also necessary to solve the equations. The professor I work for pointed out that it was in the form 1/(1+x) which again can be expanded into a taylor series. I didn't really see any nifty tricks for doing this division other that a look up table approach. I did read that there are CORDIC algorithms for doing this, but for now I will probably just take an approach that is easier for me to implement. Chip "Stan" <vze3qgji@verizon.net> wrote in message news:<1fjD9.17265$br6.6886@nwrddc03.gnilink.net>... > Depending on the precision and range of x, it might work to do a table > lookup. Expecially if you luck out for whatever reason, can it be that x > might only take on a fixed number of values by chance? > > Alternatively if you base it on 2^x, remember log a (x) = log b (x) / log b > (a), sorry it's too late at night for me to convert that into exponentials > but you might be able to do a combination of an upshift followed by > multiplication by a constant or something like that. -Stan > > > I've recently been examining possibilities for implementing the > > exponential function in a virtex 2. I am attempting to implement a > > simple neuron model (MacGregor) in a virtex 2 device using only one > > multiplier per neuron initially (eventually many neurons per > > multipier). The numerical integration scheme for the model is fairly > > straightforward except it includes an exponential function. After > > looking at a few possibilities (shift-add and look up table) it seems > > like simply using a built in multiplier to implement the taylor series > > expansion e^x = 1 + x + (x^2)/2! + (x^3)/3! + .... is a reasonable and > > easy way of solving this problem especially if I am using a multiplier > > anyway. I just thought I would see if anyone here has done this sort > > of thing before or if any of the fpga gurus here see any problems with > > this approach. > > > > Thanks for your help, > > > > ChipArticle: 49871
Hi!
Serial programmable CY22393/4/5 from CYPRESS
Datasheet
http://www.cypress.com/products/datasheet.cfm?partnum=CY22393/4/5
Regards!
Seiran Petikian
Seytronix
Anand wrote:
> Hi everybody,
>
> I am looking for a programmable oscillator for a board consisting
> mainly of a Xilinx Virtex 2000E . (XCV2000E)
>
> For this purpose I looked at DS1075 econ-oscillator ,but this
> oscillator is 5 V.
> On the other hand the Virtex-E I/O's ( I assume that I/O's include
> clock inputs)are 3.3 .
>
> Is there a solution for this problem ?
>
> I need to be able to program the clock in-circuit ?
>
> please do reply,
>
> thanks very much ,
> Anand Kulkarni
Article: 49872
Hi,
I am a newbie in FPGA.Currently I am looking the Virtex TM
2.5V datasheet.In Figure 5 of DS003-2.pdf Page 5, there is a detailed view
of Virtex Slice.But I can't understand what WSO,WSH,DI,DG do in the CLB.
Seems like WSO and WSH provide the WE signal and DI,DG provide the data.
Can anyone specify these control logics to me?
Thank you very much!
sincerely
-------------
Kuan Zhou
ECSE department
Article: 49873Jay wrote: > 3 ideas for you: > > 1) The input structure for the Vertex has a facility to insert a fixed > delay which has the effect of increasing your hold time for the case > that you used the DLL and violated hold time. > 2)The DLL has a facility to "trim" the delay that its inserting, maybe > the resolution is fine enough to get the timing relationship you > desire. > 3) Is there a speed grade available that matches you input data > timing, you are SO close. > > Best Regards > > President, Quadrature Peripherals > Altera, Xilinx and Digital Design Consulting > email: kayrock66@yahoo.com > http://fpga.tripod.com > ----------------------------------------------------------------------------- A note on #2 above: What you need to look for is `MEDDELAY' in the constraints guide. Also - If you've not yet committed your choice of device you might consider using a Virtex-2 since their DLLs (called DCMs = DigitalClockManagers for V-2) have the ability to phase shift the output clock at a resolution of TClk/256.Article: 49874
Marcin E. Hamerla <mehamerla@pro.onet.pl> wrote: : Rene Tschaggelar napisal(a): :>>>There are some manufacturers that don't publish the footprints :>>>of their devices. That would be an appreciated use of the blank :>>>pages. I could have a look at the pinout and figure out what :>>>is missing, eg which 4 pins are missing on 672 BGA, since 26^2 is :>>>676. :>>>Is that asked too much to have a page describing the foot print ? :>>>Or is there some hidden knowledge, that everything is clear ? :>> :>> :>> On Altera web page there are PCB files and gerbers of BGA packages. :> :>Ah, I found the footprints - somewhat odd to not have them in the :>datasheets. But there were no gerbers and no pcb files. : Try again: : https://www.altera.com/support/software/download/gerber/dnl-gerber.jsp For me it looks like Altera like Xilinx in their application notes don't make proposals for the decoupling capacitors. Or does Altera? I refrain to sign up yet on another site just for checking that fact. Can anybody confirm? Thanks -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z