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kayrock66@yahoo.com (Jay) wrote: >yes > >President, Quadrature Peripherals >Altera, Xilinx and Digital Design Consulting >email: kayrock66@yahoo.com >http://fpga.tripod.com >-----------------------------------------------------------------------------"hiro" <hiro-ta@pd6.so-net.ne.jp> wrote in message news:<aris55$2tu$1@news01be.so-net.ne.jp>... >> Dear all, >> >> I have a question about Xilinx's ISE tool regarding >> clock enable input of FFs. >> I use FFs with clock enable input(that is FDCE) and >> constrain clock frequency with PERIOD attribute. >> The timing analyzer will check all data paths between >> two FFs whether the sets of path delay are within specified >> value with respect to the constrain. >> Likewise, are paths to clock enable input of FFs also >> setup/hold timing-checked at this time ? >> >> Thanks, >> >> Hiro It makes no fucking sense when you read it. INSERT 4 LINES OF SIGNATURE EMAIL AND WEB REFENCES HERE -----------------------------------------------------------------------------ATTRIBUTION I have a question about Xilinx's ISE tool regarding clock enable input of FFs. I use FFs with clock enable input(that is FDCE) and constrain clock frequency with PERIOD attribute. The timing analyzer will check all data paths between two FFs whether the sets of path delay are within specified value with respect to the constrain. Likewise, are paths to clock enable input of FFs also setup/hold timing-checked at this time ? Oh and by the way what's wrong with top posting?Article: 49826
I wanted to thank you ALL for your invaluable feedback. These plus John Cooley's DAC report on SystemC have answered many questions. Alfredo.Article: 49827
Nicholas C. Weaver <nweaver@ribbit.cs.berkeley.edu> wrote: > I don't see why. > Unstable equilibrium state: Noise in either direction kicks it away. > Next to the unstable equilibrium state: Noise away kicks it away. > Noise TOWARDS kicks it towards. > So in the unstable equilibrium point, all noise kicks away. Just > outside of it, half the noise kicks it away. But there are two ways for you to be next to equilibrium: above and below. If you limit yourself to these three states, you have equal probability of being in any of the three: "under", "at", "over". In two of these states "under" and "over", you have 1/2 chance of staying away from metastability, and 1/2 chance of deteriorating. When you are "at", there is a 1/1 chance of improving. If you put these together, noise has a 1/2*1/3 + 1/2*1/3 chance of hurting you, a 1/1*1/3 chance of hurting you, and a 1/2*1/3+1/2*1/3 chance of leaving you in the same place. This is only a very rough approximation, but I'm fairly certain that a detailed statistical analysis of the surrounding states along these lines will prove that noise doesn't change anything (in fact, I'd be surprised if it hadn't been done already). If anyone sees something wrong with my logic, please let me know, probabilities were never my strong suit. > Of course, "MEET THE SETUP AND HOLD TIMES" is a lot easier to say in > general. :) Amen to that :) > -- > Nicholas C. Weaver nweaver@cs.berkeley.edu Pierre-Olivier LapriseArticle: 49828
Does anyone have an estimate of slices used in a virtex-II for this code(encoder and decoder)? In my design I would have to implement 16 encoders and 16 decoders on a 3000 chip. Just trying to find out up front the possibility of using this. Thanks BryanArticle: 49829
"Nicholas C. Weaver" wrote: > > In article <utiom46n1pu6a7@corp.supernews.com>, > Hal Murray <hmurray@suespammers.org> wrote: > >>I have tried to analyze the behaviour of such an analogy in the presence > >>of noise, but I don't have the tools to do it rigorously. It may well > >>be possible to shorten the metastable time with noise, but I really > >>can't prove it one way or the other. > > > >Somebody mentioned noise recently, but I'll repeat. It doesn't work. > >It kicks the system toward the stable point just as often as it helps > >you by kicking the system in the right direction. > > I don't see why. > > Unstable equilibrium state: Noise in either direction kicks it away. > > Next to the unstable equilibrium state: Noise away kicks it away. > Noise TOWARDS kicks it towards. > > So in the unstable equilibrium point, all noise kicks away. Just > outside of it, half the noise kicks it away. Ever hear of the wandering drunk? When you have noise that is random, the net movement will tend to bring you back to your starting point. The only way I can see noise helping bring you out of metastability is for it to put you at a point where the push away from the center is higher. I think this would make the noise contribution uneven since any movement away from center will create *increased* acceleration away from center. Since noise is normally distributed in a gaussian or similar distibution, larger kicks will be less frequent than smaller ones. But the bottom line is that it is all academic. Metastability is characterized by a couple of constants in an equation. These constants are not calculated, they are measured. This is done in the presence of noise. So any numbers you have will have already included any benificial effects of noise. If your circuit has more or less noise, it will be exceedingly hard to get any reliable result from considering the noise since it is hard to measure and even harder to control. Like a timing delay in a chip, noise can be minimized, but you can't guarantee a minimum without a lot of extra work. So what is that point of trying to consider it in this analysis of metastability? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 49830
Here's my 2 cents... Since your going to have to truncate your series expansion at some point anyway, then you're talking about an approximation. Well 2 is approximately "e". So you could compute 2^x instead which is trivial in digitalland, its just a shift. You'd probably want to model your network with this approximation but my limited experience with these things says you're still in the ball park. Regards President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- john_doebertson@yahoo.com (Chip) wrote in message news:<49cdb4ba.0211211045.5c28d468@posting.google.com>... > Hello all, > > I've recently been examining possibilities for implementing the > exponential function in a virtex 2. I am attempting to implement a > simple neuron model (MacGregor) in a virtex 2 device using only one > multiplier per neuron initially (eventually many neurons per > multipier). The numerical integration scheme for the model is fairly > straightforward except it includes an exponential function. After > looking at a few possibilities (shift-add and look up table) it seems > like simply using a built in multiplier to implement the taylor series > expansion e^x = 1 + x + (x^2)/2! + (x^3)/3! + .... is a reasonable and > easy way of solving this problem especially if I am using a multiplier > anyway. I just thought I would see if anyone here has done this sort > of thing before or if any of the fpga gurus here see any problems with > this approach. > > Thanks for your help, > > ChipArticle: 49831
So, I'm trying to build an optical transceiver, and I was reading up
on data encoding schemes. Sure enough, 8B/10B looks like what I want,
and low and behold, there are lots of reference implementations of it
made available by xilinx (through coregen and Xapp336). However, I'm
worried about the IBM patent -- by my calculations, it should have
expired in 2001, yet the xilinx app note from 2002 still has the scary
patent warning.
Any thoughts? Is xilinx just covering themselves, or are there still
patents related to this encoding scheme i should be worried about? If
so, has anyone had any success with other schemes for encoding to
optical?
Thanks for the help,
...Steve
Article: 49832In article <3DDD8260.76B7152F@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >Ever hear of the wandering drunk? When you have noise that is random, >the net movement will tend to bring you back to your starting point. Actually, a random walk of N steps, on average, sees you deviating Sqrt(N). And if the drunk is standing on a fairly narrow walkway, with a cliff on each end, he will drop off thanks to his random wandering. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 49833
If you look at your report with the optional stuff (in menu entry View/Options?) you can see the physical connections. If, for instance, it says the net going into this element is the .T port of an IOB, then it's probably a tristate-to-pad time. I miss having the timing analyzer reports defaulting to the physical implementation. "Daryl" <eengineer@eat.com> wrote in message news:Xns92CD8A16157F0eeD3eastdaycom@130.133.1.4... > Hello there, > > In my recent design, I notice that a timing parameter named "Tiotp" > which is reported by ISE 5 tools. > It seems a IOB timing parameter, but I cannot find any description on > it in the handbook of VirtexII. > If I remember rightly, for the recent version of ISE, it is "Tioop" of > IOB which means propagation delay from the O input of the IOB to PAD. > > The FPGA gurus and Xilinx people, would you explain it to me? > > > > > -- > Badahana >Article: 49834
Isn't it the case that you "can't get there from here?" To get a 400MHz clock for the feedback for the second DLL, you need a 2x output. The CLKDLLHF doesn't have a 2x output. You can't put 200MHz into a CLKDLL and you can't get a 2x output from a CLKDLLHF. 320MHz is the top end for the output frequency. Good luck with your design. "John Retta" <jretta@rtc-inc.com> wrote in message news:argf8n$j4p$1@slb6.atl.mindspring.net... > I have an application where I am using two CLKDLLs to generate a > 4x clock - 400 Mhz from a base of 100 Mhz. The applicable Xilinx > data sheet for Spartan IIe specifies a max Input clock frequency for > -7 speedgrade devices of 160 Mhz for CLKDLL, and 320Mhz for > CLKDLLHF. > > Does the max Input clock frequency refer to just the CLKIN frequency, > or does it also include the CLKFB input? > > For the second DLL, the CLKIN is 200 Mhz, but the CLKFB is 400 Mhz. > > Thanks in advance. > > -- > Regards, > John Retta > > email : jretta@rtc-inc.com > web : www.rtc-inc.com > > > >Article: 49835
Does it also work for random musings on comp.arch.fpga?
"Nicholas C. Weaver" wrote:
>
> Actually, a random walk of N steps, on average, sees you deviating
> Sqrt(N). And if the drunk is standing on a fairly narrow walkway,
> with a cliff on each end, he will drop off thanks to his random
> wandering.
> --
> Nicholas C. Weaver nweaver@cs.berkeley.edu
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49836I don't think you have to worry about that patent. It is a methode to break up 8B/10B encoding into 5B/6B + 3B/4B and it is expired. If you just do a ram lookup you should have no problem. Steve "Steve T Shannon" <stevetshannon@yahoo.com> wrote in message news:c5e9863d.0211211716.5caee767@posting.google.com... > So, I'm trying to build an optical transceiver, and I was reading up > on data encoding schemes. Sure enough, 8B/10B looks like what I want, > and low and behold, there are lots of reference implementations of it > made available by xilinx (through coregen and Xapp336). However, I'm > worried about the IBM patent -- by my calculations, it should have > expired in 2001, yet the xilinx app note from 2002 still has the scary > patent warning. > > Any thoughts? Is xilinx just covering themselves, or are there still > patents related to this encoding scheme i should be worried about? If > so, has anyone had any success with other schemes for encoding to > optical? > > Thanks for the help, > ...SteveArticle: 49837
tom_robinson6@yahoo.com (Tom) wrote in message news:<74172c34.0211210959.52b18f74@posting.google.com>... > Can anybody give me (a NOVICE in FPGA programming) some advice on how > to implement a look up table on an FPGA? Prefferably using Xilinx > software. > > Thank you > Tom How big is the table? You can use distributed ram for small tables or block ram for larger tables. Read about different kind of rams in "Libraries Guide" and in the datasheet for your device. Initial values are set with INIT_xx attribute, look it up in "Constranits Guide". Also you can use ISE "Language Templates" to instantiate rams. Regards DmitriArticle: 49838
Pierre-Olivier Laprise <plapri@tesserae.McRCIM.McGill.EDU> wrote: >Nicholas C. Weaver <nweaver@ribbit.cs.berkeley.edu> wrote: >> I don't see why. >> Unstable equilibrium state: Noise in either direction kicks it away. >> Next to the unstable equilibrium state: Noise away kicks it away. >> Noise TOWARDS kicks it towards. >> So in the unstable equilibrium point, all noise kicks away. Just >> outside of it, half the noise kicks it away. > >But there are two ways for you to be next to equilibrium: above and >below. If you limit yourself to these three states, you have equal >probability of being in any of the three: "under", "at", "over". >In two of these states "under" and "over", you have 1/2 chance of >staying away from metastability, and 1/2 chance of deteriorating. >When you are "at", there is a 1/1 chance of improving. If you put >these together, noise has a 1/2*1/3 + 1/2*1/3 chance of hurting you, >a 1/1*1/3 chance of hurting you, and a 1/2*1/3+1/2*1/3 chance >of leaving you in the same place. This is only a very rough >approximation, but I'm fairly certain that a detailed statistical >analysis of the surrounding states along these lines will prove >that noise doesn't change anything (in fact, I'd be surprised if >it hadn't been done already). If anyone sees something wrong >with my logic, please let me know, probabilities were never my >strong suit. I see plenty wrong. You assume the 'band' where equilibrium exists is large and the noise is small. A more realistic ball and hill analogy of metastability is you have a big hill with steep sides. Logic state 0 is at the bottom of one side and logic state 1 at the other. The peak of the hill is rounded, perhaps even a small flat section but (for modern fast logic at least) it is very narrow. The input signal is a ball above the hill moving between logic 1 and 0, when you 'clock' the analogy the ball stops instantly and drops onto the hill which is almost always straight to the bottom at one side or the other. If you get unlucky you clock while the ball is moving between states and it still almost always falls onto one side or the other and quickly rolls to the bottom. Once in a blue moon the ball is dropped and lands smack on the peak of the hill and sits there for a relatively long time. In the recent Xilinx tests the metastability capture window was about 0.03fs. Say the internal transition time between states is 100fs (guessing, sounds fast to me) then if the hill was a mile across the peak where metastability can exist is about 18 inches wide. So if you apply 6 inches of noise to the ball or the hill it won't make much difference, however, apply 5 feet (still less than 0.1% of the hill width) and the ball will be rolling down one side or the other after the first noise impulse. The results would have some randomness because noise is random which is why I previously suggested a high frequency agitation signal. Vibrating the hill side to side with 5 feet amplitude would limit the duration of metastability to a fraction of one cycle of the agitation signal + however long it takes the ball to roll down the side of the hill. What is the practicality of injecting say 10mV at a few GHz into flipflop feedback paths? Not very I guess.Article: 49839
Hi Stephane,
The following should help answer some of your questions.
1) Logiclock_import and logiclock_export ONLY deal with
assignments/constraints. They are only useful when there are logiclock
regions present.
2) When a VQM file is generated it is treated as though it were the top
level, so yes there are IOs in it. In the QII 2.0 release the compiler will
give the warnings that you are seeing wrt to IOs from the lower level; just
ignore them. Later versions of Quartus do not issue these warnings.
So, lets assume you have a lower level design: BOTTOM. And a top level
design: TOP. TOP instantiates BOTTOM (perhaps multiple instances). When the
user is finished working on BOTTOM, then he should use Logiclock_export to
create a BOTTOM.ESF file which contains all the placement information and
other constraints that were used. Also, they should generate a BOTTOM.VQM
to preserve the synthesis.
In the top level, the user should have a source file: TOP.VHD which makes
instances of BOTTOM. To compile TOP, the user also needs to place an
appropriate source file for BOTTOM in the TOP project directory. In this
case they should use the BOTTOM.VQM file that was generated earlier. So the
user should copy the BOTTOM.VQM and the BOTTOM.ESF file into the TOP project
directory.
Now they must use Logiclock_import to import the assignments/constraints
from the BOTTOM.ESF file into the TOP.ESF file. This is accomplished by:
#doing elaboration first:
cmp start "analysis_and_elaboration" "analysis_and_elaboration"
while {[cmp is_running]} {
after 10
update
FlushEventQueue
}
#Now they run the import command
cmp logiclock_import
The project is now ready to be compiled.
Hope this helps.
- Subroto Datta
Altera Corp.
"Mancini Stéphane" <stephane.mancini@inpg.fr> wrote in message
news:arie12$a2j$1@new-news.grenet.fr...
> Hi all,
> I'm trying to use the logick lock methodology from Altera but
> with little (if none) success. Furthermore, I would like to
> use scripts to perform all the steps.
> I'm using Leonardo 2002e and Quartus 2.0.
> The entry is VHDL.
> For the moment, I would like to try a very simple architecture which
> hierarchy is :
> A top level controleur_can_periodique embeds a module controleur_can
> and some processes.
> I managed to produce separate edif files for the entities
> and produce an atom controleur_can.vqm but I don't know how to
> import it on the top file. Indeed I do it but I don't know if
> I produced a good vqm file as I get messages such as :
>
> Info: WYSIWYG I/O primitives converted to equivalent logic
> Info: WYSIWYG I/O primitive
> controleur_can:inst_controleur_can|convertit~I converted to equivalent
logic
>
> did I put some I/O on my sub-module ? How to prevent this ?
> Also, why does quartus produces .sof file for the sub-module ?
>
> So, could someone tell me :
> - how many scripts do I need for leonardo, quartus (one for each module ?)
> and how to use them
> - what should I put in them
> - How, and when, to use the command cmp logiclock_import
> Indeed, the quartus compiler stops if I use it as stated in the Altera
> Application Note 195 (Scripting with Tcl ....)
> The following piece of code doesn't seems to work
> while { [cmp is_running] } {
> FlushEventQueue
> puts "--- Importing LogicLock Regions ---"
> # Import all LogicLock regions for the project.
> cmp logiclock_import
> }
> So I've tried to compile without logiclock_import (silly ?)
>
> Could someone give me some light ?
> It would be wonderfull if you have a set of simple VHDL files and all the
> scripts to produce the final .sof file.
>
> Thanks very much for your help
>
> Stephane Mancini
>
>
>
Article: 49840In article <3DDD9AB9.AF88ECD4@andraka.com>, Ray Andraka <ray@andraka.com> wrote: >Does it also work for random musings on comp.arch.fpga? Nope. Because mine start at "Step One, fall off the cliff". -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 49841
Depending on the precision and range of x, it might work to do a table lookup. Expecially if you luck out for whatever reason, can it be that x might only take on a fixed number of values by chance? Alternatively if you base it on 2^x, remember log a (x) = log b (x) / log b (a), sorry it's too late at night for me to convert that into exponentials but you might be able to do a combination of an upshift followed by multiplication by a constant or something like that. -Stan > I've recently been examining possibilities for implementing the > exponential function in a virtex 2. I am attempting to implement a > simple neuron model (MacGregor) in a virtex 2 device using only one > multiplier per neuron initially (eventually many neurons per > multipier). The numerical integration scheme for the model is fairly > straightforward except it includes an exponential function. After > looking at a few possibilities (shift-add and look up table) it seems > like simply using a built in multiplier to implement the taylor series > expansion e^x = 1 + x + (x^2)/2! + (x^3)/3! + .... is a reasonable and > easy way of solving this problem especially if I am using a multiplier > anyway. I just thought I would see if anyone here has done this sort > of thing before or if any of the fpga gurus here see any problems with > this approach. > > Thanks for your help, > > ChipArticle: 49842
Ray Andraka <ray@andraka.com> wrote in message news:<3DDC3176.D4C052EE@andraka.com>...
> process(clk)
> if rising edge(clk) then
> sync register<= slow input;
> sync z<= sync register;
> rising edge happened<= sync register and not sync z;
>
>
> Presumably you have a clock in your system that is faster than you slow i
> nputs. The above synchronizes the input to the local clock, then generat
> es a 1 clock wide pulse each time a rising edge is detected on the slow i
> nput (presumes that the slow input changes state and then stays that way
> for longer than the period of the clock.
Why can't we directly use the asynchronized input signal to trigger
flip-flop?
Synchronize all asynchronized input by a global clock, don't directly
connect the asynchronized input as clock or strobe signal. It will
guarantee more reliability of flip-flop or latch access.
I describe my experience at recent.
When I design my ISA interface card, I suffer a problem. The problem
is when I write the ISA port continuously, only sometime writing is
ok. Even if I insert many ISA bus wait states. It still doesn't write
data reliablely.
Although FPGA simulation is correct and maxima working frequency of
FPGA device is more fast than ISA spec. I guess the possible reason is
the asynchronized input controlling signal doesn't not meet the
setup/hold time of the flip-flops or latches. The following is my ISA
R/W VHDL.
#the un-reliable ISA port R/W VHDL about my design
port_en <= decode latched I/O address
P1:
PROCESS(IOW, IOR, port_en)
BEGIN
IF port_en='1' THEN
IF IOR='0' THEN
SD <= data_reg;
ELSIF IOW='0' THEN
data_reg <= SD;
ELSE
SD <= (OTHERS=>'Z');
END IF;
ELSE
SD <= (OTHERS=>'Z');
END IF;
END PROCESS;
#modified reliable ISA port R/W VHDL
P2:
PROCESS(BCLK)
BEGIN
IF rising_edge(BCLK) THEN
port_en_sync <= port_en;
IOR_sync <= IOR;
IOW_sync <= IOW;
END IF;
END PROCESS;
-- using the synchronized control signal (IOR_sync, IOW_sync,
port_en_sync)
-- instead of the asynchronized signal (IOR, IOW, port_en)
P1:
PROCESS(IOR_sync, IOW_sync, port_en_sync)
...
END PROCESS;
Article: 49843
The difficulty with a separate input clock is if you have many of them, which I think was
the case that started this thread, you run out of clock nets to put them on. As a result,
you have to route the clock on general interconnect, which in turn means that you need to
be very careful about clock skew and relative delay between your clock and your data.
Balancing the delays pretty much means hand routing to keep the delays under control.
Ru-Chin Tsai wrote:
> Ray Andraka <ray@andraka.com> wrote in message news:<3DDC3176.D4C052EE@andraka.com>...
> > process(clk)
> > if rising edge(clk) then
> > sync register<= slow input;
> > sync z<= sync register;
> > rising edge happened<= sync register and not sync z;
> >
> >
> > Presumably you have a clock in your system that is faster than you slow i
> > nputs. The above synchronizes the input to the local clock, then generat
> > es a 1 clock wide pulse each time a rising edge is detected on the slow i
> > nput (presumes that the slow input changes state and then stays that way
> > for longer than the period of the clock.
>
> Why can't we directly use the asynchronized input signal to trigger
> flip-flop?
> Synchronize all asynchronized input by a global clock, don't directly
> connect the asynchronized input as clock or strobe signal. It will
> guarantee more reliability of flip-flop or latch access.
>
> I describe my experience at recent.
> When I design my ISA interface card, I suffer a problem. The problem
> is when I write the ISA port continuously, only sometime writing is
> ok. Even if I insert many ISA bus wait states. It still doesn't write
> data reliablely.
> Although FPGA simulation is correct and maxima working frequency of
> FPGA device is more fast than ISA spec. I guess the possible reason is
> the asynchronized input controlling signal doesn't not meet the
> setup/hold time of the flip-flops or latches. The following is my ISA
> R/W VHDL.
>
> #the un-reliable ISA port R/W VHDL about my design
>
> port_en <= decode latched I/O address
> P1:
> PROCESS(IOW, IOR, port_en)
> BEGIN
> IF port_en='1' THEN
> IF IOR='0' THEN
> SD <= data_reg;
> ELSIF IOW='0' THEN
> data_reg <= SD;
> ELSE
> SD <= (OTHERS=>'Z');
> END IF;
> ELSE
> SD <= (OTHERS=>'Z');
> END IF;
> END PROCESS;
>
> #modified reliable ISA port R/W VHDL
>
> P2:
> PROCESS(BCLK)
> BEGIN
> IF rising_edge(BCLK) THEN
> port_en_sync <= port_en;
> IOR_sync <= IOR;
> IOW_sync <= IOW;
> END IF;
> END PROCESS;
>
> -- using the synchronized control signal (IOR_sync, IOW_sync,
> port_en_sync)
> -- instead of the asynchronized signal (IOR, IOW, port_en)
> P1:
> PROCESS(IOR_sync, IOW_sync, port_en_sync)
> ...
> END PROCESS;
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 49844nospam wrote: > <snip> > The results would have some randomness because noise is random which is why > I previously suggested a high frequency agitation signal. Vibrating the > hill side to side with 5 feet amplitude would limit the duration of > metastability to a fraction of one cycle of the agitation signal + however > long it takes the ball to roll down the side of the hill. > > What is the practicality of injecting say 10mV at a few GHz into flipflop > feedback paths? Not very I guess. With CMOS Logic, the PSRR is very poor (1/2), so wiggling either supply wiggles the threshold, so it's not as difficult as it first seems. Hence my earlier suggestion to _actually_test_ a FPGA, with a LUT configured with, and without the surrounding ones 'active', and see if any difference can be seen in the metastability numbers. For a stimulus I would choose a simple gate-delay chain with the LUT.D tapped from appx the middle. Single gate delays are << 1ns, and the internal rise/fall will be faster again. So you will get some mv of 'ground bounce' in the local supply fabrics. -jgArticle: 49845
Hi Jay, sorry to hear, that the old Spartan family are not supported by the free web-pack, as I had already ordered two pieces of it :-( My consideration was to play around first with a part in a plcc84 case in order to use a plcc84 socket to move my fpga to different test boards with hardware wired together by simple thin wire ;-) Thanks for your reply and I would take in account all hints for my next steps in fpga programming. Bye Markus ============================================ Markus Wolfgart DLR ============================================ PS.: remove the xx_ from email adr. to reply ============================================Article: 49846
Ok Luigi Ho cominciato a costruirlo, dato che proprio devo cominciare a lavorarci. Saluti P.S. mica sei del centro italia??? (dal cognome proprio no) 73 luigi funes <fuzzy8888@hotmail.com> wrote in message wX5C9.11494$Ka3.344795@twister1.libero.it... > Rinux ha scritto nel messaggio ... > >Hi all > >Anyone know a sinple way to program a max3000 ?? > > > >regard > > > Ciao Rinux, > Altera MAX3000 are in system programmable devices. > The best way to program it is with a Byteblaster cable. > Bye > > Luigi > > >Article: 49847
"Ray Andraka" <ray@andraka.com> wrote in message news:3DD2FBB9.76B321B@andraka.com... (snip) > > In the 4000/spartan series parts you basically needed the LUT to get at the bit > outputs from the carry chain, so unless you weren't using particular bits, you > still had to use the LUTs there. The advantage the 4K carry chain had was that if > you were only using the output at the end of the carry chain, perhaps as a > subtractive comparator, then the LUTs were available for other things with the > restriction that a few of the inputs were shared with the carry chain. That made > certain functions more compact than can be done in Virtex, but not your case. One that I used to like was a MAX(x,y) function, to select the maximum of two numbers. The carry chain does the compare, and the LUTs do the mux to select the maximum (or minimum) value. Someday I will have to see how to do this in Virtex. -- glenArticle: 49848
"Ray Andraka" <ray@andraka.com> wrote in message news:3DDB109D.D0CD8056@andraka.com... (big snip) > > The bottom line is that carry save adder trees DO NOT MAKE SENSE for FPGAs > that have dedicated adder resources. How about for adding a large number of very small numbers. Say for adding 32 one bit numbers, for example? -- glenArticle: 49849
hi tom,
the code below is a simple 4-input LUT using the conversion functions. you
just have generate a instace of this including a generic attribute where the
"hard-coded" hex value is assigned.
(not fine, but it works ;)
jens
----------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity MY_X_LUT4 is
generic (INIT : bit_vector(15 downto 0));
port(
ADR0 : in std_logic;
ADR1 : in std_logic;
ADR2 : in std_logic;
ADR3 : in std_logic;
O : out std_logic
end MY_X_LUT4;
architecture MY_X_LUT4_arch of MY_X_LUT4 is
begin
O <= TO_STDLOGICVECTOR(INIT)(conv_integer(std_logic_vector'(ADR0, ADR1,
ADR2, ADR3)));
end MY_X_LUT4_arch;
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