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Hi, I trying to understand programming fpga`s. Have this book ( The practical Xilinx designer lab book written by David Van den Bout) Although I`ve got the latest version of Xilinx`s software (WebPack) I want the older version which is used with the book (Xilinx Foundation 1.5 Series Software) so I can `catch up` with the book Anybody knows where to get this older version? Tanks. Aroen. run@arun.demon.nlArticle: 50226
Hi there!
I am trying to find a memory module for my design, which I will download
in a Virtex. I use Xilinx ISE 4.2i and I tried the Xilinx parameterizable
RAM for Virtex from their IPcenter, but when I tried the Post Place & Route
Simulation, in many cases, the output was undefined. Does anyone know where
I can find vhdl code for memory modules that actually works!!?
Thank you!
Dimitris
Article: 50227Ralph Mason wrote: > "eric - Mtl" <notervme@sympatico.ca> wrote in message > news:3LsH9.6981$3J2.987911@news20.bellglobal.com... > >>the processor can even rely on the VGA ram to hold it's software, thus >>making the whole design very cost effective ... >> > > > Assuming one could find a ready supply of ISA video cards. > > Ralph > > You'll probably have trouble finding them at the board level, using ISA form factor, however many PC104 video cards are based on ISA chips, such as http://www.technoland.com/tl_pc104_vga01.htm and the chips are still available for embedded uses from sources such as Asiliant (Chips & Tech) their ISA chip is : http://www.asiliant.com/65545.htm (BTW, you'll find in the main PDF a detailed description of the standard VGA registers) However, for new, much higher performance designs, and better long term availability, AGP bus would be required. AGP being based on a point to point version of PCI, it should not be out of reach to interface it using a FPGA (but obviously not as easy as an ISA device, by far) If you'd like to check it out : ftp://download.intel.com/technology/agp/downloads/agp20.pdf ftp://download.intel.com/technology/agp/downloads/AGPDesignGuide_20.pdf For devices that need CRT/LCD display, a FPGA and a mid range processor, using a standard PC graphic card both for the display function an as an optimised dual port memory controller certainly makes sense for both developement time, product complexity and cost. Eric. PS : For unobfuscated email, remove "not" and "me"Article: 50228
I think aoubt it this way: A regular "logic gate" is usually thought of as 2 input nand gate. Since you can make anything out of nand gates anything you can make can be expressed in the number of nand gates it would take to build the design. The total "System Gates" number is the maximum "potential gates" on the chip. By that I mean if had a design used every feature then you would need that many nand gates to build the design. Steve PS if you want to know what kind a area your design will take in a certain part you need to look at how many LUTs and Flops for a worst case number. "Steve" <steve1@mecca.com> wrote in message news:ee7ac4c.-1@WebX.sUN8CHnE... I have a pre-made USB interface design which claims to use 16K-20K gates, and I'm looking for an appropriate FPGA for implementing this. It seems that most FPGA's (I've checked several of the Virtex and Spartan series) report "system gates", and sometimes include "logic gates" as well. What is the difference between these two? For example, the SpartanXL XCS50XL says it has 13K-40K system gates and 20K max. logic gates. Where do the rest of the system gates go? Are they all for RAM? Also, what would the USB's gate count be referring to.. system gates or logic gates? Thanks! -SteveArticle: 50230
Anand wrote: > Hi everybody, > I have the following situation in my board design : > > (A)FPGA-pin--"R"-------T------connector--cable--connector------T-----FPGA-pin(B) > > R = series termination resistor > T = "5 mil width" PCB trace > More info : > The resistor is for series termination at the source. > The termination resistor value is 33 ohms. > The cable is a 3 feet long SCSI cable. > The connectors are 68-pin SCSI female,high density connectors. Looks good to me. Might want diode clamps at connectors if this is a customer cable. When you get a board, get A wiggling, put a scope on B, and optimize damping with R value. -- Mike TreselerArticle: 50231
>(A)FPGA-pin--"R"-------T------connector--cable--connector------T-----FPGA-pin(B) >The termination resistor value is 33 ohms. >The cable is a 3 feet long SCSI cable. >The connectors are 68-pin SCSI female,high density connectors. Are you running single ended or differential? What's the impedance of the SCSI cable? What's the impedance of your traces at each end and/or how long are they? Traces are usually close to 50 ohms. Depends on layer spacing. I think differential SCSI cables are >100 ohms. That will probably be close enough if you use it differentially. If you ground one side of the pair and use it single ended you might get a big reflection at the transition between trace and cable. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 50232
Assuming optimistically that trace-connector-cable-connector-trace haev a common characteristic impedance, you will have a one-way propagation time of about 7 ns, and a round-trip time of 14 ns for the reflection at the receiving end to reach the source A again. The FPGA output impedance ( depends on the strength chosen) plus R must equal the characteristic impedance. Thus you will se a half-amplitude step at the right-hand side of R, and the full reflection at B will double this to a full signal. This travels back to A where you can see its arrival a total of 14 ns later. You can adjust the excess amplitude or lack of amplitude by changing R. If the connection has impedance discontinuities, you can see thos as additional reflections, provided you have a fast scope. It's all textbook stuff. Peter Alfke, Xilinx Applications ============================ Mike Treseler wrote: > Anand wrote: > > > Hi everybody, > > I have the following situation in my board design : > > > > (A)FPGA-pin--"R"-------T------connector--cable--connector------T-----FPGA-pin(B) > > > > R = series termination resistor > > T = "5 mil width" PCB trace > > More info : > > The resistor is for series termination at the source. > > The termination resistor value is 33 ohms. > > The cable is a 3 feet long SCSI cable. > > The connectors are 68-pin SCSI female,high density connectors. > > Looks good to me. > Might want diode clamps at connectors if this is a customer cable. > > When you get a board, get A wiggling, > put a scope on B, and optimize damping with R value. > > -- Mike TreselerArticle: 50233
> > You want to measure power consumption of a single chip, or the whole > board? Measuring the power draw of a single chip in an operating system > is tricky, as you need to break all the power connections between the chip > and the rest of the board, and funnel it through a sensing resistor or > hall effect probe. > > Measuring total system power consumption should be easier. A DVM > with a current shunt can be used, just put it in series with each power > source coming into the board. Multiply each current times the voltage to > get power, add power for all voltages together to get total power. > > Without descibing the board in more detail, it is hard to get more > specific. > > Jon Thanks, I am going to use a PCI Board that will execute the loops of a software. I need to measure the power that will be expended in the pci board while the loops are being executed. I am using Xilinx PowerX to estimate the power but I need to experimentally validate the estimates. Also I want to see if we really can gain in using the PCI board as a coprocessor for executing the loops in hardware. Incidentally the boards that I have are from Alpha Data and Annapolis. So inserting a probe for a DVM is also pretty tricky ..Article: 50234
>I am going to use a PCI Board that will execute the loops of a software. > I need to measure the power that will be expended in the pci board >while the loops are being executed. I am using Xilinx PowerX to >estimate the power but I need to experimentally validate the estimates. >Also I want to see if we really can gain in using the PCI board as a >coprocessor for executing the loops in hardware. Incidentally the boards >that I have are from Alpha Data and Annapolis. So inserting a probe for >a DVM is also pretty tricky .. You might get some information by measuring the temperature of the chip. If you are willing to sacrifice a mother board, you could (maybe?) yank the pins from the connectors on the power rail you want to measure. Then you could add it back on through a meter. I think some PCI extender cards may have a way to measure current or let you provide current for the board under test separately. [Seems like a reasonable idea if you want to test lots of boards and don't want to reboot the system each time you change cards.] -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 50235
Welcome to the wonderful world of marketing. Those in the
know often refer to these as 'marketing gates' for good
reason. In the ASIC world, a design size can be measured in
'gates' because that is the atomic unit there. With FPGAs,
the atomic unit is LUTs or more precisely LUT+FF pairs.
Marketing attempts to assign a gate count to these resources
is fraught with peril. How many gates makes up a 4 input
LUT? Depends on how it is used. If it incorporates just a
2 input NAND function, then it is just one gate. If it is a
4 input parity function, it is many more equivalent gates,
and even more if it is used as memory or as a shift
register... The USB's gate count could be in ASIC gates, or
could have been gleened from a PAR report's reported
'equivalent gates'.
A considerably more accurate measure of FPGA real estate
used is in a LUT count, or in the case of the Xilinx parts a
'slice count' which is a tally of the elemental units
germane to FPGAs. It makes no more sense measuring FPGA
design size in gates than it does measuring distance in
Liters. There is no direct conversion between the two
measures.
Steve wrote:
> I have a pre-made USB interface design which claims to use
> 16K-20K gates, and I'm looking for an appropriate FPGA for
> implementing this. It seems that most FPGA's (I've checked
> several of the Virtex and Spartan series) report "system
> gates", and sometimes include "logic gates" as well.
>
> What is the difference between these two? For example, the
> SpartanXL XCS50XL says it has 13K-40K system gates and 20K
> max. logic gates. Where do the rest of the system gates
> go? Are they all for RAM?
>
> Also, what would the USB's gate count be referring to..
> system gates or logic gates?
>
> Thanks!
> -Steve
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin
Franklin, 1759
Article: 50236Hal Murray wrote: >>I am going to use a PCI Board that will execute the loops of a software. >> I need to measure the power that will be expended in the pci board >>while the loops are being executed. I am using Xilinx PowerX to >>estimate the power but I need to experimentally validate the estimates. >>Also I want to see if we really can gain in using the PCI board as a >>coprocessor for executing the loops in hardware. Incidentally the boards >>that I have are from Alpha Data and Annapolis. So inserting a probe for >>a DVM is also pretty tricky .. > > > You might get some information by measuring the temperature of the chip. > > If you are willing to sacrifice a mother board, you could (maybe?) yank > the pins from the connectors on the power rail you want to measure. > Then you could add it back on through a meter. > > I think some PCI extender cards may have a way to measure current > or let you provide current for the board under test separately. > [Seems like a reasonable idea if you want to test lots of boards > and don't want to reboot the system each time you change cards.] > The code that I am trying to execute has a host program that runs on the computer and the compute intensive parts run on the FPGA. So the data has to be brought in from the memory (computer) and we try to measure the latencies and the i/o bottleneck ... now we decided power must be also a factor in this .. You see, we are not using the FPGA like an ASIC .. we want to get the FPGA to act as a reconfigurable coprocessor .. We are trying to validate our CoDesign scenario and are trying to quantify the power savings that we can hope to achieve. Do u know of any place where I can get an extender card so that can measure the current.Article: 50237
>Do u know of any place where I can get an extender card so that can
>measure the current.
Try Google. (The Universal answer for questions like that.)
I fed it "PCI extender"
The first hit is http://www.sycard.com/pciext.html
As an extender card the PCIextend
extends a PCI card 2.5" above the host computer. Jumpers
blocks on Vcc allow for current consumption or voltage
margin testing. Multiple power status LEDs indicate 3.3V,
5V, +12V and -12V.
There are many more hits to check.
--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.
Article: 50238Ray Andraka wrote > It makes no more sense measuring FPGA > design size in gates than it does measuring distance in > Liters. Or even Litres. What has happened to the language of Shakespeare :-)Article: 50239
.vec files can be read in by Quartus II. Use the File Open dialog box, and select Files of Type to be Waveform/Vector Files (.vwf, .vec, .tbl). If there is a specific problem with your vec file, please contact the Altera support at mysupport.altera.com. The following is an excerpt from the online help. "The Quartus® II Simulator can use MAX+PLUS II VEC files as stimulus for timing simulation. However, you cannot create VEC Files with the Quartus II Waveform Editor. Instead, you can create Vector Waveform Files (.vwf) for use with the Quartus II Simulator. VEC Files are only supported for backwards compatibility with MAX+PLUS II." - Subroto Datta "siriuswmx" <wangmanxi@yahoo.com> wrote in message news:4528663b.0212042020.1f5d29f4@posting.google.com... > Hi, everybody, > I met with a problem when i simulated my program in QUARTUS2.0. > I want to the simulator driven by the stimulus of a text file, for > example the *.vec file. I can open *.vec in MAXPLUS2 ,but fail in > QUARTUS. Although I tried to change the *.vec to *.tbl, it can't be > opened still. > Can Quartus open *.vec ? and how to open the stimulus from a text > file in QUARTUS? thank you! > Best regards! > > siriuswmxArticle: 50241
"Steve Casselman" <sc@vcc.com> wrote in message news:eLOH9.3209$ti7.77237430@newssvr13.news.prodigy.com... > I think aoubt it this way: A regular "logic gate" is usually thought of as 2 > input nand gate. Since you can make anything out of nand gates anything you > can make can be expressed in the number of nand gates it would take to build > the design. The total "System Gates" number is the maximum "potential > gates" on the chip. By that I mean if had a design used every feature then > you would need that many nand gates to build the design. The one that I usually use says that the number of gates is the number of transistors used divided by the number in a two input NAND gate. That is four in CMOS. This rules makes sense for ASIC design but not much sense for FPGA design. As to the original question, yes, they count built in RAM in the gate count, as it would under the transistors definition. Though you wouldn't really build RAM out of NAND gates. -- glenArticle: 50242
Chen Wei Tseng <chenwei.tseng@xilinx.com> wrote in message news:<3DEF8C58.E458668E@xilinx.com>... > Muthu, > > Usually, when you create a RPM, you would want to RLOC everything. This warning message tells you > that you still have components (LUTS/DFF/ etc...) not placed when you are trying to create the RPM. > This will results in the unplaced logic not bound to the RPM shape. > > Possible cause of this. > > 1. Using replace all with placement - And you have DFF packed into the IOB. Since Floorplanner > doesn't show components in the IOB, you'll have to manually place the DFF components or leave them > out of the RPM shape. > > 2. When you're manually placing the components, you didn't place all the components other than the > IOBs. > > Regards, Wei Hi wei, Yeah i agree, some components are not place in the Floor-planner. Thats why this warning came. But i am sure that it is not due to IOB FFs. Becasue, My input .edf file is generted with out inserting the IOB while synthesis. Best regards, MuthuArticle: 50243
Hi, can anybody explain exactly *when* setting the DESKEW_ADJUST = SOURCE_SYNCHRONOUS for a DCM has any effect on a DCM, exactly *how* it affects the DCM and if Trace should report any different timing than if the default mode was used (because it doesn't for me). I have already looked at Answer Records # 14743 and # 15350 and searched the Xilinx documentation but I can't find the info I need. Can someone also explain how the default mode (SYSTEM_SYNCHRONOUS) works, especially how the "secret" compensation offset between CLKIN and CLKFB is determined in different situations? In Answer Record # 13024 the Tdcmclkinoffset is described in the follwing way: Tdcmclkinoffset = A compensation offset fixed to account for other circuit anomalies.* * This number is dependent upon circuit conditions and low-level speed file parameters. How *exactly* is it calculated? Best Regards, Magnus JacobssonArticle: 50244
glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: : "Steve Casselman" <sc@vcc.com> wrote in message : news:eLOH9.3209$ti7.77237430@newssvr13.news.prodigy.com... :> I think aoubt it this way: A regular "logic gate" is usually thought of as : 2 :> input nand gate. Since you can make anything out of nand gates anything : you :> can make can be expressed in the number of nand gates it would take to : build :> the design. The total "System Gates" number is the maximum "potential :> gates" on the chip. By that I mean if had a design used every feature then :> you would need that many nand gates to build the design. : The one that I usually use says that the number of gates is the number of : transistors used divided by the number in a two input NAND gate. : That is four in CMOS. This rules makes sense for ASIC design but not : much sense for FPGA design. : As to the original question, yes, they count built in RAM in the gate : count, as it would under the transistors definition. Though you wouldn't : really build RAM out of NAND gates. Lies, damned lies and FPGA Gate Count :-) -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 50245
Cisa <yxjiang2002@sina.com> wrote: : After I successfully synthesize and <BR> : translate a design,continue to map, ISE give me the following error message: FATAL_ERROR:MapLib:basmmngm.c:1935:1.127 - Could not find a physical signal for <BR> : this pin Process will terminate. To resolve this error, please consult the <BR> : Answers Database and other online resources at <a href="http://support.xilinx.com">http://support.xilinx.com</a>. If <BR> : you need further assistance, please open a Webcase by clicking on the <BR> : "WebCase" link at <a href="http://support.xilinx.com">http://support.xilinx.com</a> <BR> : WARNING:Portability:111 - Message file "MapHelpers.msg" wasn't found. <p>What causes this fatal error?Please help me. <BR> : Thanks. If you don't post HTML garbage, chances are better that somebody responses... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 50246
Muthu, The warning should not prevent you from creating the NCF file. Just make sure you have all the slice logic comp placed and you'll be fine. If you have all slice logic comps placed and still sees the warning; then it's likely a bug that you may want to report to the hotline. As for IOB DFFs, if you don't specify it, MAP by ISE default should try to pack them into IOBs. Thanks, Wei Muthu wrote: > Chen Wei Tseng <chenwei.tseng@xilinx.com> wrote in message news:<3DEF8C58.E458668E@xilinx.com>... > > Muthu, > > > > Usually, when you create a RPM, you would want to RLOC everything. This warning message tells you > > that you still have components (LUTS/DFF/ etc...) not placed when you are trying to create the RPM. > > This will results in the unplaced logic not bound to the RPM shape. > > > > Possible cause of this. > > > > 1. Using replace all with placement - And you have DFF packed into the IOB. Since Floorplanner > > doesn't show components in the IOB, you'll have to manually place the DFF components or leave them > > out of the RPM shape. > > > > 2. When you're manually placing the components, you didn't place all the components other than the > > IOBs. > > > > Regards, Wei > > Hi wei, > > Yeah i agree, some components are not place in the Floor-planner. > Thats why this warning came. > > But i am sure that it is not due to IOB FFs. Becasue, My input .edf > file is generted with out inserting the IOB while synthesis. > > Best regards, > MuthuArticle: 50247
Hi, I trying to understand programming fpga`s. Have this book ( The practical Xilinx designer lab book written by David Van den Bout) Although I`ve got the latest version of Xilinx`s software (WebPack) I want the older version which is used with the book (Xilinx Foundation 1.5 Series Software) so I can `catch up` with the book Anybody knows where to get this older version? Tanks. Aroen. run@arun.demon.nlArticle: 50248
Magnus, For system synchronous, we need to compensate for the worst possible PVT internal delays to guarantee timing. Thus we insert a delay that is settable by the bitstream, and was characterized for each device over all process corners. This does throw away some timing (obviously) and adds more variability in and of itself, as the delay is also affected by PVT, and adding it makes things less accurate. Hence the reason why system synchronous is harder to make work at higher frequencies (generally true for everyone....not just us). For source synchronous, we can set this delay to zero (or nearly so) as the DCM has the phase shift feature, which allows for placing the sample clock in the center of the data cell. In such a setup, the "data sample window" or variation for guaranteed proper sampling of the data by the clock is reduced, and higher clock speeds are supported with an even larger "eye margin." Source synchronous is the solution to trying to run busses at these higher clock rates (also generally true for everyone). Austin Magnus Jacobsson wrote: > Hi, > > can anybody explain exactly *when* setting the DESKEW_ADJUST = > SOURCE_SYNCHRONOUS for a DCM has any effect on a DCM, exactly *how* it affects > the DCM and if Trace should report any different timing than if the default mode > was used (because it doesn't for me). > > I have already looked at Answer Records # 14743 and # 15350 and searched the > Xilinx documentation but I can't find the info I need. > > Can someone also explain how the default mode (SYSTEM_SYNCHRONOUS) works, > especially how the "secret" compensation offset between CLKIN and CLKFB is > determined in different situations? In Answer Record # 13024 the Tdcmclkinoffset > is described in the follwing way: > > Tdcmclkinoffset = A compensation offset fixed to account for other circuit > anomalies.* > > * This number is dependent upon circuit conditions and low-level speed file > parameters. > > How *exactly* is it calculated? > > Best Regards, > Magnus JacobssonArticle: 50249
This thread brings to mind an issue that's been bugging me recently. Could anyone tell me why you can't 'freeze' routing (or is there a way? I'm using ISE 5.1), or reserve certain routing resources? It would seem to me to be a useful addition, am I missing something? Pierre-Olivier On Fri, 6 Dec 2002, Chen Wei Tseng wrote: > Muthu, > > The warning should not prevent you from creating the NCF file. Just make sure you have all the slice > logic comp placed and you'll be fine. If you have all slice logic comps placed and still sees the > warning; then it's likely a bug that you may want to report to the hotline. > > As for IOB DFFs, if you don't specify it, MAP by ISE default should try to pack them into IOBs. > > Thanks, Wei > > Muthu wrote: > > > Chen Wei Tseng <chenwei.tseng@xilinx.com> wrote in message news:<3DEF8C58.E458668E@xilinx.com>... > > > Muthu, > > > > > > Usually, when you create a RPM, you would want to RLOC everything. This warning message tells you > > > that you still have components (LUTS/DFF/ etc...) not placed when you are trying to create the RPM. > > > This will results in the unplaced logic not bound to the RPM shape. > > > > > > Possible cause of this. > > > > > > 1. Using replace all with placement - And you have DFF packed into the IOB. Since Floorplanner > > > doesn't show components in the IOB, you'll have to manually place the DFF components or leave them > > > out of the RPM shape. > > > > > > 2. When you're manually placing the components, you didn't place all the components other than the > > > IOBs. > > > > > > Regards, Wei > > > > Hi wei, > > > > Yeah i agree, some components are not place in the Floor-planner. > > Thats why this warning came. > > > > But i am sure that it is not due to IOB FFs. Becasue, My input .edf > > file is generted with out inserting the IOB while synthesis. > > > > Best regards, > > Muthu > >
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