Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
I'm not familiar with the numbers in the area of jitter and clock distribution. I'm assuming anything interested in serious low jitter would be using differential signaling. How much jitter comes out of a good oscillator package? I think of crystals as being very high Q and expect them to be good at jitter. Are any brands/models significantly better/worse than others? How much does a clock buffer (non PLL) add? How much jitter comes out of a PLL type clock buffer? Are there any parts that are significantly better than others? How careful do I have to be about PCB layout and power decoupling? Or how much can I gain if I am crazy or lose if I'm not careful? I'm just fishing for rough numbers. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 50276
A bit offtopic: if I have a clock coming into Spartan IIE clock network, and I need to feed it to an IO pin, doing something like: io_pin<=clock_pin; causes Mapper error saying I am trying to connect clock_pin and clock_pin_ibuf. What's the correct way? Thanks! Hal Murray wrote: >>I have a 120MHz clock being fed into a global clock pin and would like to >>be able to send this clock to an ADC on my board using the DLL for more >>clocking options. > > I think you want to consider that carefully. > > DLLs add jitter. That's generally bad when ADCs are involved. > > There was a lot of discussion about this here a while ago. > Google-groups might be interesting. >Article: 50277
Chen Wei Tseng <chenwei.tseng@xilinx.com> wrote in message news:<3DF0C105.7B384597@xilinx.com>... > Muthu, > > The warning should not prevent you from creating the NCF file. Just make sure you have all the slice > logic comp placed and you'll be fine. If you have all slice logic comps placed and still sees the > warning; then it's likely a bug that you may want to report to the hotline. > > As for IOB DFFs, if you don't specify it, MAP by ISE default should try to pack them into IOBs. > > Thanks, Wei Hi wei, Here i tried to generate RLOC for a top module which has Module's with 3 levels of Hierarchy. The notable thing here is, some of the modules with in the hierarchy is generted from the coregen. So, that will have the RLOC contrains. How that constrains will be treated. will that be overwritten or the ORIGIN alone gets vary. And My submodule's Having the instantiation of BRAMs too. So, after generating the .ucf from the floor planner. I just tried to Re-Run the same with the .ncf contrain. But There i am getting an translation error that, some of the instances couldn't find. I didn't change any line of .ncf generated by the Floor planner.? What could be the reason.? Now i am trying to do RLOC for the module's which is not having BRAMS...... whats going wrong ???? Guide me in this... Thanks in advance. Best regards, MuthuArticle: 50278
Hi there, Can anyone please explain to me what's the problem with this warning? Will it cause any harms later? I've encountered this warnings with exclamation marks ! Can anyone help me fix it? First warnings : Warning: The net '/Booth3/neg2' is a feed through net. (FPGA-CHECK-9) Warning: The net '/Booth3/neg1' is a feed through net. (FPGA-CHECK-9) Warning: The net '/Booth3/neg0' is a feed through net. (FPGA-CHECK-9) Warning: The net '/Booth3/neg4' is a feed through net. (FPGA-CHECK-9) Warning: The net '/Booth3/neg7' is a feed through net. (FPGA-CHECK-9) Warning: The net '/Booth3/neg3' is a feed through net. (FPGA-CHECK-9) Warning: The net '/Booth3/neg6' is a feed through net. (FPGA-CHECK-9) Warning: The net '/Booth3/neg5' is a feed through net. (FPGA-CHECK-9) Second warning : Warning: Variable 'mul3x' is being read in routine pp_0 line 24 in file 'F:/Floating Point Unit/pp_0.vhd', but is not in the process sensitivity list of the block which begins there. (HDL-179) thanks in advance.Article: 50279
Tim wrote: > Ray Andraka wrote > > > It makes no more sense measuring FPGA > > design size in gates than it does measuring distance in > > Liters. > > Or even Litres. What has happened to the language of > Shakespeare :-) Or even the language of Racine since Lit<er | re>s were invented by those revolutionary French in between spells at the guillotine. `He Jaque, je vien de decapite 2000 litres d'Aristocrats' `Bien Georges mais je commande 3000 litres par jour, faites attention ou tu sera le prochaine!'Article: 50280
"Dimitris Theodoropoulos" <theodor@mhl.tuc.gr> wrote in message news:<aso7oa$1ulh$1@ulysses.noc.ntua.gr>... > Hi there! > > I am trying to find a memory module for my design, which I will download > in a Virtex. I use Xilinx ISE 4.2i and I tried the Xilinx parameterizable > RAM for Virtex from their IPcenter, but when I tried the Post Place & Route > Simulation, in many cases, the output was undefined. Does anyone know where > I can find vhdl code for memory modules that actually works!!? > > Thank you! > Dimitris Dimitri, please refer to Xilinx application notes and their XCell Online Journal. You can easily find some examples on several sites if you follow the VHDL FAQ which is issued at comp.lang.vhdl. Entajei? Uncle "The G.B. Man" NoahArticle: 50281
A statement like: output <= input; will generate a 'feed through net warning'. All it's telling you is that there's no "logic". Ignore it. The 2nd warning is telling you to go fix your sensitivity lists. (mul3x is being used on the RHS of an assignment, but is not in the sensivity list for the process) Go fix your sensitivity lists. SH7 On Sat, 7 Dec 2002 17:04:03 +0800, "Kevin Yeoh" <kevyeoh@tm.net.my> wrote: >Hi there, > >Can anyone please explain to me what's the problem with this warning? Will >it cause any harms later? > >I've encountered this warnings with exclamation marks ! Can anyone help me >fix it? > >First warnings : > >Warning: The net '/Booth3/neg2' is a feed through net. (FPGA-CHECK-9) >Warning: The net '/Booth3/neg1' is a feed through net. (FPGA-CHECK-9) >Warning: The net '/Booth3/neg0' is a feed through net. (FPGA-CHECK-9) >Warning: The net '/Booth3/neg4' is a feed through net. (FPGA-CHECK-9) >Warning: The net '/Booth3/neg7' is a feed through net. (FPGA-CHECK-9) >Warning: The net '/Booth3/neg3' is a feed through net. (FPGA-CHECK-9) >Warning: The net '/Booth3/neg6' is a feed through net. (FPGA-CHECK-9) >Warning: The net '/Booth3/neg5' is a feed through net. (FPGA-CHECK-9) > > >Second warning : > >Warning: Variable 'mul3x' is being read > in routine pp_0 line 24 in file 'F:/Floating Point Unit/pp_0.vhd', > but is not in the process sensitivity list of the block which begins > there. (HDL-179) > > >thanks in advance. >Article: 50284
"Thomas Rudloff" <thomas_rudloff@gmx.net> wrote in message news:3DF15428.F1FC6403@gmx.net... > It looks OK. The uA are static current without load. > So real power depends on flip flops toggleing and of course > output driving. Maybe your 6.7mA are just the current required to drive > your loaded outputs high. > > Regards > Thomas > > > John wrote: > > > I'm trying to measure the power consumption of a Xilinx CoolRunner > > CPLD. It doesn't need to be extremely accurate. I've put a 1 ohm > > resistor between my +ve power supply and my board's VCC, and measured > > the voltage across that, which gave me 6.7 mV. This would imply that > > 6.7 mA of current is being drawn, although the CoolRunner should draw > > current in the range of uA. Is there anything wrong with this simple > > setup? > > > > Thanks, > > John Place a RC low-pass filter accross the resistor and feed this signal into the meter. The filter will give you the average reading - if your meter doesn't allready do so Cheers Klaus >Article: 50285
Hello, I know it's technology-dependent feature, should I bother about it targeting for FPGA? Actually I wish to describe structure of binary decoder on the AND2 gate basis.Article: 50286
Kevin,
Issue 1:
The first warning says a signal comes in and goes out
of a block without any logic.
SH7 is right for an FPGA, this is usually not a problem.
Most FPGA place and route tools flatten the netlist and
then route it.
For an ASIC, this can be a fatal problem for some of the
place and route tools. It would be really ugly to fix
by manipulating the netlist. Much easier to fix in the
source code. Don't bring a signal into a block that is
not used in that block. For arrays, only bring in the
part of the array into a block that is needed.
So if you ever plan on reusing the code for an ASIC,
you will want to fix it.
Issue 2:
Most of the time this means you must fix your sensitivity
list. However, watch out as some tools have quirks
with processes that create registers. I have seen a
similar warning with the following process:
MyRegProc : process
begin
wait until Clk = '1' ;
MyReg <= mul3x ;
end process ;
Here the process cannot have a sensitivity list.
Hence, if this is where your warning comes from,
you might try the following register coding style
and see if your issue goes away:
MyRegProc : process (Clk)
begin
if rising_edge(Clk) then
MyReg <= mul3x ;
end process ;
Cheers,
Jim Lewis
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Kevin Yeoh wrote:
> Hi there,
>
> Can anyone please explain to me what's the problem with this warning? Will
> it cause any harms later?
>
> I've encountered this warnings with exclamation marks ! Can anyone help me
> fix it?
>
> First warnings :
>
> Warning: The net '/Booth3/neg2' is a feed through net. (FPGA-CHECK-9)
> Warning: The net '/Booth3/neg1' is a feed through net. (FPGA-CHECK-9)
> Warning: The net '/Booth3/neg0' is a feed through net. (FPGA-CHECK-9)
> Warning: The net '/Booth3/neg4' is a feed through net. (FPGA-CHECK-9)
> Warning: The net '/Booth3/neg7' is a feed through net. (FPGA-CHECK-9)
> Warning: The net '/Booth3/neg3' is a feed through net. (FPGA-CHECK-9)
> Warning: The net '/Booth3/neg6' is a feed through net. (FPGA-CHECK-9)
> Warning: The net '/Booth3/neg5' is a feed through net. (FPGA-CHECK-9)
>
>
> Second warning :
>
> Warning: Variable 'mul3x' is being read
> in routine pp_0 line 24 in file 'F:/Floating Point Unit/pp_0.vhd',
> but is not in the process sensitivity list of the block which begins
> there. (HDL-179)
>
>
> thanks in advance.
>
>
Article: 50287
valentin tihomirov wrote:
> Hello,
> I know it's technology-dependent feature, should I bother about it targeting
> for FPGA? Actually I wish to describe structure of binary decoder on the
> AND2 gate basis.
AND gates could decode all ones, but nothing else.
For fpga design, there aren't really any structures
as simple as a AND2 or NAND2 on the chip, so you
should just use the logic description that's easiest
for you and your tools.
-- Mike Treseler
Article: 50288
Hi,
I am having some questions on Virtex 2.5 V architecture now.
If you look at the Xilinx databook on pg5 (ds003-2.pdf), what's the
function of CE and REV on the Flip-flop block?
When Xilinx implements the LUT in the CLB,it needs a 4-16 decoder
inside.Is there a good decoder design available to the public?
Amy
Article: 50289Hi, "Ray Andraka" <ray@andraka.com> wrote in message news:3DF149F3.B9BCE307@andraka.com... > No, don't do it. You'll get lousy noise performance because of the jitter > introduced by the DLL (clock jitter at the ADC creates a sampling jitter, which > in turn translates to noise if your signal input changes from sample to > sample). Instead, run the clock directly to the ADC and to the FPGA. At 120 > MHz you may have problems with driving both the ADC and the FPGA. Low skew > buffers can sometimes help, but you need to watch the jitter specs on those too > because many are PLL based. If you select an ADC with a Data Ready output that > transitions (DDR style) on each valid sample, you can use that as the clock into > the FPGA assuming your ADC is always running, and that should drive the DLL in > the FPGA via a clock pin. I was unclear before about the required ADC clock. It actually is only 40MHz, there is also a DAC on the board and it is clocked directly from the 120Mhz crystal oscillator. We are planning to generate the 40MHz signal for the ADC clock inside the Spartan IIE FPGA. I know that this 40MHz clock will be noisier than if we used something like an external pll, but will it be acceptable for a 10bit 40MSPS ADC? cheers, Jamie MorkenArticle: 50290
In article <Pine.SOL.3.96.1021207160333.7392A-100000@vcmr-86.server.rpi.edu>, Jingjing (Amy) Hu <huj5@rpi.edu> wrote: >Hi, > I am having some questions on Virtex 2.5 V architecture now. >If you look at the Xilinx databook on pg5 (ds003-2.pdf), what's the >function of CE and REV on the Flip-flop block? CE is clock enable. REV, do you mean SR (set reset)? > When Xilinx implements the LUT in the CLB,it needs a 4-16 decoder >inside.Is there a good decoder design available to the public? Its a 16-1 mux, nothing really special. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 50291
Hi Dimitris - The Xilinx memory models have typically performed set-up and hold checks for gate level simulations. So using these models in RTL simulations will introduce timing violations since all inputs are changing within 0 ns (at the clock edge) of the block ram clock input. The trick is to add delay to the signals which are input to the block ram model in the RTL code directly to move the transitions outside the setup/hold time window checking. -- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. 303-926-0068 email : jretta@rtc-inc.com web : www.rtc-inc.com "Dimitris Theodoropoulos" <theodor@mhl.tuc.gr> wrote in message news:aso7oa$1ulh$1@ulysses.noc.ntua.gr... > Hi there! > > I am trying to find a memory module for my design, which I will download > in a Virtex. I use Xilinx ISE 4.2i and I tried the Xilinx parameterizable > RAM for Virtex from their IPcenter, but when I tried the Post Place & Route > Simulation, in many cases, the output was undefined. Does anyone know where > I can find vhdl code for memory modules that actually works!!? > > Thank you! > Dimitris > >Article: 50292
Didn't know that. Thanks. SH7 On Sat, 07 Dec 2002 11:37:29 -0800, Jim Lewis <jim@SynthWorks.com> wrote: > >For an ASIC, this can be a fatal problem for some of the >place and route tools. > >So if you ever plan on reusing the code for an ASIC, >you will want to fix it. >Article: 50293
Hi, everyone,
Must i turn to symbol entry window to assign the pins?
thanks a lot!
Article: 50294
This is a multi-part message in MIME format.
------=_NextPart_000_000C_01C29E9D.2173DA90
Content-Type: text/plain;
charset="koi8-r"
Content-Transfer-Encoding: quoted-printable
Sorry, combining 2 questions into one was confusing.
consider the following decoder at RTL:
case(adr) is
when "00" =3D> y<=3D"0001"
when "01" =3D> y<=3D"0010"
when "10" =3D> y<=3D"0100"
when "11" =3D> y<=3D"1000"
end case;
Question 1: Will this code look like the following netlist at the gate =
level after synthesis?
A1
-------+----------------+
_|_ _|_
|INV| |BUF|
|___| |___|
| |
+-------+ +-------|
A0 | | | |
----+--+-----+-+-----+-+-----+ |
|__|_ _|_|_ _|_|_ _|_|_
|AND2b| |AND2 | |AND2b| |AND2 |
|_____| |_____| |_____| |_____|
| | | |
0 1 2 3
Here, AND2b - is and element with the first input inverted.
Question 2) As you see, the decoder sonsists only of and2 elements. Thus =
it must have a couterpart consisting of nand2 elements.
Article: 50295
For the Unisims, Xilinx put in timing parameters (why they felt they needed
timing info in a functional sim library is anyone's guess). You need to set
the Timingcheckson attribute to false on clocked elements to work with RTL
code.
John Retta wrote:
> Hi Dimitris -
> The Xilinx memory models have typically performed set-up and hold checks
> for gate level simulations. So using these models in RTL simulations will
> introduce
> timing violations since all inputs are changing within 0 ns (at the clock
> edge) of
> the block ram clock input. The trick is to add delay to the signals which
> are input
> to the block ram model in the RTL code directly to move the transitions
> outside
> the setup/hold time window checking.
>
> --
> Regards,
> John Retta
> Owner and Designer
> Retta Technical Consulting Inc.
> 303-926-0068
>
> email : jretta@rtc-inc.com
> web : www.rtc-inc.com
>
> "Dimitris Theodoropoulos" <theodor@mhl.tuc.gr> wrote in message
> news:aso7oa$1ulh$1@ulysses.noc.ntua.gr...
> > Hi there!
> >
> > I am trying to find a memory module for my design, which I will
> download
> > in a Virtex. I use Xilinx ISE 4.2i and I tried the Xilinx parameterizable
> > RAM for Virtex from their IPcenter, but when I tried the Post Place &
> Route
> > Simulation, in many cases, the output was undefined. Does anyone know
> where
> > I can find vhdl code for memory modules that actually works!!?
> >
> > Thank you!
> > Dimitris
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50296
"valentin tihomirov" <valentin@abelectron.com> schrieb im Newsbeitrag
news:3df2f63b$1_1@news.estpak.ee...
Sorry, combining 2 questions into one was confusing.
consider the following decoder at RTL:
case(adr) is
when "00" => y<="0001"
when "01" => y<="0010"
when "10" => y<="0100"
when "11" => y<="1000"
end case;
Question 1: Will this code look like the following netlist at the gate level
after synthesis?
A1
-------+----------------+
_|_ _|_
|INV| |BUF|
|___| |___|
| |
+-------+ +-------|
A0 | | | |
----+--+-----+-+-----+-+-----+ |
|__|_ _|_|_ _|_|_ _|_|_
|AND2b| |AND2 | |AND2b| |AND2 |
|_____| |_____| |_____| |_____|
| | | |
0 1 2 3
Here, AND2b - is and element with the first input inverted.
NO, since the finest decoder emelments in a FPGA are not AND, NAND etc, its
a LUT (Look Up Table), which is (in most cases) a 16x1 bit ROM with free
programmable content. The the decoder above would use one LUT per output,
resulting in just one level of logic (= very fast). You can decode any
arbitrary 4 input function in a LUT.
--
MfG
Falk
Article: 50297"Jamie Morken" <jmorken@shaw.ca> schrieb im Newsbeitrag news:oGuI9.173443$ka.4005430@news1.calgary.shaw.ca... > I know that this 40MHz clock will be noisier than if we used something like > an external pll, but > will it be acceptable for a 10bit 40MSPS ADC? Hmm, a rough estimate. 40 Msps => 25 ns 10 bit resolution => 1/1024 => 25ns / 1024 => ~25 ps I guess the jitter added in the FPGA is higher (100ps ++) -- MfG FalkArticle: 50298
"siriuswmx" <wangmanxi@yahoo.com> schrieb im Newsbeitrag news:4528663b.0212071721.41490a4e@posting.google.com... > Hi, everyone, > Must i turn to symbol entry window to assign the pins? > thanks a lot! This dependes on you software you use. In general, the pins are not assigned in a VHDL file, rather than in a software specific file. For Xilinx Webpack its the UCF (User Constraint File). -- MfG FalkArticle: 50299
Hi. I would like to hear about Xilinx experience of the following flag: SET XIL_PAR_SKIPAUTOCLOCKPLACEMENT=1 (PCs) setenv XIL_PAR_SKIPAUTOCLOCKPLACEMENT 1 (Workstations) This flag can be used when Placer rejects valid BUFGMUX configuration. As sepcified by Record Number: 11384 in Xilinx answer database. ThankX, NAHUM.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z