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Hello, general question here, sorry if it is off-topic. what makes an implementation be elligible for a patent status? i expect Novelty first. But if someone takes an architecture and optimise it according to a special FPGA (eg. Virtex), so he takes the maximum of the chip features to implement it optimally. can he submit this work for a patent?? what's differ a patent from a copyrighted work? sideline comment, Ray, do you have patents ? could you list some of them? [i expect all of your posts in this newsgroup should be patented ;-), well no just Ray, Falk also... ] Merry christams to all of you.Article: 50551
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<GdPJ9.6090$HE7.166025521@newssvr13.news.prodigy.com>... > As a follow-up to my post, in looking at Floorplanner it seems that it might > be sensible to build large input output busses by straddling two banks in > each corner of a device. This would allow shortest path from every related > I/O pin to the logic resources in that corner. Is this true? Probably so. But if you clock stuff on/off chip in the IOBs, chances are you don't have to worry too much about this anyway. > What are the issues regarding clock distribution? At your speeds (155 MHz), clock distribution should not be a problem assuming you use the global clock nets. To answer the concerns on your previous posting, assigning a pinout is indeed a big chore, but thanks to the Virtex family having good routing resources, it is rarely fatal if you make suboptimal choices. The only thing that you didn't mention taking into account is the type, direction, and drive of the I/O's. Even if they are all the same type, breaking them up across two or more banks should provide slightly better margin all around because you are distribuating the I/O across a larger number of power and ground pins. Have fun, MarcArticle: 50552
Magnus, What are you trying to accomplish? I don't believe you want to use the DESKEW_ADJUST attribute. This attribute is used if you are doing a source-synchronous designs as described in different Xilinx Source-Sync application notes. Your clocking scheme does not match what Xilinx suggests. If you are trying to line up a clock with the I/O, I would used the FIXED_PHASE_SHIFT attribute to adjust the phase of the clock. The DESKEW_ADJUST attribute does affect the Tdcmino number. If you have properly applied the attribute, it is automatically taken into account. I believe this will only affect Tdcmino if there is internal feedback. The FIXED_PHASE_SHIFT will show up as Clock Arrival time in the details of the OFFSET constraint. The current software does not take clock phase into account in the Setup/Hold tables at the bottom of the timing report. It will in 5.2i. Kate Magnus Jacobsson wrote: > Hi Austin, > > thanks for your answer, but you didn't really answer my questions. In my design > I have 6 DCMs using and generating internal and external clocks in different > combinations. One of the DCMs drives three other DCM:s. I think one or two of > them should be system synchronous and the rest should be source synchronous. But > I'm not sure because I can't find any description of *exactly* how the deskewing > works. > > For instance, the compensation delay you mention, is it *always* inserted in > system synchronous mode or only if the DCM is used in a certain configuration > such as CLKIN comes from an external clock, CLKFB comes from an external clock > or it drives an external clock? > > What about chained DCMs where the first generates an internal clock driving > three other DCMs by multiplying (2X) an external clock (internal feedback, no > deskew of extrenal clock) and the three following DCMs are replicating this > clock with different phase shifts (NONE, FIXED with external feedback and > VARIABLE controlled by logic sampling a receive clock? Below is a simplified > scematic of the system (most BUFGs have been left out): > > +-------------+ +------------+ > | _________ | | ________ | > +-| FB 0|-+ +-|FB 0|-+------> int_clk2x_0 > ext_clk -|>----+-----| IN 2x|---+-----|IN 90|--------> int_clk2x_90 > BUFG | | | | | | > v | (1) | | | (2) | > int_clk | | | |SHIFT | > | | | |NONE | > --------- | -------- > | > +---> int_clk2x > | ________ > ext_clk2x_fb -------------------< | >---|FB 0|--------> ext_clk2x > +-----|IN | > | | | > | | (3) | > | |SHIFT | > | |FIXED | > | -------- > | > | > | +------------+ > | | ________ | > | +-|FB 0|-+------> int_clk2x_vs_0 > +-----|IN 90|--------> int_clk2x_vs90 > | | > ext_rec_clk--(ctrl_logic)---------------|PS* (4) | > |SHIFT | > |VARIABLE| > -------- > How should DESKEW_ADJUST for these be set for DCM 1, 2, 3 and 4? > > Is there any way to see in the timing analysis or somewhere else how these > compensation offsets affects the DCM? > > Best Regards, > Magnus > > Austin Lesea wrote: > > > Magnus, > > > > For system synchronous, we need to compensate for the worst possible PVT internal > > delays to guarantee timing. Thus we insert a delay that is settable by the > > bitstream, and was characterized for each device over all process corners. > > > > This does throw away some timing (obviously) and adds more variability in and of > > itself, as the delay is also affected by PVT, and adding it makes things less > > accurate. > > > > Hence the reason why system synchronous is harder to make work at higher frequencies > > (generally true for everyone....not just us). > > > > For source synchronous, we can set this delay to zero (or nearly so) as the DCM has > > the phase shift feature, which allows for placing the sample clock in the center of > > the data cell. In such a setup, the "data sample window" or variation for > > guaranteed proper sampling of the data by the clock is reduced, and higher clock > > speeds are supported with an even larger "eye margin." > > > > Source synchronous is the solution to trying to run busses at these higher clock > > rates (also generally true for everyone). > > > > Austin > > > > > > Magnus Jacobsson wrote: > > > > > >>Hi, > >> > >>can anybody explain exactly *when* setting the DESKEW_ADJUST = > >>SOURCE_SYNCHRONOUS for a DCM has any effect on a DCM, exactly *how* it affects > >>the DCM and if Trace should report any different timing than if the default mode > >>was used (because it doesn't for me). > >> > >>I have already looked at Answer Records # 14743 and # 15350 and searched the > >>Xilinx documentation but I can't find the info I need. > >> > >>Can someone also explain how the default mode (SYSTEM_SYNCHRONOUS) works, > >>especially how the "secret" compensation offset between CLKIN and CLKFB is > >>determined in different situations? In Answer Record # 13024 the Tdcmclkinoffset > >>is described in the follwing way: > >> > >>Tdcmclkinoffset = A compensation offset fixed to account for other circuit > >>anomalies.* > >> > >>* This number is dependent upon circuit conditions and low-level speed file > >>parameters. > >> > >>How *exactly* is it calculated? > >> > >>Best Regards, > >>Magnus Jacobsson > >> > > > > -- > Magnus Jacobsson Net Insight AB > Phone: +46-8-685 0415 Box 42093, SE-126 14 Stockholm, Sweden > Fax: +46-8-685 0420 Visiting address: Västberga Allé 9 > Mobile: +46-70-269 1487 http://www.netinsight.netArticle: 50553
hristo <hristostev@yahoo.com> wrote: : Hello, : general question here, sorry if it is off-topic. : what makes an implementation be elligible for a patent status? A good lawyer in first place. : i expect Novelty first. But if someone takes an architecture and : optimise it according to a special FPGA (eg. Virtex), so he takes the : maximum of the chip features to implement it optimally. can he submit : this work for a patent?? He can submit it and, at least with a good lawyer, will get it granted. Others may however claim "former art" or other objections later. : what's differ a patent from a copyrighted work? A patent denies you to have the same idea as somebody other had and got a patent for this idea. With copyrighted work you may not use his implementation for the idea, but you may implement it your way. With now often the time to have the same idea being shorter than doing a patent search to find if somebody has has the same idea before and patented, things get strange. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 50554
Try this. Go into the FPGA editor and call up the device you use. Then make
a "blank" ncd file. Then take you design and do a bitgen
---- from Austin Lesea
bitgen {all options used for design1.bit} -g ActiveReconfig:Yes -r
design1.bit design2.ncd
This creates the difference bitfile from the two ncd files.
In this way you can see exactly what a partial bitstream size is for
reconfiguration.
--------
I think if you make sure there are columns that are empty you can save you
space. You may have to prepend some frames for initialization. The problem I
see is if you use all the I/O since I/O bits and logic/routing bits are in
the same atomic frames.
Steve
"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message
news:ata9bc$n5c$1@news.tu-darmstadt.de...
> Is it possible to use a smaller configuration device with Xilinx FPGA than
> forseen?
>
> I my case I have forseen a XC2S200 on the board and I have XC18V01 and
> XC2S200 on stock. The XC2S200 has about 1.3 million configuration bits,
but
> the xc18v01 can only hold one milion.
> The Spartan is only partial filled (with all block ram
> used):
>
> The mapper report tells:
>
> Number of Slices: 629 out of 2,352 26%
>
> PS: I found the bitgen compress option, but only about 50000 bits where
> saved. Any other option?
>
> Thanks
> --
> Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
>
> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 50555The MTBF depends on device type, clock rate, data rate, but also very much on the available slack time between the output of the synchronizing flip-flop ( which inevitably will go metastable) and the logic that it drives. At 80 MHz clock rate I assume you might be able to afford 2 extra ns of metastable delay. Now you can use the table in XAPP094. It is based on older technology, so the answer will be overly pessimistic (conservative = short MTBF). For an extra 2 ns with XC4005, the MTBF for 10 MHz/1 MHz is > 10 million years. Since you use an 8 times higher clock rate the MTBF would be 8 times shorter, but since you use only 8 kHz instead of 1 MHz, the MTBF would be 125 times longer. So you get an MTBF of 15 times 10 million years = 150 million years. Might be long enough... But if you allow for only one ns of slack, the MTBF will be less than a year ! Peter Alfke, Xilinx Applications Nagaraj wrote: > Hi, > I have an asynchronous input to a synchronous system. I want to > calculate MTBF for a simple synchronizer(using only one synchonizing > FF). > Details are here below. > 1.Device Virtex-E, -8 speed grade, CLB flip-flops used > 2.Asynchronous input rate = 8KHz > 3.Clock frequency = 80MHz > > Could anybody in the group help me in finding out the MTBF? > > Regards, > NagarajArticle: 50556
I haven't bothered with patents. It is expensive, and they are only as
good as your ability to defend them, and then you first need to be able to
detect infringement. Being a small company, we don't have the resources.
hristo wrote:
> Hello,
> general question here, sorry if it is off-topic.
>
> what makes an implementation be elligible for a patent status?
>
> i expect Novelty first. But if someone takes an architecture and
> optimise it according to a special FPGA (eg. Virtex), so he takes the
> maximum of the chip features to implement it optimally. can he submit
> this work for a patent??
>
> what's differ a patent from a copyrighted work?
>
> sideline comment, Ray, do you have patents ? could you list some of
> them?
> [i expect all of your posts in this newsgroup should be patented ;-),
> well no just Ray, Falk also... ]
>
> Merry christams to all of you.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50557In article <3DF8D0BE.8A312B6@andraka.com>, Ray Andraka <ray@andraka.com> wrote: >I haven't bothered with patents. It is expensive, and they are only as >good as your ability to defend them, and then you first need to be able to >detect infringement. Being a small company, we don't have the resources. Patents are sometimes of use for a small company, but only if you can get a fairly broad patent on a rather new technology, which could otherwise be widely adopted if known and when you can patent pretty much teh only effective ways of doing it. But for many cases, a small company is better left doing things as "trade secret" or similar liscencing schemes. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 50558
saupal@indiatimes.com (Saurabh Pal) wrote in message news:<62ef09ee.0212120101.12969041@posting.google.com>... > > How can a better clock speed can be achieved? > Using Verilog and learning hardware.Article: 50559
Marc, Thanks for your reply. OK, I understand. Yes, I was planing on registering everything at the IOB's. The signal standard is LVCMOS33 for input busses and LVDCI_33 for output busses. The design will have one clock coming into a GCLKx pin in bank 5. This clock will get DCM'd into three new clocks: a de-skewe'd version and two synthesised frequencies. One such frequencies is the SDRAM clock. I was planning on delivering two copies of the clock to the memory array by using the DDR mechanism in the IOB's. As I understand it, this is an elegant and effective way to move a clock off chip along with the data it is clocking out and, at the same time, with the guarantee that the clock will be in time with this data. Do you know of any issues/problems with this methodology? Thanks again, -- Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "Marc Randolph" <mrand@my-deja.com> wrote in message news:15881dde.0212120837.479f715b@posting.google.com... > "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<GdPJ9.6090$HE7.166025521@newssvr13.news.prodigy.com>... > > As a follow-up to my post, in looking at Floorplanner it seems that it might > > be sensible to build large input output busses by straddling two banks in > > each corner of a device. This would allow shortest path from every related > > I/O pin to the logic resources in that corner. Is this true? > > Probably so. But if you clock stuff on/off chip in the IOBs, chances > are you don't have to worry too much about this anyway. > > > What are the issues regarding clock distribution? > > At your speeds (155 MHz), clock distribution should not be a problem > assuming you use the global clock nets. > > To answer the concerns on your previous posting, assigning a pinout is > indeed a big chore, but thanks to the Virtex family having good > routing resources, it is rarely fatal if you make suboptimal choices. > The only thing that you didn't mention taking into account is the > type, direction, and drive of the I/O's. Even if they are all the > same type, breaking them up across two or more banks should provide > slightly better margin all around because you are distribuating the > I/O across a larger number of power and ground pins. > > Have fun, > > MarcArticle: 50560
"Kip Ingram" <Kip@NOkipSPAMingram.rom> writes: >The general approach to rapidly computing logarithms (used by Henry Briggs >to generate the log tables he published in 1617) is to first reduce the >problem to the computation of the logarithm of a value very near 1. Then >use the power series > log (1+x) = x - x^2/2 + x^3/3 - x^4/4 ...... >to get a value of whatever accuracy you need. The "cleverness" is in how to >creatively move the argument near 1. I thought that in this case the guy was starting with a floating point number. In that case, the floating point exponent is *already* the integer part of the base-2 log of the number, while the floating point mantissa is *already* a number in the range [0.5, 1). So you're in a position to use the polynomial approximation to get the fractional part of the logarithm. Or use a lookup table, as someone suggested. But the hard part has already been done in the process of normalizing the floating-point number. DaveArticle: 50561
> what makes an implementation be eligible for a patent status? > > I expect Novelty first. But if someone takes an architecture and > optimize it according to a special FPGA (e.g.. Virtex), so he takes the > maximum of the chip features to implement it optimally. can he submit > this work for a patent?? There are different kinds of patents. The main patent types this field are "method" patents and "apparatus" patents. These are basically patents on physical "things" or "procedures." They are often related to manufacturing. The Inventor is supposed to know the state-of-the-art and be able to give the patent examiners everything they could possibly want or need. If you don't, and the patent is worth anything, then some lawyer will point out what ever it is you miss. I think the motivation behind patents was to publish, and there by preserve, trade secrets that often died with the inventor or just got lost. In return the inventor got a small amount time whereby others could be excluded from competing. > > what's differ a patent from a copyrighted work? > Copy Rights are on "Intellectual" things or things that can be "authored." These could be songs, art, bit patterns, micro code. Things that can be written books, software... Copy Rights last for the life of the author plus 75 years in the U.S. This means if somebody did a piece of music at the age of 5 and lived to be 105 their work could not become public for 175 years! That's about 10 times longer than patents. > sideline comment, Ray, do you have patents ? could you list some of > them? Go to www.uspto.gov You can search on any name. SteveArticle: 50562
"hristo" <hristostev@yahoo.com> wrote in message news:b0ab35d4.0212120822.46ba96e@posting.google.com... > Hello, > general question here, sorry if it is off-topic. > > what makes an implementation be elligible for a patent status? > > i expect Novelty first. But if someone takes an architecture and > optimise it according to a special FPGA (eg. Virtex), so he takes the > maximum of the chip features to implement it optimally. can he submit > this work for a patent?? Since the XOR operator has been patented, and upheld twice, I would say that it doesn't take much to be eligible. -- glenArticle: 50563
AE wrote: > > However, after implementation according to the map report the RDCLK > component was loadless and removed as well as te RDBK component. My TRIG > input port was not placed althought the DATA port was still placed, > albeit with no connected signals to drive the pad. I verified this in > the FPGA editor. Hi AE, Been there, done that, bought the T-shirt. I'm just digging through my files to find a document I wrote once we solved it. Had some help from John Blaine at Xilinx - basically you need a custom EDIF black box to get around this problem. WIll dig it out and let you know where to find it. Regards, JohnArticle: 50564
This is a multi-part message in MIME format.
--------------070904090505060406000709
Content-Type: text/plain; charset=us-ascii; format=flowed
Content-Transfer-Encoding: 7bit
Hi aaron,
I couldn't find the longer document which talks about it, but found the
EDIF and associated VHDL file (attached). Put the EDIF and VHDL in your
project directory, and then connect your signals (RB, TRIG, RIP) to the
ports created in the READBK.VHD file. I think you'll need to edit the
last line of the EDIF file to put the correct part number - not sure if
it's strictly necessary but I did and it worked for me.
Good luck,
John
--------------070904090505060406000709
Content-Type: text/plain;
name="readbk.vhd"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
filename="readbk.vhd"
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity readbk is
Port ( TRIG_SIG: in std_logic;
DATA_SIG: out std_logic;
RIP_SIG: out std_logic);
end readbk;
architecture Behavioral of readbk is
component blaine1
port( TRIG_SIG: in std_logic;
DATA_SIG: out std_logic;
RIP_SIG: out std_logic);
end component;
begin
U1: blaine1 port map (TRIG_SIG => TRIG_SIG,
DATA_SIG => DATA_SIG, RIP_SIG => RIP_SIG);
end Behavioral;
--------------070904090505060406000709
Content-Type: text/plain;
name="blaine1.edf"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
filename="blaine1.edf"
(edif blaine1
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2002 5 7 13 49 23)
(author "Synplicity, Inc.")
(program "Synplify" (version "7.0.0, Build 139R"))
)
)
(library UNILIB
(edifLevel 0)
(technology (numberDefinition ))
(cell GND (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port G (direction OUTPUT))
)
)
)
(cell VCC (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port P (direction OUTPUT))
)
)
)
)
(library work
(edifLevel 0)
(technology (numberDefinition ))
(cell RDBK (cellType GENERIC)
(view syn_black_box (viewType NETLIST)
(interface
(port TRIG (direction INPUT))
(port DATA (direction OUTPUT))
(port RIP (direction OUTPUT))
)
)
)
(cell blaine1 (cellType GENERIC)
(view behavioral (viewType NETLIST)
(interface
(port TRIG_SIG (direction INPUT))
(port DATA_SIG (direction OUTPUT))
(port RIP_SIG (direction OUTPUT))
)
(contents
(instance VCC (viewRef PRIM (cellRef VCC (libraryRef UNILIB))) )
(instance GND (viewRef PRIM (cellRef GND (libraryRef UNILIB))) )
(instance U1 (viewRef syn_black_box (cellRef RDBK)) )
(net (rename trig_sig "TRIG_SIG") (joined
(portRef TRIG_SIG)
(portRef TRIG (instanceRef U1))
))
(net (rename data_sig "DATA_SIG") (joined
(portRef DATA (instanceRef U1))
(portRef DATA_SIG)
))
(net (rename rip_sig "RIP_SIG") (joined
(portRef RIP (instanceRef U1))
(portRef RIP_SIG)
))
(net (rename VCCZ0 "VCC") (joined
(portRef P (instanceRef VCC))
))
(net (rename GNDZ0 "GND") (joined
(portRef G (instanceRef GND))
))
)
)
)
)
(design blaine1 (cellRef blaine1 (libraryRef work))
(property PART (string "xc4010epc84-4") (owner "Xilinx")))
)
--------------070904090505060406000709--
Article: 50565"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<Sp5K9.102$9Q.11397460@newssvr13.news.prodigy.com>... > > OK, I understand. Yes, I was planing on registering everything at the > IOB's. > The signal standard is LVCMOS33 for input busses and LVDCI_33 for output > busses. > > The design will have one clock coming into a GCLKx pin in bank 5. This > clock will get DCM'd into three new clocks: a de-skewe'd version and two > synthesised frequencies. > > One such frequencies is the SDRAM clock. I was planning on delivering two > copies of the clock to the memory array by using the DDR mechanism in the > IOB's. As I understand it, this is an elegant and effective way to move a > clock off chip along with the data it is clocking out and, at the same time, > with the guarantee that the clock will be in time with this data. Do you > know of any issues/problems with this methodology? I have not used the DDR method of sending a clock off chip. For source synchronous clock and data, that would be ideal and can't imagine any trouble you would have with it. What I have used is DCM's for off-chip deskew. In fact, I just completed a V2 design that uses 11 of the 12 DCMs - either for deskew'ed on-chip clocks (7 internal clock domains) or for deskew'ing clocks that go to a total of 6 off chip devices (including 3 banks of SRAM's). What I did was dedicate a DCM to each off-chip device, where the FB of the DCM comes from that off-chip net, length matched. This works very well - the clock that appears at the input pin of the far away device is phase aligned to the master input clock to the FPGA. Have fun, MarcArticle: 50566
Hi, We want to buy a board with Xilinx FPGA Virtex-II. The algorithms we developed can be downloaded to the FPGA to evaluate our system. I wish the FPGA is bigger than XC2V3000. Also I require the board comes with 8 channel high speed A/D, whose maximum sampling rate should be higher than 50 MHz. Our application is related with software radio. I have found one even with DDC chips besides FPGA and ADC. Unfortunately it has only 4 channel ADC. Anyone know the similar products? ThanksArticle: 50567
Prashant wrote: > I appreciate your response and that definitely helps my understanding. > I was under the impression that the wire delays were estimated > accurately in the synthesis process, but I guess not. "Wire" delays in fpgas are very sensitive to place and route because the switch elements and parts of the path itself are silicon rather than aluminum. Consider using one of the global clock pins to rule out hold violations. -- Mike TreselerArticle: 50568
Good point. That means you'd know how many terms you'd have to take in the polynomial to get a sufficiently accurate result. Then the 2^N part just requires that you add N*log(2). Kip -- Get daily news and analysis from the FPGA market for pennies a day. Subscribe to The FPGA Roundup today: http://www.KipIngram.com/FPGARoundup.html -- "Dave Martindale" <davem@cs.ubc.ca> wrote in message news:atao4n$o9e$5@mughi.cs.ubc.ca... > "Kip Ingram" <Kip@NOkipSPAMingram.rom> writes: > >The general approach to rapidly computing logarithms (used by Henry Briggs > >to generate the log tables he published in 1617) is to first reduce the > >problem to the computation of the logarithm of a value very near 1. Then > >use the power series > > > log (1+x) = x - x^2/2 + x^3/3 - x^4/4 ...... > > >to get a value of whatever accuracy you need. The "cleverness" is in how to > >creatively move the argument near 1. > > I thought that in this case the guy was starting with a floating point > number. In that case, the floating point exponent is *already* the > integer part of the base-2 log of the number, while the floating point > mantissa is *already* a number in the range [0.5, 1). So you're in a > position to use the polynomial approximation to get the fractional part > of the logarithm. Or use a lookup table, as someone suggested. > > But the hard part has already been done in the process of normalizing > the floating-point number. > > DaveArticle: 50569
Ryan,
At present the command to generate symbols for entities in a file,
expects that the VHDL file does not refer any other source files. Therefore
you are not doing anything wrong, when these errors are seen. You have also
described the workaround for this problem in your posting. This issue will
be resolved in a future version of the software.
- Subroto Datta
"Ryan" <ryans@cat.co.za> wrote in message
news:3df8b929.0@obiwan.eastcoast.co.za...
> Hi
>
> I have a vhdl project that makes use of a package that lives in an
external
> vhdl file. The package contains a whole lot of constants. It is basically
a
> look-up table. The project compiles & simulates perfectly in Quartus 2.1.
> Now when I come to make a symbol for it to use in another project, the
> wheels fall off! I open the vhdl logic file, click on tools and then click
> on "Create symbol files for entities in current file". Then a whole lot of
> errors come up to do with the external package. Now if I cut the package
and
> paste it into the logic vhdl file, then it creates a symbol for the block
no
> problem.
>
> What am I doing wrong? Suggestions would be most welcome.
>
> Thanks
> Ryan
>
>
>
Article: 50570Your new circuit will have 2 clock domains and is passing signals from one to the other. It is not guaranteed to work the same in the real FPGA as it does in your simulation. And now the reason... While HDL's look like computer programs, they really aren't, they're just another way of describing a circuit. The cicuit is made up of elements that are already exisiting in the FPGA you're targeting with certain pre-existing connections. In reality they can only be used in a limited number of ways even though the HDL would seem to suggest that you can do things any way you want. Since you're starting out, try to just use one clock, use any other signals as enables. Best way to learn this stuff is to check out some simple examples from other people. Regards President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- "Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it> wrote in message news:<mV1K9.10145$ab2.280679@news1.tin.it>... > "Muthu" <muthu_nano@yahoo.co.in> ha scritto nel messaggio > news:28c66cd3.0212120657.2814b0d6@posting.google.com... > > > 1. Just Increment a counter with HCLK always > > 2. Detect a the rising edge of the LCLK by sampling the > > LCLK with > > respect to HCLK edges, and generate a Pulse with respect > > to HCLK. > > 3. This pulse has to go as a Asynchronous RESET input to > > the Counter. > > > > Hope this helps. > > Thank you, I'll try. In the meanwhile I've found a way that works, but I > don't fully understand how: :-) > > architecture Behavioral of cntdiv is > begin > process( CLKIN, PULSE) > variable cnt: std_logic_vector( 7 downto 0); > variable oldcnt: std_logic_vector( 7 downto 0); > begin > if CLKIN='1' and CLKIN'event then > QOUT <= cnt-oldcnt; > oldcnt := cnt; > end if; > > if PULSE='1' and PULSE'event then > cnt := cnt+1; > end if; > end process; > end Behavioral;Article: 50571
First, what are your 80 16X1 rams used for, and in what configuration (e.g. 80 wide by 16 deep, etc..) fpga_wonderkid@yahoo.com (FPGA Wonderkid) wrote in message news:<23069c63.0212120205.478a78c@posting.google.com>... > Hi, I am planning to use an Altera Cyclone/ACEX device in place of my > existing XC2S200E device. However, as I use lot of distributed RAM, I > cannot easily go to Cyclone/ACEX as they do not support distributed > RAM like Xilinx. Can anyone tell me how to efficiently convert the > spartan-2e distributed RAM primitives into Cyclone/ACEX block ram > architecture. What i need to know is how to convert 80 nos of 16X1 > RAM, I have implemented in spartan-2e to cyclone architecture w/o > consuming too much space. > > > Thanks!Article: 50572
"Steve Casselman" <sc@vcc.com> wrote in message news:<KG3K9.53$y57.4758831@newssvr13.news.prodigy.com>...
> Try this. Go into the FPGA editor and call up the device you use. Then make
> a "blank" ncd file. Then take you design and do a bitgen
>
> ---- from Austin Lesea
>
> bitgen {all options used for design1.bit} -g ActiveReconfig:Yes -r
> design1.bit design2.ncd
>
> This creates the difference bitfile from the two ncd files.
>
> In this way you can see exactly what a partial bitstream size is for
> reconfiguration.
>
> --------
>
> I think if you make sure there are columns that are empty you can save you
> space. You may have to prepend some frames for initialization. The problem I
> see is if you use all the I/O since I/O bits and logic/routing bits are in
> the same atomic frames.
>
> Steve
Hmm, Even if you can generate a shorter bit stream that will be
sufficient for your implementation, the FPGA will try to read the
entire 1.3 mil. bits. So I wonder what will the 18V01 return above
the first 1 mil. bits ? Will it wrap around and deliver the original
bit stream again, or will it return garbage or will it return some
other pattern ?
Just curious ...
rudi
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Article: 50573Chen Wei Tseng <chenwei.tseng@xilinx.com> wrote in message news:<3DF8A4F3.C042BA5C@xilinx.com>... > Muthu, > > When using RLOC_ORIGIN, make sure you're appending it to comp that has > RLOC of X0Y0 since RLOC values accumulates. > How to find which component is Located in X0Y0. I searched the .ncf file, none of the elements are placed in that Location. > ex. RLOC_ORGIN at slice_x10Y10 on comp that has RLOC of X5Y5 will result > in the comp be loc-ed at X15Y15. > > So when you're trying to Loc down the RPM, make sure the accumulated > RLOC_ORIGIN value isn't pushing part of your RPM out of the device slice > boundary. > > As for BRAMs, MULTs, Floorplanner's RPM creation will leave them > unconstrained. You can either manually create another RPM for the > BRAM/MULTs, or go over XAPP416 on the exact detail of using it. > Basically, user has to read teh RPM_GRID coordinate from FPGA Editor and > manually append the RPM_GRID coordinate value to the RPM. > > Note that Floorplanner doesn't fully support RPM_GRID yet. > > Regards, WeiArticle: 50574
Saurabh Pal wrote:
> Following is a Handel-C program which reads a 128-bit data,
> copies the data to a buffer and, finally, the buffer contents are
> given to the output pins.
>
> The data input/output interface is 32-bit unidirectional.
>
> After implementing the given design on a Xilinx Virtex-II FPGA,
> I'm getting a clock speed of 126.374MHz.
>
> How can a better clock speed can be achieved?
How much better do you need? And what can you change? Do you have a
constraint (.ucf) file that defines the required timing for your
design? The tools will do a better job if you tell them exactly what
you need in terms of timing.
A short list of suggestions, in no real order, not all aimed at your
design:
1) Buy a faster FPGA. Might make sense if you are basically done with
the design and the volume is tiny.
2) Understand more about the problem areas. Get a full timing report
with the timing set to the requirement, and look closely at the failing
paths. Identify the sources and destinations of the failing paths, and
identify where in the source code these come from. Often you can change
the source to produce faster logic. Try some other methods of getting
the the same result. For example, rather than do this:
> data[0][index] = sig_data[31:24];
> data[1][index] = sig_data[23:16];
> data[2][index] = sig_data[15:8];
> data[3][index] = sig_data[7:0];
> }
Try this:
data[0][0] = sig_data[31:24];
data[1][0] = sig_data[23:16];
data[2][0] = sig_data[15:8];
data[3][0] = sig_data[7:0];
data[3:1] = data[2:0];
Now, does this produce faster logic or slower logic? Look carefully at
the timing report and at these paths in FPGAEditor to find out why. Or
was the logic not the critical path, and the result is basically the
same??
3) Assign a pin out. With a good specified pin out, Xilinx's tools can
do a better job. The hard part is learning how to assign a good pin
out. Spend some time looking at the results with FPGAeditor (or
floorplanner if you have Webpack only), and see what pins might be moved
to reduce the routing delay between the internal logic and the pins.
4) Floorplan. Register (variable) names are somewhat constant between
the source and the implantation. By putting the registers into the
"correct places", you give hints to the placer where the logic needs to
go.
5) Have the critical paths coded in VHDL as "netlists of primitives"
with fixed (or relative) placements.
--
Phil Hays
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