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Although I did not see the xdl files in the web release look in $XILINX/help/xdl. In the xdl version of a design you get stuff like net "FIVE_SEC_COUNT<13>" , outpin "FIVE_SEC_COUNT<13>" XQ , inpin "N1961" G3 , pip R27C32 S1_XQ -> OUT5 , pip R27C32 OUT5 -> N14 , pip R26C32 S14 -> S_P14 , pip R26C32 S_P14 -> S0_G_B3 , # net "FIVE_SEC_COUNT<13>" loads=1 drivers=1 pips=4 rtpips=0 So you can get the number and kind of pips the signal goes through. If you look at a the file generated by xdl -report -pips v300 v300.xdlrc (111 megabytes) You can see all the resources for a v300. All tiles all the I/O all the Slices and all the routing information. Even with just net information from a design file you can start to do some in house tools that you might like better than the tools Xilinx supplies. The good thing about xdl is it is all readable and has all the information needed to do what ever you want. For example you could write a program that only ripped out nets with 10 pips and then give it back to the router. Or you unroute some part of the hierarchy or preplace something... Steve "Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote in message news:av1une$22bf$1@agate.berkeley.edu... > In article <7B373EDCA1DF1741917BCFC2E20A52DA08BF1F0B@pfx21.stu.nus.edu.sg>, > Liao Jirong <iscp1097@nus.edu.sg> wrote: > > > >>However, I don't think you can really get a delay feel from it, as > >>routing has a significant effect and you can only do a gross ad-hoc > >>estimate of delays based on logic levels and manhattan distance. > > > >Estimate of delay is fine. How to do that? Could you specify more > >details? > > Unfortunatly, Xilinx doesn't publish the delay details you want, so > you just have to come up with a crude measure based on manhattan > distance. > > > > -- > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 51126
What parts are you looking to program? I've used the BP programmers and they rock, no question about it. However, having said that, it seems that ISP seems to be the way everything is going these days due in part to the smaller packages and semi conductor tech (EEPROM, flash) so I'd question what you'd need an actual physical programmer for these days. Regards President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- Dave <dfnr2@yahoo.com> wrote in message news:<m34r8yao2s.fsf@yahoo.com>... > Hello, > > I'm thinking of letting my Data I/O coast on without further software > updates, and put the money into a new BP programmer. I'm frustrated > by the lack of pricing information on the BP website, or any > distributors' sites. Would anyone who recently bought a BP-1200 care > to post some prices for the 1200, any of the extra modules, any > upgrades, and the software upgrade to generate serial numbers. > > Also, is it possible to write your own little program to generate > serial numbers, and have the free BP software call it, or do you still > have to pay for an "advanced features" package? > > It would be great if some kind soul posted some info here; > alternatively, I'd be grateful for a scanned pricelist by email. I've > contacted the local rep, but since there's no reply, I assume he's on > vacation. > > Thanks for any info, > > David.Article: 51127
The simple answer is that, in an FPGA, you can implement any combination of logic functions that you can otherwise implement in an ASIC, or put on a pc-board ( well, no analog stuff!) That means, you can do what you intend to do, no problem. On a more sophisticated level, you can also use partial reconfiguration to modify the logic functionality ( not just the data) in one part of the FPGA, as determined by results from another ( or even the same) part of the device. This can get quite esoteric... Peter Alfke, Xilinx Applications ============================= Harkirat wrote: > HI :) > Im new to FPGA's and im wondering if it is possible to program a > segment of the FPGA to perform a particular function say act as a > binary divider and then program another segment to perform a different > function in combination with the first one ....say the second program > needs to divide 2 numbers and it makes use of the first segment to > achieve this > Is this possible? > Thank you for you kind consideration in advance:) > Harkirat > i1073@tamu.eduArticle: 51128
Interesting problem. Here is a half-answer and half-promise: You can use series termination with DCI as the FPGA driver, and then ( strange idea! ) keep the FPGA output active ( High or Low) while receiving data from the DRAM. That gives you a brute-force parallel input termination to Vcc or to ground (your choice by manipulating the FPGA Dout line). The problem is that you may end up with poor receive logic levels, depending on the DRAM output impedance and the FPGA I/O standard. The promise is that we are working on configuration standards to solve that issue... DCI looks better every day. Peter Alfke, Xilinx Applications jakab tanko wrote: > Hi Andy, > > This solves one half of my problem; if virtex2 drives the > bidirectional line then DCI will probably work, what about the DRAM > driving the same line (not the same time, of course). There is no > built in series resistor in the DRAM !? > --- > jakab > Andreas Schweizer <aschweiz@iiic.ethz.ch> wrote in message > news:3e1458fc@core.inf.ethz.ch... > > Hi Jakab, > > > > also a happy new year to you! > > > > > a Xilinx Virtex2 on one end and a DRAM on the other, > > > > These have built-in "resistors". You can configure the IO's as > > DCI (digitally controlled impedance) and provide two reference > > resistors per IO bank (VRN, VRP). > > If you instantiate the correct IO buffers in your code, > > probably LVDCI or LVDCI_DV2 (the former with 50 Ohm reference > > resistors, the latter with 100 Ohm), the virtex-ii automatically > > matches the impedance. > > > > HTH, > > Andy > > > >Article: 51129
This is a multi-part message in MIME format. ------=_NextPart_000_001E_01C2B28A.0E4180C0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable If you are using a schematic to connect the two designs, and the entire = bus is available as a port on the symbol for the first design, the bit = that you are intersted in can be tapped. For example if the name of the = bus is busa[16..0] and appears on the symbol for component 1 (first = design), you can draw a bus attached to that port on component 1, give = it a name busa[16..0]. Then if you want to connect bit busa[5] from = component 1, to a scalar port in component 2, draw a wire to the port in = component 2, and name it busa[15]. Basically the splitting and = connection is done by name. - Subroto Datta "Sudip Saha" <sudip.saha@philips.com> wrote in message = news:ee7b2ea.-1@WebX.sUN8CHnE... Hi, I want to connect two of my designs in quartus. There is a bus in one = design. I want to take only one bit of that bus and connect it to other = component(design). Is there any bus splitter in quartus? I can not change the internals of the design. So Internally I can not = take that one bit and assign it to one port. Any comments how this can be achieved? Sudip Saha sudip.saha@Philips.comArticle: 51130
hi prashanth, the code whatever u wrote in the CODE B is synchronous and the first oone is asynchronous. S.RANGA REDDY prashantj@usa.net (Prashant) wrote in message news:<ea62e09.0301021035.77494be8@posting.google.com>... > Hi all, > > I read an article recently which mentioned that an inference of a > latch due to an incomplete IF statement is an asynchronous piece of > code. I agree with that. But if I had this piece of code within a > process which triggers @ the rising edge of a clk, would it still be > considered async ? I would think not. > > for e.g. > ---------------------------------------------------- > Code A > > process(A) > begin > if (A = 1) then > B <= C; > end if; > end process; > ---------------------------------------------------- > > ---------------------------------------------------- > Code B > > process(clk) > begin > if clk'EVENT and clk = '1' then > if (A = 1) then > B <= C; > end if; > end if; > end process; > ---------------------------------------------------- > > I would assume Code B to be synchronous, while code A is async. Am I > correct ? > > Thanks, > PrashantArticle: 51132
Heyho Andy,
I've read all the thread (since now) and think it is a good option to tie
them to GND. But it maybe useful to tie some of them via a resistor
(might even be 0 Ohm) to GND. Like that you have the possibility to
connect easily any testsignals or signals that you forgot in your layout.
Just take the resistor of and you get another accessible IOO of your
FPGA. I always do this, it makes debugging more easy. Just think about
putting an internal signal on the pin in order to analyze it... It helped
me often...
I wish you all a happy, successful and healthy new year! ("Happy new
year, Miss Sophy" for those who know "Dinner for one" :o) )
Be readin' ya,
Thomas
--
No matter if you are going on-piste or off-piste just hit the slope and
stay healthy!
For email-reply replace "nospam" with "kurth".
Article: 51133"Prashant" <prashantj@usa.net> wrote in message news:ea62e09.0301021035.77494be8@posting.google.com... > Hi all, <snip> > > ---------------------------------------------------- > Code A > > process(A) > begin > if (A = 1) then > B <= C; > end if; > end process; > ---------------------------------------------------- > Code B > > process(clk) > begin > if clk'EVENT and clk = '1' then > if (A = 1) then > B <= C; > end if; > end if; > end process; > ---------------------------------------------------- > > I would assume Code B to be synchronous, while code A is async. Am I > correct ? > Yes that's correct. Another way to think about it is to ask yourself what happens when the output signal is not assigned. In Code A, when A is not 1, B has to keep it's old value - hence the synthesis tool infers a transparent latch with A on the Gate (or Enable). In code B, B still has to remember it's value when A is not 1, but that happens "for free" as the assignment to B in a clocked process causes the synthesis tool to infer a D type flip-flop. Most tools would use a flip-flop with a clock enable, and connect A to the CE pin. If there was is no enable flip-flop in the library, then the tool can put a mux in front of the flip flop to choose between input C or the output of the flip-flop B. regards Alan -- Alan Fitch [HDL Consultant] DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 51134
Hi all, I have written a programm for the Xilinx XC4005E PQ100. But now my programm is too large for this FPGA. Unfortunately I let manufactured the printed circuit boards before, so I can't take an FPGA which don't match with the layout of the printed circuit boards. Does anybody know an other FPGA with more memory but the same layout? Thanks to all MarkusArticle: 51135
If you could have a solution where a bidirectional FPGA I/O would have a source (series) termination when driving and also a load (parallel) termination when driven that would eliminate the the need for source termination at the other end (DRAM in this case).. That would be the ultimate DCI, DCI on stereoids if you like :-) For know I think I will put series resistors at the output of the DRAM data lines, one thing I dont know for sure is if this will have any effect on the load that the virtex2 sees when driving these lines? Thanks for your answers, jakab Peter Alfke <peter@xilinx.com> wrote in message news:3E14C766.C049B98C@xilinx.com... > Interesting problem. > Here is a half-answer and half-promise: > You can use series termination with DCI as the FPGA driver, and then ( > strange idea! ) keep the FPGA output active ( High or Low) while > receiving data from the DRAM. That gives you a brute-force parallel > input termination to Vcc or to ground (your choice by manipulating the > FPGA Dout line). > The problem is that you may end up with poor receive logic levels, > depending on the DRAM output impedance and the FPGA I/O standard. The > promise is that we are working on configuration standards to solve that > issue... > DCI looks better every day. > Peter Alfke, Xilinx Applications > > jakab tanko wrote: > > > Hi Andy, > > > > This solves one half of my problem; if virtex2 drives the > > bidirectional line then DCI will probably work, what about the DRAM > > driving the same line (not the same time, of course). There is no > > built in series resistor in the DRAM !? > > --- > > jakab > > Andreas Schweizer <aschweiz@iiic.ethz.ch> wrote in message > > news:3e1458fc@core.inf.ethz.ch... > > > Hi Jakab, > > > > > > also a happy new year to you! > > > > > > > a Xilinx Virtex2 on one end and a DRAM on the other, > > > > > > These have built-in "resistors". You can configure the IO's as > > > DCI (digitally controlled impedance) and provide two reference > > > resistors per IO bank (VRN, VRP). > > > If you instantiate the correct IO buffers in your code, > > > probably LVDCI or LVDCI_DV2 (the former with 50 Ohm reference > > > resistors, the latter with 100 Ohm), the virtex-ii automatically > > > matches the impedance. > > > > > > HTH, > > > Andy > > > > > > >Article: 51136
Thanks. That helps and I appreciate the response. Prashant sudharr@myw.ltindia.com (RANGA REDDY) wrote in message news:<37ba429a.0301022040.7fcb1049@posting.google.com>... > hi prashanth, > > the code whatever u wrote in the CODE B is synchronous and the first > oone is asynchronous. > > S.RANGA REDDY > > prashantj@usa.net (Prashant) wrote in message news:<ea62e09.0301021035.77494be8@posting.google.com>...Article: 51137
Hello, I work on an altera MAX7000 & MAX+PLUS II. I want to use a D latch sensitive to falling edge for clock & rising edge for reset. For the clock it is not a problem but I don't find any lacth which is not sensitive to level on reset pin. It can be made in VHDL but i don't have the license. Is it possible to do it in an other way ? Thanks for your answers. EricArticle: 51138
Markus Walter wrote: > > Hi all, > > I have written a programm for the Xilinx XC4005E PQ100. But now my programm > is too large for this FPGA. Unfortunately I let manufactured the printed > circuit boards before, so I can't take an FPGA which don't match with the > layout of the printed circuit boards. Does anybody know an other FPGA with > more memory but the same layout? I assume that you have checked the other parts in the XC4000E series and none are available in the PQ100 package? I belive that Atmel makes a line of FPGAs which are footprint compatible with the XC4000 Xilinx parts. I don't know if they are voltage compatible with the 4000E parts or if they are available in the PQ100 package. But their parts are easy to check. They only have two lines, the old 6000 and the (slightly) newer one. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 51139
jakab tanko wrote: > > If you could have a solution where a bidirectional FPGA I/O > would have a source (series) termination when driving and > also a load (parallel) termination when driven that would eliminate the > the need for source termination at the other end (DRAM in this case).. > That would be the ultimate DCI, DCI on stereoids if you like :-) > For know I think I will put series resistors at the output of the > DRAM data lines, one thing I dont know for sure is if this will > have any effect on the load that the virtex2 sees when driving these lines? > Thanks for your answers, > jakab There are a few issues to deal with. Typically the series termination is used to match the output driver to the trace impedance so it is smaller than the trace impedance. The parallel impedance normally matches the trace impedance. So the same resistor can not be used for both purposes. However if they use an internal control for direction in the same way a tristate control works, then they can switch the resistance to match in both cases. Is this what Xilinx is thinking about doing? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 51140
The 4010XL is listed in a PQ100 package, but not the XC4010E. You have to check for pin-out subtleties ( most likely none), and the Vcc is of course 3.3 V. That's the best match I could find. Peter Alfke Markus Walter wrote: > Hi all, > > I have written a programm for the Xilinx XC4005E PQ100. But now my programm > is too large for this FPGA. Unfortunately I let manufactured the printed > circuit boards before, so I can't take an FPGA which don't match with the > layout of the printed circuit boards. Does anybody know an other FPGA with > more memory but the same layout? > > Thanks to all > MarkusArticle: 51141
hamish@cloud.net.au wrote: > Kate Kelley <kate.kelley@xilinx.com> wrote: > > > > I don't believe you want to use the DESKEW_ADJUST attribute. This attribute is used if > > you are doing a source-synchronous designs as described in different Xilinx Source-Sync > > application notes. Your clocking scheme does not match what Xilinx suggests. If you are > > trying to line up a clock with the I/O, I would used the FIXED_PHASE_SHIFT attribute to > > adjust the phase of the clock. > > Is there a difference between system synchronous with a phase shift of X > and source synchronous with a phase shift of Y? > > I have had source synchonous working since before Xilinx offered this > feature; is there any advantage in switching, given that we have already > determined the appropriate phase shift for our application? > > Thanks, > Hamish > -- > Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au> Hamish, Sorry for the late reply. For particular applications there are advantages of using the DESKEW_ADJUST. If your design matches the Source Synchronous designs described in Xilinx App Note and the Datasheet, there are advantages. From what I remember of your design, it does not match therefore I don't believe there will be any advantages. If the phase shifting worked before, I would stick to that. You have more control on how much a clock is shifted using the FIXED/VARIABLE PHASE SHIFT than you do with the DESKEW_ADJUST. KateArticle: 51142
jakab tanko wrote: > If you could have a solution where a bidirectional FPGA I/O > would have a source (series) termination when driving and > also a load (parallel) termination when driven that would eliminate the > the need for source termination at the other end (DRAM in this case).. > That would be the ultimate DCI, DCI on stereoids if you like :-) That's exactly what I suggested and (kind of) promised. > > For know I think I will put series resistors at the output of the > DRAM data lines, one thing I dont know for sure is if this will > have any effect on the load that the virtex2 sees when driving these lines? If you series-terminate the DRAM pins with an external resistor, this will be invisible to the FPGA DCI-terminated output, and will have no impact to the voltage at the DRAM-end of the pc-board trace, but the resistor + DRAM pin capacitance will form a low-pass filter. Let's assume 30 Ohm and 10 pF = 300 ps. That's all. In this case you must of course 3-state the FPGA when it receives data. Peter Alfke, Xilinx Applications > > Thanks for your answers, > jakab > Peter Alfke <peter@xilinx.com> wrote in message > news:3E14C766.C049B98C@xilinx.com... > > Interesting problem. > > Here is a half-answer and half-promise: > > You can use series termination with DCI as the FPGA driver, and then ( > > strange idea! ) keep the FPGA output active ( High or Low) while > > receiving data from the DRAM. That gives you a brute-force parallel > > input termination to Vcc or to ground (your choice by manipulating the > > FPGA Dout line). > > The problem is that you may end up with poor receive logic levels, > > depending on the DRAM output impedance and the FPGA I/O standard. The > > promise is that we are working on configuration standards to solve that > > issue... > > DCI looks better every day. > > Peter Alfke, Xilinx Applications > > > > jakab tanko wrote: > > > > > Hi Andy, > > > > > > This solves one half of my problem; if virtex2 drives the > > > bidirectional line then DCI will probably work, what about the DRAM > > > driving the same line (not the same time, of course). There is no > > > built in series resistor in the DRAM !? > > > --- > > > jakab > > > Andreas Schweizer <aschweiz@iiic.ethz.ch> wrote in message > > > news:3e1458fc@core.inf.ethz.ch... > > > > Hi Jakab, > > > > > > > > also a happy new year to you! > > > > > > > > > a Xilinx Virtex2 on one end and a DRAM on the other, > > > > > > > > These have built-in "resistors". You can configure the IO's as > > > > DCI (digitally controlled impedance) and provide two reference > > > > resistors per IO bank (VRN, VRP). > > > > If you instantiate the correct IO buffers in your code, > > > > probably LVDCI or LVDCI_DV2 (the former with 50 Ohm reference > > > > resistors, the latter with 100 Ohm), the virtex-ii automatically > > > > matches the impedance. > > > > > > > > HTH, > > > > Andy > > > > > > > > > >Article: 51143
rickman wrote: > However if they use an internal control for direction in > the same way a tristate control works, then they can switch the > resistance to match in both cases. > > Is this what Xilinx is thinking about doing? Yes, but it's even simpler. The resistance is not even switched around, and the output is not 3-stated. It's just made active Low (or High). Intriguingly simple. :-) Peter Alfke > > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 51145
Muthu, The 5.1i software SHOULD always handle all 16 global clocks. Before you invest time in floorplanning, run the design through PAR and see what happens. There are still some designs that PAR can't handle and do require floorplanning. These designs should be sent to the Xilinx hotline so engineering can take a look at them. Kate Vikram wrote: > muthu_nano@yahoo.co.in (Muthu) wrote in message news:<28c66cd3.0212250047.7dc59bca@posting.google.com>... > > Aurash Lazarut <aurash@xilinx.com> wrote in message news:<3E084E50.30D2E989@xilinx.com>... > > > Muthu, > > > > > > DCMs are located on the top and bottom of the bram column (on the IOB > > > ring) if you stay with the mouse on these resources in graphical rep. of > > > the die, you can see the coordinates (the same in fpga_editor) > > > Hope this helps, > > > Aurash > > > > Hi Aurash, > > > > Thanks. If we use more than 8 BUFG, then manual placing of BUFG is > > required. But what should be the approach. Should we LOC the DCM > > first? where can i find more details? > > > > Thanks and regards, > > Muthu > > Irrespective of the number of DCMs used in a design, it is always > advisable to LOC the DCM and the BUFG/BUFGMUX. For more details on > usage of global clocks - (assuming a Virtex2 device) - > http://www.xilinx.com/publications/products/v2/handbook/ug002_ch2_gcn.pdf > > Hope this helps, > Vikram.Article: 51146
If your real concern is messaging, then you can suppress all output except ERRORS (STDERR) by specifying the -intstyle silent option in XST. This is available as of SP 2. However, if you want to address `define text macros warnings only. There's no switch to suppress such warnings. Personally, I believe this is a Verilog design methodology issue. You should use parameters in the lower-level modules and use defparam on the instantion of the lower-level module. The param/defparam allows a cleaner method of reassigning values. The `define should all be one centralized file that is compiled with other design files. `define width 8 module top ( ); defparam U1.port_width = `width; sub U1 (.a (a1), .b (b1), .c (c1)); endmodule module sub (a, b, c); parameter port_width = 4; input [port_width-1:0] a, b; output [port_width-1:0] c; assign c = a + b; endmodule Carl De Far wrote: > > I have ISE 5.1i running under windows 2000. > > I am getting the following warnings I'd like to suppress (during synthesize > / synthesis) from the syntesis report. > > WARNING:HDLCompilers:38 - infc_constants.v line 142 Macro 'W_ERR_CS_ADDR' > redefined > > These redefinitions are intended and I do not to to see the warnings, they > clutter up the console output. > Any ideas how I might suppress these warnings? > > I checked xilinx support website, no joy. > thanks > > p.s. i have searched http://www.xilinx.com/support/searchtd.htm > answers database > answers archive > application notes > technical tips > xilinx software version 5.1i > application version i+F+34450 > > keywords: supress warnings -- / 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) \ \ ` Xilinx hotline@xilinx.com / / 2100 Logic Drive http://www.xilinx.com \_\/.\ San Jose, California 95124-3450 USAArticle: 51147
Peter Alfke wrote:
> On a more sophisticated level, you can also use partial reconfiguration
> to modify the logic functionality ( not just the data) in one part of the
> FPGA, as determined by results from another ( or even the same) part of
> the device. This can get quite esoteric...
In cases where your pcb has the flash and firmware to load
the FPGA, you can keep multiple configurations
in flash available to downloade in response to
a system mode change.
-- Mike Treseler
Article: 51148Yes, absolutely true. But it needs an external piece of logic to maintain the control, since the FPGA is "dead" during the whole reconfiguration process. That's not the fact during partial reconfiguration, but it may require real finesse to take advantage of that. Peter Alfke ================== Mike Treseler wrote: > Peter Alfke wrote: > > > On a more sophisticated level, you can also use partial reconfiguration > > to modify the logic functionality ( not just the data) in one part of the > > FPGA, as determined by results from another ( or even the same) part of > > the device. This can get quite esoteric... > > In cases where your pcb has the flash and firmware to load > the FPGA, you can keep multiple configurations > in flash available to downloade in response to > a system mode change. > > -- Mike TreselerArticle: 51149
Aki,
Check out XFLOW.
http://toolbox.xilinx.com/docsan/xilinx5/pdf/docs/dev/dev.pdf
Chapter 22.
XFLOW is a command line tool similar to makefiles. It might be what you want to
do.
Kate
Aki Niimura wrote:
> Hi everyone,
>
> I have been using Xilinx design manager for years and I liked it as I can
> organize multiple versions and revisions.
>
> Unfortunately, Xilinx has discontinued the design manager starting from
> ISE 5.1i. And 'ise' didn't give me the same flexibility as the design
> manager provided.
>
> Now, I'm thinking of running Xilinx projects using Makefile.
> 'ise' provides a command line log file ('<project>.cmd_log') but it is
> not a complete Makefile.
>
> I thought many people have already created such Makefile for Xilinx ISE5.1i.
> (I just don't want to reinvent the wheel)
>
> Could anybody share such Makefile with eveyone?
>
> Any feedbacks will be highly appreciated.
>
> Best regards,
> Aki Niimura
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