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Ian (Jock), It all depends on what speed you are running. In my experience of customer designs that are running fairly slow (<60MHz) they have had no problems literally filling the devices to the gills. As you increase the usage, you end up with the Mapper merging un-related logic, and the side effect of this is of course performance. Provided that you have covered all the timing requirements adequately you should not find that anything does not work if the mapper starts merging logic. TRCE will then tell you whether or not it will work. In this case, you may then want to try thw Map -timing option to see if it improves. Dave Jock wrote: > What is the recommended maximum usage in a Virtex FPGA. I've heard on the > grapevine that more than 80% full will give sub-optimal timing in a typical > design. > > I'm using an XCV50 which various between being 99% and 103% of slices being > used (about 20% of these having unrelated logic), depending on how I set > options such as resource sharing, etc. > > When I change one function, I find a completely unrelated function will stop > working.Article: 42526
ybc wrote: > Dear All Dir > > Xilinx XC2S150 PQ208 slave parallel mode for flash download program error > !!! > > CCLK = 1.832MHZ Flash AT29C040-12, PROG. INIT push high 10k (PROG link at > push putton). M0=0,M1=1,M2=1 > 1. push putton > 2. wr.cs go lo, busy = lo > 3. init goto lo 1uS go hi > 4. flash addr counting and data output to XC2S150 > 5. about 40uS init go hi , why? I don't think INIT went high - should have gone low to indicate framing or CRC error. If Init is high and stay's high then everything is fine. If init never goes low, and Done never goes high, then the chances are that you have the data incorrectly programmed in the Atmel part. The FPGA *must* see the AA995566 sync word before *anything* will work ie Done, Init etc.... Dave > > 6. stop all > > Help Me please!Article: 42527
Peter Alfke wrote: [Power-Up-Problems with XC95288XL, XC95144XL] > Second, as you noted, the JTAG command basically "heals" the device. > What is going on here is that at the end of a JTAG command (many of > them, anyway), the internal TAP controller receives an additional > command to re-transfer the internal Flash bits to SRAM cells within > the chip. I use the XC95(XL) on boards which may be continuously powered for many days or weeks and i would like to do this re-transfer from time to time without switching the power off and on. Just to avoid any power-up problems and to be on the safe side in case the power had been bad once during the recent days. Unfortunatelly these boards work stand-alone and i cannot perform a JTAG programming session while running. Is there any way to perform this re-transfer with simple glue logic or other easy means? TIA; Ralf.Article: 42528
Paul, Why don't you use either FPGA Editor, or XDL? FPGA Ed: Change to R/w mode, Select the ROM, Hit EditBlk, Then hit F=, and you can change the values. XDL: Convert the Ncd file to .xdl (using xdl -ncd2xdl) and search for the instance name. Change the INIT values, and save. Then use XDL to change back (using xdl -xdl2ncd) and then run bitgen.... Dave Paul wrote: > Hy, > > I am using a ROM in my design on a VirtexE-1000. This ROM is made as a > RAM block where the WE signal is always inactive. To write the initial > value to the ROM I regenerate the core (core generator) assigning a > new init file to the memory. The problem is that doing it I have to > re-synthetize and P&R the whole design everytime I want to change some > value in the ROM. Is there any way to change the ROM content without > synthesis and P&R?? (I am using Xilinx ISE 4.2 tools and the XST > synthetizer) > > Thaks in advance!! > Paul.Article: 42529
Well, We are testing many of them in the Characterization Lab, and doing all of the things we normally do with real silicon. People tell me they are shipping them to customers..... I see the yield reports from the fab..... I see the test reports from test..... I have seen the serializer/deserializer test report with jitter transfer, jitter tolerance, pattern sensitivity, etc etc etc all the way to 3.125 with the pre-emphasis settings over 0 10 20 "" of FR4, and so on and so forth. I have seen people play freeware C games on the demo board (what better use of a processor for a demo?). I have seen "hello world" execute back in January, and later Pi calculated to 300 decimal digits in February..... Can't do that with a rumor, can you? Don't confuse Xilinx with other companies, please. When we say we have a new part, we really physically have it, and we really have physically shipped it to someone to prove it. We ususally pre-annouce our intent to make a new family a year before we release it. Virtex II Pro was talked about over a year ago in general terms with our public announcements of our agreements with Connexant, and IBM. From the pre-announcement to the real announcement, and here we are! Virtex II was announced a year before, and it is now >10% of our shipments (by $). Can't do that with rumors either. Oh, and please miss - spell Virtex properly. Vertex is a geometric term, or the name of a Japanese Radio company (Used to be called Yeasu). Austin SECRET wrote: > Hi, > > I noticed that Xilinx is claiming on their website that they have a > Vertex II PRO with a 3.125 Gbps Transceiver and up to 4 IBM PowerPC > Processors? Can you actually get silicon for this or is this just > Marketing BS? > > (do not e-mail me.. just post here) > > >Hideout<Article: 42530
Hi, I'm using webpack 4.1, I want to know how can I generate .sdf and .vhd output files for modelsim simulation? LaurentArticle: 42531
Rick, I grant you may not be able to get by with less than six clocks. At least with telecom, the speeds are all bounded, and well known. Look at the data sheet to understand the clocking of the part. And feet, pounds, seconds are the units we continue to torture ourselves with here in the US, while others enjoy the beauty and simplicity of the metric system. Commas and periods as delimiters are a similar strange habit that is of interest to some. Austin rickman wrote: > Austin Lesea wrote: > > rickman wrote: > > > > > Austin, > > > > > > I think you need to read the original post more carefully. He is not > > > working with a 1 MHz clock, it is an 11 MHz clock. > > > > OK. Still no reason for a DLL. > > > > > The other clock is > > > either 4 MHz or 4 GHz depending on if he is using the comma as a decimal > > > point or as a thousands marker. I find that whole comma vs. period > > > thing very confusing. How did we get to a state where half the > > > technical world uses an opposite notation from the other half? > > > > And how many miles per gallon does your car get? > > I am lost. What are you trying to say??? > > > > If it is 4 GHz, then I can't help at all. If it is 4 MHz, it is no > > different that 1 or 11 MHz. > > I agree, but my point is that it is not clear. > > > > But even if he is working with a 1 MHz clock, how does that eliminate > > > the need for clock deskewing? If he has a minimum hold time that is not > > > met without the clock deskewing, then he will need to use it. > > > > Well, he can use the time honored techiques of using the falling edge of the > > clock to sample, or some other technique that was used for thirty years > > before the DLL came into being. > > You are assuming that he has control over all aspects of the design. He > may be working with a signal that is only defined over a very small > window around a single clock edge, say 2 nS setup and 1 nS hold. Of > course you can start making assumptions about the nature of the setup > time or hold time if you understand the other half of the circuit, but > often a user has to work with a spec that gives no insight into that. > > > > I think he was asking for a little more info on how DLLs work, what they > > > accomplish and in which situations you would want to use them. > > > > For that, I recommend the website, and the original Virtex DLL app note. > > > > > > > > I personally would like to understand SpartanII clocking better. I need > > > six clocks in my design and I am not sure what pins to use to assure > > > that they are routed using low skew paths inside the chip. Only two of > > > these clocks need the DLLs for deskewing inside vs. outside the chip. > > > > Well, there are only four clock resources in the chip, so two of them are > > going to have be very carefully placed, perhaps even by hand. I would put > > the highest frequency ones on the internal BUFG resources, and then tightly > > constrain the slowest two, and then verify the results. I would use the > > DLLs are requried for deskew of the highest speed clocks. > > I am not clear about what the four clock resources are. Are you saying > that there are only four BUFGs in the Spartan II and they go hand in > hand with the DLLs? > > > Why six clocks? Anyway to use fewer clocks and use clock enables? I once > > had a design that had 10 clocks, and I had a consultant come in who reduced > > that to two global clocks. All of the others went away through the use of > > the clock enables on the FF's in the design. > > Four clocks with clock enables is not the clean approach I would like. > I have a memory bus clock at 100 MHz, an MCU bus clock at 30.xxx MHz and > four IO clocks at independant rates from 8 kHz to 60 MHz set according > to the application which varies. Even if we use clock enables, that > requires the reclocking of the data and the IO clocks would need to be > distributed for the data reclocking. How would that be accommodated? > Is there a way to use conventional routing and keep the skew low for a > small number of clock inputs? > > > I know sometimes it is not possible, but this experience really opened my > > eyes (E1 <> E2 asynchronous multiplexer/demultiplexer). > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 42532
Oh darn. Austin Noddy wrote: > Ah... herein lies the problem... as mentioned in my original post, I am > using a Spartan II (200k). Hence the need to design one from scratch. > > adrian > > > Adrian, > > > > The DFS in Virtex II or II Pro can provide an output that is M/D times the > > input. > > > > For example, you could multiply the 5 MHz input by fifteen over one, to > get 75 > > MHz as an output frequency. The jitter will be: 0.89 ns Peak to peak, > (6.7%) or > > less. This is from our jitter calculator that predicts the worst case > output > > jitter of the DFS CLKFX output. Number above is for Viretx II, Virtex II > Pro > > might be less (the predictor program is just being finished now). > > > > Ultimately, you would want to clean up the jitter of the DDFS output, > which > > could be done by the ICS 8745 part. > > > > http://www.icst.com/pdf/ics8745.pdf > > > > This reduces the jitter by a factor of ~ 15 to 1. For even more jitter > > reduction, a VCXO would have to be used (need long time constants and > stable > > oscillator). > > > > Austin > > > > Noddy wrote: > > > > > Thanks for the reply, Austin, > > > > > > Using an external PLL together with a VCO would multiply my frequency > up. > > > However, is it possible to multiply this frequency up internally? Or am > I > > > missing something here. > > > > > > Adrian > > > > > > > Noddy, > > > > > > > > To use a DDFS, you need 2 X the highest output frequency as the input > > > > frequency. I would take the 5 MHz maser, multiply it up externally > with a > > > PLL > > > > to > 100 MHz, and then run the DDFS with that. You also may have to > > > filter the > > > > 1/CLK jitter from the DDFS output, and another PLL that is 1:1 will do > > > that > > > > fine. > > > > > > > > Or, you can synthesize a 2 MHz output with your 5 MHz clock, and run > it to > > > a PLL > > > > that is 1:16 to get your 32 MHz AND filter the jitter at the same > time. > > > > > > > > For ultra low jitter and stability, I would use a VCXO as part of the > PLL > > > doing > > > > the filtering. > > > > > > > > I designed GPS Stratum 1 clock sources for 12 years, and that is how I > did > > > it. > > > > Note I have the patent on the techniques, so be sure to read the > patent > > > and do > > > > it differently (not hard to do), or license it from my former > employers. > > > > > > > > Austin > > > > > > > > Noddy wrote: > > > > > > > > > I suppose maybe I should've been a bit clearer. If I am correct in > > > saying, a > > > > > DDFS will generate digital values for a synthesised waveform, to be > used > > > as > > > > > input into a DAC. What I need is to generated a square wave output > at a > > > > > given frequency, using the 5MHz signal as a reference... ideally i > am > > > trying > > > > > to generate a 32MHz signal. > > > > > > > > > > Noddy > > > > > > > > > > > Noddy, > > > > > > > > > > > > Use a DDFS (direct digital frequency Synthesizer). > > > > > > > > > > > > Austin > > > > > > > > > > > > Noddy wrote: > > > > > > > > > > > > > Hi, > > > > > > > > > > > > > > I am trying to design a high precision (30 bit) frequency > > > synthesiser > > > > > inside > > > > > > > a Spartan II. Of course, normal way to do this is with a charge > > > pump, > > > > > > > voltage controlled oscillator and a phase lock loop. > > > > > > > > > > > > > > Can anyone point me to some good references? I have a very high > > > > > precision > > > > > > > 5Mhz which is generated from a hydrogen maser and will be used > as > > > the > > > > > input > > > > > > > clock signal. > > > > > > > > > > > > > > thanks > > > > > > > adrian > > > > > > > > > > > >Article: 42533
You're right....what I meant was a serial DAC, like the CS4334...someday, I might even get some sleep too... still looking at datasheets for the CPLD's, various types, Atmel, Xilinx, etc. Those puppies are complicated and I'm not getting it at the moment, so I'm probably going to have to find something much smaller to start out with. Of course I'd like to jump into the CPLD's up to my neck, but I'd be wasting my time... -- Jeremy D. Grotte www.geocities.com/Skimask87 "Jim Granville" <jim.granville@designtools.co.nz> wrote in message news:3CC85E64.1A4@designtools.co.nz... > Jeremy D. Grotte wrote: > > > > Cool. I really didn't expect any responses, much less a > > couple here and a half a dozen e-mails in one day... > > > > I did some thinking about the circuit, and I really don't > > need the latches. The circuit I've designed already has the > > latches, I just need a high speed method of controlling > > them. But on that same note, I am going to check out the > > T89C51SND1 chip. The only thing that chip doesn't have on > > it is an MP3 decoder, which is easily done by a VS1001K. > > ... actually, it does :-) ( you didn't say you needed one !) > > -jgArticle: 42535
1. We are working with Spartan II: XC2s50 device, with speed grade -5. While configuring it by Boundary Scan method, we used a chain of XC18V01 configuration PROM and the XC2s50 device. While initialising the chain, the FPGA device was detected as XC2v50, a Vertex family device, by the Webpack software. Is this a bug with the software? 2. While configuring the device using the Boundary Scan chain, the chain was not getting identified at all. We used the debug chain feature to float values on the TMS, and TCK pins. We tried to detect these voltages by a multimeter, and when the TMS pin was being monitored by the DMM probe, the chain initialization succeeded.. We are thinking the capacitance of the probe helped clean the TMS logic values. What could be the probable reason? We have built owr own Parallel cablle III. Thabks in advance.. Ajit OkeArticle: 42536
"Ajit Oke" <ajitoke@yahoo.com> schrieb im Newsbeitrag news:4eb6bec8.0204260805.5c305580@posting.google.com... > 1. > We are working with Spartan II: XC2s50 device, with speed grade -5. > While configuring it by Boundary Scan method, we used a chain of > XC18V01 configuration PROM and the XC2s50 device. > While initialising the chain, the FPGA device was detected as > XC2v50, a Vertex family device, by the Webpack software. > Is this a bug with the software? No, all is fine. Spartan-II is theh lowcost version of Virtex. > 2. > While configuring the device using the Boundary Scan chain, the chain > was not getting identified at all. We used the debug chain feature to > float values on the TMS, and TCK pins. We tried to detect these > voltages by a multimeter, and when the TMS pin was being monitored by > the DMM probe, the chain initialization succeeded.. We are thinking the > capacitance of the probe helped clean the TMS logic values. > What could be the probable reason? > We have built owr own Parallel cablle III. There are reports of glitching signals with old software. Do you have all the caps on your cable that are in the schematic? But on the other hand side, I build a JTAG cable with all those strange lowpass-filters, and all works fine. -- MfG FalkArticle: 42537
"Laurent Gauch" <laurent.gauch@amontec.com> schrieb im Newsbeitrag news:3CC96CCA.60708@amontec.com... > Hi, > > I'm using webpack 4.1, I want to know how can I generate .sdf and .vhd > output files for modelsim simulation? ???? Just go to the menu PROJECT -> New Source -> VHDL Testbench (or Testbench waveform, if you have installed HDL-Bencher) Create the testbench, then you see an option in the process view window for simulation press it, and Modelsim will start and do a 1us simulation. From there you can adjust all settigs/signals to you likings. -- MfG FalkArticle: 42538
"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag news:3CC8BCEA.89FC0A7@yahoo.com... > I am not clear about what the four clock resources are. Are you saying > that there are only four BUFGs in the Spartan II and they go hand in > hand with the DLLs? They do. Since the DLLS and BUFGs are very close together (with dedicated routing between them) you have very good control over timing. > Four clocks with clock enables is not the clean approach I would like. > I have a memory bus clock at 100 MHz, an MCU bus clock at 30.xxx MHz and > four IO clocks at independant rates from 8 kHz to 60 MHz set according > to the application which varies. Even if we use clock enables, that > requires the reclocking of the data and the IO clocks would need to be > distributed for the data reclocking. How would that be accommodated? > Is there a way to use conventional routing and keep the skew low for a > small number of clock inputs? How about this. Use a small asynchronous FIFO to synchronize all non-global clock datas to your fastest clock. In this case, the clock on non-clock lines must drive only a dozen clock inputs, which can be easyly constraint to a column. Use NET mynet uselowskewlines; in the UCF to force the P&R to do so. -- MfG FalkArticle: 42539
"Ajit Oke" <ajitoke@yahoo.com> wrote in message news:4eb6bec8.0204260805.5c305580@posting.google.com... > 1. > We are working with Spartan II: XC2s50 device, with speed grade -5. >FPGA device was detected as > XC2v50, a Vertex family device, by the Webpack software. > Is this a bug with the software? Virtex... No its a bug with the marketing. Both have the same idcode. > 2. > While configuring the device using the Boundary Scan chain, the chain > was not getting identified at all.> We have built owr own Parallel cablle III. > Thabks in advance.. > Ajit Oke If it read out the idcode it did a lot of stuff right. Most likely your cable is fine. If your downloading via jtag make sure 1) your mode pins are right and 2) start up clock is set to jtag and not cclk. Steve CasselmanArticle: 42540
In article <Ix7y8.92717$SR5.2345896@twister1.libero.it>, stefano.mora@antispam.libero.it says... > Thank you very much .. > > > They are both clocks, since everything with signalname'event is a clock. > > The problem is not that htey are clocks, the problem is, that you tried to > > playe one of these clock inputs to a general purpose IO. > > Right !! My mistake is the use of 'event attribute: i tried to detect falling > edge of a signal using a clock attribute ... now i'm changing my code > as follow: > > process(clock,p_strobe_n) > begin > if(clock'event and clock='1') then > if (p_strobe_n='0') then -- <=== Clock enable > byte <= p_data; > end if; > end if; > end process; Yes, p_strobe_n will now go one the clock enable of the D-FF. Hint: don't put any more than the CE signal in that if statement (that I marked as a clock enable). ---- KeithArticle: 42541
Hi, I have a board that uses the XC4005XL-TQ144 package. (plastic quad flat pack) I need to know whether this chip is in fact pin-compatible with the 4010XL device in the same package. I've been told contradictory things and can not find the appropriate information in the Xilinx documentation. Also, if anyone knows of a document that lists which packages are compatible with each other, I'd be quite interested. It seems bizarre to me that anybody would design a part to be compatible with another part, then not tell anybody about it. Thanks. JonArticle: 42542
It's not free, but it certainly is nice. I'm sure you can get trial license. http://www.concept.de/gv_index.html Tim wrote: > > I theory this is very straightforward, so I knocked together > a quick Windows program with the MS TreeView control. Really > amusing timing. The program could read and (sort of) parse a > multi-megabyte EDIF file in a few seconds, but the TreeView > took absolutely ages to build and draw. > > I guess Micro$oft designed their control to display a few hundred > files, not a million or so EDIF nodes. Then they delegated the > programming of the control to someone who slept through the data > structures class. > > Good luck with the hunt. Pls post if you find something. > > Gunther May wrote: > > Hello FPGA experts, > > > > does anybody know a freeware graphic EDIF viewer? > > > > Thank you very much, > > Gunther May > > > > -- / 7\'7 Paulo Dutra (paulo@xilinx.com) \ \ ` Xilinx hotline@xilinx.com / / 2100 Logic Drive http://www.xilinx.com \_\/.\ San Jose, California 95124-3450 USAArticle: 42543
Falk Brunner wrote:
>
> "Laurent Gauch" <laurent.gauch@amontec.com> schrieb im Newsbeitrag
> news:3CC96CCA.60708@amontec.com...
> > Hi,
> >
> > I'm using webpack 4.1, I want to know how can I generate .sdf and .vhd
> > output files for modelsim simulation?
>
> ????
> Just go to the menu
>
> PROJECT -> New Source
> -> VHDL Testbench (or Testbench waveform, if you have installed HDL-Bencher)
> Create the testbench, then you see an option in the process view window for
> simulation
> press it, and Modelsim will start and do a 1us simulation.
> From there you can adjust all settigs/signals to you likings.
>
> --
> MfG
> Falk
Falk, I think the original poster wants to do a post P&R
simulation, not an RTL simulation.
To do a post P&R simulation, the easiest way to do will be to register a
testbench file as a file related to the project (ISE WebPACK should
automatically resolve the hierarchy.), and select the testbench file in
"Sources in Project."
Then "Processes for Current Source" should give the user four simulation
options, and here the original poster will select "Post P&R simulation."
After synthesis and P&R, ISE WebPACK will automatically start ModelSim
XE-Starter. (I will assume the original poster is poor like me, and
using ModelSim XE-Starter.)
Note that when doing a post P&R simulation, ModelSim XE-Starter runs
reallllllly slooooooow, but I always do so before burning a
Configuration PROM.
If ModelSim XE-Starter doesn't respond for the first 20 minutes, that's
normal. (Takes awfully a lot of time in the beginning.)
ISE WebPACK 4.2 release note claims ModelSim XE-Starter 5.5e that comes
with ISE WebPACK 4.2 runs faster than ModelSim XE-Starter 5.5b that
comes with ISE WebPACK 4.1, and it actually seems like the newer one is
indeed faster, but I am not 100% positive about that because I didn't
time them.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 42544Click on http://www.xilinx.com/partinfo/ds006.pdf and look for the XC4000E/XL pin-out tables. You may have to print out two pages and do a visual compare... Sorry for the inconvenience, but my memory does not serve me well enough to give you a reliable answer. Peter Alfke ======================= Jon wrote: > Hi, > > I have a board that uses the XC4005XL-TQ144 package. (plastic quad flat > pack) I need to know whether this chip is in fact pin-compatible with > the 4010XL device in the same package. I've been told contradictory > things and can not find the appropriate information in the Xilinx > documentation. > > Also, if anyone knows of a document that lists which packages are > compatible with each other, I'd be quite interested. It seems bizarre > to me that anybody would design a part to be compatible with another > part, then not tell anybody about it. > > Thanks. > > JonArticle: 42545
Hi why do not use a dual port RAM instead a single port and enable the write port when you want to change the ROM pattern , through I/O it will be so easy to reload as soon as you want even in real time .... cheers -- Use our news server 'news.foorum.com' from anywhere. More details at: http://nnrpinfo.go.foorum.com/Article: 42546
Steffen Thieringer wrote: > > Hello newsgroup! > I am looking for a 8051 Core to implement in an Xilinx Spartan2 FPGA. > The task for it is a control of a sensorless brushless DC motor. > The software for the processor is already done but needs to be speeded up. > So i need pwm, capture/compare units, several timers ans so on... > I have several in my mind but not yet found 'the one'. Cygnal have just announced their 128KF, 100 MIPS C8051F, and also a 25 MIPS CAN bus model. Unlike a FPGA, these do not need separate loader memory / code memory chips. Both have many PWM modes, which you can augment with CPLD for complex drive - slave either as fast serial, or as XDATA. - jgArticle: 42547
In article <3CC85E64.1A4@designtools.co.nz>, jim.granville@designtools.co.nz wrote: >Jeremy D. Grotte wrote: >> >> Cool. I really didn't expect any responses, much less a >> couple here and a half a dozen e-mails in one day... >> >> I did some thinking about the circuit, and I really don't >> need the latches. The circuit I've designed already has the >> latches, I just need a high speed method of controlling >> them. But on that same note, I am going to check out the >> T89C51SND1 chip. The only thing that chip doesn't have on >> it is an MP3 decoder, which is easily done by a VS1001K. > >.... actually, it does :-) ( you didn't say you needed one !) > >-jg It does? Where can I buy/borrow/steal it from? I have a prototyping board with a SPARTAN 2 and I'd like to implement an MP3 decoder for it. Possibly even an MP3 encoder too, it it'll fit. LTArticle: 42548
Flip-flops tend to retain their names in synthesis, while synthesized
combinatorial logic does not. If you keep your logic to one level of logic
behind each flip-flop, you can just place the flip-flops and let the
auto-placer do the combinatorials with very consistent results. If you must
place the combinatorial logic (eg. luts), then you'll have to instantiate
LUTs in order to keep the names from changing. You can also put RLOCs on any
instantiated primitives or components that use primitives. For second level
logic, you can use area constraints if your design is hierarchical with
somewhat reasonable results.
Chris wrote:
> One possibility may be to put location constraints into the ucf file by
> hand. You can use your VHDL net names. For example:
>
> INST "/module/myff*" LOC=CLB_R11C5;
>
> Please look up the syntax of the location because it changes with the
> FPGA families. It is also possible to use RLOCs and other location
> constraints. And the use of wildcards is a nice option, which makes you
> more indepandant of the tools. FPGA Express renames all registers with
> "_reg". I don't know what XST does.
>
> This strategy does not work for combinatorical logic, though. Because you
> have to name the instance, and it's the task of the synthesizer to
> optimize the logic, so don't know the name. You can come around this
> problem when you instantiate LUT directly in you VHDL source code.
>
> The "assumed way" is to do the synthesis and then do iterations with the
> floorplanner, I think. But if you resynthesize you you have to redo your
> work. An application engineer will know this better than I do.
>
> Chris
>
> In <c3771dbf.0204230731.1fb51677@posting.google.com>
> rjshaw@iprimus.com.au (russell) wrote:
> >Hi,
> >
> >Trying to floorplan a hierarchial design done in XST VHDL,
> >i couldn't really get the hang of, because of the tedious
> >net names. Previous messages have mentioned that the net
> >names can change from just a slight modification in the
> >source code.
> >
> >There must have been an assumed way the tools were to be
> >used when the floor planner was being done. I'd guess one
> >assumption was that schematics were used atleast for the
> >top level of a hierarchial design.
> >
> >I was wondering, if i did all the various parts of the
> >hierarchy as schematic blocks, and just filled in the
> >simple blocks with vhdl such as state machines, counters,
> >filters etc, would the end result give an easy to interpret
> >netlist amenable to sane routing in the floor planner?
> >
> >After reading lots of C.A.F. messages, it seems the xilinx
> >floor-planning tools are a bit dated/broken/etc.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 42549
The DLLs work by delaying the clock input so that the delay, including the
delay through the clock distribution is equal to a period of the input
clock. The DLL has a state machine in it that dynamically selects the best
tap on a tapped delay line to accomplish that goal.
The length of the tapped delay line determines the lowest frequency that can
be supported by the DLL. The 25 MHz minimum frequency spec ensures that the
delay line is long enough under any legal voltage/temperature/process
condition with some margin.
rickman wrote:
> Austin,
>
> I think you need to read the original post more carefully. He is not
> working with a 1 MHz clock, it is an 11 MHz clock. The other clock is
> either 4 MHz or 4 GHz depending on if he is using the comma as a decimal
> point or as a thousands marker. I find that whole comma vs. period
> thing very confusing. How did we get to a state where half the
> technical world uses an opposite notation from the other half?
>
> But even if he is working with a 1 MHz clock, how does that eliminate
> the need for clock deskewing? If he has a minimum hold time that is not
> met without the clock deskewing, then he will need to use it.
>
> I think he was asking for a little more info on how DLLs work, what they
> accomplish and in which situations you would want to use them.
>
> I personally would like to understand SpartanII clocking better. I need
> six clocks in my design and I am not sure what pins to use to assure
> that they are routed using low skew paths inside the chip. Only two of
> these clocks need the DLLs for deskewing inside vs. outside the chip.
>
> Austin Lesea wrote:
> >
> > Pawel,
> >
> > Some answers, below.
> >
> > Austin
> >
> > "Paweł J. Rajda" wrote:
> >
> > > I am making a small (XC2S30) project and have a few questions:
> > >
> > > 1. DLL's
> > > Is the usage of DLLs obligatory or not? I am shifting data to the
> > > Spartan
> > > synchronously with external 4,096MHz clock. Another clock in my
> > > project
> > > is about 11MHz. Do such clocks need DLLs?
> >
> > No. They do not. DLLs deskew clocks for high speed applications
> > where even 100's of ps are important to keep track of. At 1 MHz,
> > deskew is not an issue, as the clock period is 1000 ns!
> >
> > >
> > > 2. I/Os
> > > I have to interface to 5V devices. Which I/O standard should I
> > > use: LVTTL
> > > or PCI_33_5? In what they differs (both are 5V tolerant)? Only in
> > > current
> > > sink/source capabilities?
> >
> > Run IBIS simualtions to choose the best IO standard.
> >
> > >
> > > 3. Configuration
> > > I will use Master Serial mode. What is the Preconfiguration
> > > Pull-ups option?
> > > Should I turn it on or off?
> >
> > One can have the IOs pull up while configuring, or not (remain
> > tristate).
> >
> > >
> > >
> > > --
> > > Regards,
> > > Pawel J. Rajda
> > >
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
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