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Noddy wrote: > > Hi, > > I am trying to design a high precision (30 bit) frequency synthesiser inside > a Spartan II. Of course, normal way to do this is with a charge pump, > voltage controlled oscillator and a phase lock loop. > > Can anyone point me to some good references? I have a very high precision > 5Mhz which is generated from a hydrogen maser and will be used as the input > clock signal. > > thanks > adrian I have read all of the posts up to this point and I am not sure you have an answer to your question. I think you have not indicated clearly to the other posters what your requirements are. You say that you need to generate a highly stable clock signal with mHz resolution over the range 31.5 to 32.5 MHz from a 5 MHz reference signal. You want to do it in a SpartanII with as few as possible external components. You have indicated that you want to do coherent signal averaging. Unfortunately since I don't know what this entails, I don't know how this impacts your clock requirements. So here are my comments. As others have indicated, you can use a DDS in an FPGA to generate a highly stable frequency to any resolution that you require without using external components. But this will require a reference clock that is a higher frequency (at least 2x) than your output signal. The generated signal will also have a relatively large jitter. So the question is, are you willing to use a PLL to generate your higher frequency reference signal? Also, can you tolerate the jitter (+- 1/2 high freq ref period)? There is another alternate solution that is different from any described so far. This one also requires external componenets, but it can be as simple as a single chip plus filter passives. The DDS uses an NCO (numerically controlled oscillator) to accumulate the phase angle and generate the output clock. If instead of just taking the high order bit you use the N MSBs to drive a DAC, you can generate a sinewave. The sinewave can be filtered to remove the alias components and clipped with a comparator to recover a square wave. The recovered square wave will have greatly reduced jitter (due to the filter). The filter can be a very narrow bandwidth due to your narrow freq range requirements. The real beauty of this is that you can get the DAC and comparator on a single chip from Analog Devices. Also, you may not need to generate a high freq reference since even if the DAC is clocked at 5 MHz, there will be a 32 MHz component which can be isolated from the other alias components by a good filter. :) So this may or may not be optimal for your needs, but it won't be overly complex and will only require a single external chip. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 42876
I wish to have a bus of pins into an FPGA. Some of the pins are not connected to any logic in the FPGA. It is important that the unused pins are not driven by the FPGA. Is there a way that I can reserve individual pins on the FPGA as inputs so that they are not optimised out of the desing by ISE??Article: 42877
On Mon, 06 May 2002 03:24:34 GMT, Peter Alfke <palfke@earthlink.net> wrote: >It's a bit tedious in words: >Put an external pull-up to 5 V on the pin. >Drive the output signal as usual. >Now comes the trick: > >Drive the output T signal ( Tristate active High) with an AND of the internal data >signal AND the input signal coming from your output. (Remember, any pin is always an >input) > >When you drive a Low output, the buffer is active (T is Low). >When you start driving a High output, the buffer remains active until the output pin >is crossing the threshold. Then the AND goes true, and the output goes 3-state. >That means you got an active (<10 Ohm) output helping you on the way up. >Obviously, it is in your interest to delay the input signal from reaching the AND >gate too soon. > >You cannot get any help >3.3 V, but you may get a much faster rise time for the >first 2 to 2.5 V, and that reduces the rising delay significantly. > >The falling delay is short anyway. > >Peter Alfke, Xilinx Applications >============================ Peter, thanks; we'll keep that in mind. I guess you know the 'Shannon's Circuit' PECL driver trick: pull the signal up at the PECL load with a line-matched terminator to Vh = 4.2 volts maybe; FPGA tristate open becomes PECL high. To make a low, enable the tristate output and make a TTL high, which will be 3.3 volts = PECL low. This is very fast. The gotcha is that the FPGA 3.3 volt supply may have to *sink* current if you do this a lot. The other direction, PECL to FPGA, is not as nice. JohnArticle: 42878
Hi Martin, Extremely sorry!!!! The values indeed are from 2 to 32 and you need to use externally generated clocking as you said. Regards, SANKET. "Martin E." <0_0_0_0_@pacbell.net> wrote in message news:<yahB8.723$lK6.72949872@newssvr14.news.prodigy.com>... > "Xilinx FAE from Insight SANKET" <sanket@insight.memec.co.in> wrote in > message news:84bd8d50.0205050105.536b90a0@posting.google.com... > > > One more thing---Once upon a time even you were a JUNIOR and were > > given a chance and so you are here. > > Just to clarify, the term "junior" was not used as a pejorative at all. The > bottome line is that I need current information because it affects > electrical design. I am new to FPGA's myself, so you could call me a > "junior" in that regard just as well ... and that's the more reason to > obtain accurate information. The data sheet I got off the Xilinx site, > document DS031-2 (v1.3) dated January 25, 2001, calls out a range of 1 to > 4095 for M and D. If this is not true, and the range is 2 to 32, I will > have to use externally generated clocking. Being that the board goes to > layout next week ... > > Thanks for your input.Article: 42879
For heavens sake, even Icarus Verilog supports that. It is very easy for a synthesizer to write out wide gates as carry chain logic. The tool needs a Virtex aware netlist generator, but not a Virtex aware synthesizer. I would be astonished if xst and/or FPGA Express does not make wide gates with carry logic. news.bellatlantic.net wrote: > Do any of the tools (either the synthesis or mapping stages) support this, > or do you have to create instantiations yourself? > > "Peter Alfke" <palfke@earthlink.net> wrote in message > news:3CCB9127.D10CAD92@earthlink.net... > >>Any one LUT takes 4 inputs (any function you want). >>You can then concatenate LUTs through the carry chain at no extra cost in >>area, and about 30 ps additional delay per LUT used. >> -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." abuse@xo.com uce@ftc.govArticle: 42880
Sorry, meant to write 32.000000031 MHz... > Noddy wrote: > > > > I just need a conversion from 5Mhz to an adjustable frequency ratio which > > will always be between 31.5 and 32.5 MHz. When I say mHz resolution, I mean > > I need to be able to set my 32 MHz frequency down to mHz accuracy ie. > > 32.031 Mhz, and of course there should be no jitter at this level of > > accuracy. > > What you have written here, has 1 KHz LSB. > When you write mHz, and MHz, most readers assume > MilliHertz (32031000.001Hz ), and MegaHertz (32MHz) > Digital solutions, by nature, are quantized, so must have jitter. > > For 32MHz / 1KHz LSB, a 74HC4046 or derivatives should be a good > starting point. > > -jgArticle: 42881
This is a multi-part message in MIME format. --------------3EAD866CF7681BC3EC51DB3A Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi Shane, One way would be to use the following statement in the ucf file, CONFIG PROHIBIT = "Pin Number" ; where "Pin Number" is the device specific pin. This will prohibit PAR from using this IO pin, reserving it for later use. Stephan Shane wrote: > I wish to have a bus of pins into an FPGA. Some of the pins are not connected to any logic in the FPGA. It is important that the unused pins are not driven by the FPGA. Is there a way that I can reserve individual pins on the FPGA as inputs so that they are not optimised out of the desing by ISE??Article: 42882
Hi, We are developing a PCI system based on Spartan II 208 pin PQFP devices. For this we are busy licensing the PCI core but need to finalise our schematic designs and hence need some information on the pre-allocated PCI pin numbers to use for the 32 bit/33 Mhz PCI core using this device. Thanks Anthony.Article: 42883
This is a multi-part message in MIME format. --------------043EDFB6861D78C6A577EA1C Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi Anthony, If you let me know what device you are targetting I can send you the pinouts for that particular device. Cheers, Stephan Anthony Ellis wrote: > Hi, > > We are developing a PCI system based on Spartan II 208 pin PQFP devices. For > this we are busy licensing the PCI core but need to finalise our schematic > designs and hence need some information on the pre-allocated PCI pin numbers > to use for the 32 bit/33 Mhz PCI core using this device. > > Thanks Anthony.Article: 42884
Hi,
I would like to know, which are the most caracteristic areas and
applications where SOPC solutions are developed in the current
market.Could anybody give me some information about it?
Thanks a lot,
Itsaso Zuazua
Article: 42885rjshaw@iprimus.com.au (russell) wrote in message news:<c3771dbf.0205050315.4f6990cd@posting.google.com>... > cavallino-rampante@mschumacher.com (Sumeet) wrote in message news:<67b681bf.0205042236.53df06f1@posting.google.com>... > > i have a doubt about the way the XST synthesis tool will intrepret the > > following code for a state machine : > > > > ( please ignore any syntax errors, the construction is more important) > > > > ....... > > --signal declarations > > > > process(......sensitivity list....) > > > > begin > > > > -- default signal assignment > > > > signal_1 <= '0'; > > signal_2 <= '1'; > > signal_3 <= '0'; > > > > -- conditional signal assignment > > --not all signals assigned in each state > > > > case curr_state is > > > > when state_1 => > > signal_1 <= '1'; > > next_state <= state_2; > > > > when state_2 => > > signal_3 <= '1'; > > next_state <= state_3; > > > > when state_3 => > > signal_3 <= '0'; > > next_state <= state_1; > > end case; > > > > end; > > > > well, the code is not for anything in particular, what i wanted to > > know was, since all signals are given "default" values, am i allowed > > to do something like what is done above, and not assign each output in > > each state, assuming that it will get its default value? > > > > This works in leo-spec, but will it also work in webpack4.2 ? > > > > we are using spartan2 xc2s50, by the way. > > > > thanks in anticipation > > --Sumeet > > I've done that for leonardo, but haven't run it in > webpack yet. I've seen them say in books that just > having defaults before the case statement is adequate. > It is all procedural in a process statement, so > should be ok. As a side comment, default statements like the above have not worked for me with the Verilog compiler that comes with MaxPlus v10.1 :(. I have seen the default style documented in Verilog books, and the style lends itself to a more terse style IMHO. I have not seen a problem with "default" style using Synplicity or FPGA Express synthesizers. Newman NewmanArticle: 42886
Tsoi Kuen Hung <khtsoi@cse.cuhk.edu.hk> wrote in message news:<aavl6i$8ea$2@eng-ser1.erg.cuhk.edu.hk>... > Hi - may be this is a another question. I want to know how you create your > hard macro. I have a component with only primitives and fully RLOCed in VHDL. > also, a netlist is generated from these codes. is there a way to reduce the > time to create the hard macro by using these information? Thanks in advance. > ---- Brittle > > btw: I am working on XCV1000E chip and it take me 20 hrs. to finish a design. > how many logics are there in your week long design? Answer Record #10901 in the Xilinx Answer Database gives a step-by-step on creating a hard macro using FGPA Editor. But, as I have stated, this doesn't work if there are VCCs or GNDs in the design. I am going to attempt to use XDL to create my hard macro, since FPGA Editor seems to be a lost cause. If anyone has any advice, I'm all ears. Thanks, JeffArticle: 42887
Peter, Thanks for the help. One more question. What's the range of value the pullup you recommend for that circuit? I was thinking about 10K would be sufficient. Thanks again. LT In article <3CD5F763.8BF179E5@earthlink.net>, palfke@earthlink.net wrote: >It's a bit tedious in words: >Put an external pull-up to 5 V on the pin. >Drive the output signal as usual. >Now comes the trick: > >Drive the output T signal ( Tristate active High) with an AND of the internal > data >signal AND the input signal coming from your output. (Remember, any pin is > always an >input) > >When you drive a Low output, the buffer is active (T is Low). >When you start driving a High output, the buffer remains active until the > output pin >is crossing the threshold. Then the AND goes true, and the output goes 3-state. >That means you got an active (<10 Ohm) output helping you on the way up. >Obviously, it is in your interest to delay the input signal from reaching the > AND >gate too soon. > >You cannot get any help >3.3 V, but you may get a much faster rise time for the >first 2 to 2.5 V, and that reduces the rising delay significantly. > >The falling delay is short anyway. > >Peter Alfke, Xilinx ApplicationsArticle: 42888
On Sun, 5 May 2002 21:35:02 +0200, "Noddy" <g9731642@campus.ru.ac.za> wrote: >I just need a conversion from 5Mhz to an adjustable frequency ratio which >will always be between 31.5 and 32.5 MHz. When I say mHz resolution, I mean >I need to be able to set my 32 MHz frequency down to mHz accuracy ie. >32.031 Mhz, That would be kHz resolution, six orders of magnitude easier. Or did you mean 32.031234567 MHz? - BrianArticle: 42889
Jeff wrote: > > Tsoi Kuen Hung <khtsoi@cse.cuhk.edu.hk> wrote in message news:<aavl6i$8ea$2@eng-ser1.erg.cuhk.edu.hk>... > > Hi - may be this is a another question. I want to know how you create your > > hard macro. I have a component with only primitives and fully RLOCed in VHDL. > > also, a netlist is generated from these codes. is there a way to reduce the > > time to create the hard macro by using these information? Thanks in advance. > > ---- Brittle > > > > btw: I am working on XCV1000E chip and it take me 20 hrs. to finish a design. > > how many logics are there in your week long design? > > Answer Record #10901 in the Xilinx Answer Database gives a > step-by-step on creating a hard macro using FGPA Editor. But, as I > have stated, this doesn't work if there are VCCs or GNDs in the > design. What are VCCs and GNDs in vhdl? Is that when a variable is set to a constant of '1' or '0'? > I am going to attempt to use XDL to create my hard macro, since FPGA > Editor seems to be a lost cause. If anyone has any advice, I'm all > ears. > > Thanks, > > JeffArticle: 42890
This is a multi-part message in MIME format. --------------3B68FD1000E28D0251586C40 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi Russel, Any signal that does not change state and is not optimised out by the tools will be implemented as Vcc or Gnd. Russell wrote: > Jeff wrote: > > > > Tsoi Kuen Hung <khtsoi@cse.cuhk.edu.hk> wrote in message news:<aavl6i$8ea$2@eng-ser1.erg.cuhk.edu.hk>... > > > Hi - may be this is a another question. I want to know how you create your > > > hard macro. I have a component with only primitives and fully RLOCed in VHDL. > > > also, a netlist is generated from these codes. is there a way to reduce the > > > time to create the hard macro by using these information? Thanks in advance. > > > ---- Brittle > > > > > > btw: I am working on XCV1000E chip and it take me 20 hrs. to finish a design. > > > how many logics are there in your week long design? > > > > Answer Record #10901 in the Xilinx Answer Database gives a > > step-by-step on creating a hard macro using FGPA Editor. But, as I > > have stated, this doesn't work if there are VCCs or GNDs in the > > design. > > What are VCCs and GNDs in vhdl? Is that when a variable is set > to a constant of '1' or '0'? > > > I am going to attempt to use XDL to create my hard macro, since FPGA > > Editor seems to be a lost cause. If anyone has any advice, I'm all > > ears. > > > > Thanks, > > > > JeffArticle: 42891
10k would give you a very slow final rise to 5 V. 470 Ohm to 1 kilohm is much better, limited by the output sink capability. Peter Alfke ================== Loi Tran wrote: > Peter, > > Thanks for the help. One more question. What's the range of value the pullup > you recommend for that circuit? I was thinking about 10K would be sufficient. > > Thanks again. > > LT > > In article <3CD5F763.8BF179E5@earthlink.net>, palfke@earthlink.net wrote: > >It's a bit tedious in words: > >Put an external pull-up to 5 V on the pin. > >Drive the output signal as usual. > >Now comes the trick: > > > >Drive the output T signal ( Tristate active High) with an AND of the internal > > data > >signal AND the input signal coming from your output. (Remember, any pin is > > always an > >input) > > > >When you drive a Low output, the buffer is active (T is Low). > >When you start driving a High output, the buffer remains active until the > > output pin > >is crossing the threshold. Then the AND goes true, and the output goes 3-state. > >That means you got an active (<10 Ohm) output helping you on the way up. > >Obviously, it is in your interest to delay the input signal from reaching the > > AND > >gate too soon. > > > >You cannot get any help >3.3 V, but you may get a much faster rise time for the > >first 2 to 2.5 V, and that reduces the rising delay significantly. > > > >The falling delay is short anyway. > > > >Peter Alfke, Xilinx ApplicationsArticle: 42892
hi, You need to map the simulation libraries in the modelsim directory to your work library. Do the following in modelsim: vmap lpm <work library> vmap altera_mf<work library> This should fix it. bye, Prashant shenyun78@sohu.com (strong) wrote in message news:<8fb33227.0205050404.22acd6ad@posting.google.com>... > I use Altera's LPM in my project,and I want to stimulate it by > modelsim, > but I do not know how to do because modelsim can not interpret the > LPM?please help me,thanks.Article: 42893
Shane <shane.bentley@cisra.canon.com.au> wrote in message news:<ee76524.-1@WebX.sUN8CHnE>... > I wish to have a bus of pins into an FPGA. Some of the pins are not connected to any logic in the FPGA. It is important that the unused pins are not driven by the FPGA. Is there a way that I can reserve individual pins on the FPGA as inputs so that they are not optimised out of the desing by ISE?? Hi Shane! First you can constrain your Bus signals to dedicated pins. Therefore put the following in the User Constraint File: NET "<SignalName>" LOC = "<PinName>"; For instance: NET "DATAIN03" LOC = "P187"; (Pin name from a Virtex-E device) Unfortunately this seems not to prevent the mapper from optimizing your inputs away if you don't use them internally. What I've done in the past is putting some dummy logic on those unused inputs so that the mapper couldn't recognize them as "useless" anymore. As you can see I'm not a real expert yet as this solution is not very elegant. So who knows a more sophisticated way? As you already might know unconfigured/unused user I/O pins are switched to high impedance by default (at least in virtex devices) and thus not driven by the FPGA. Regards, StephanArticle: 42894
Jeff <jeff@Despammed_Domain.com> wrote: > Answer Record #10901 in the Xilinx Answer Database gives a > step-by-step on creating a hard macro using FGPA Editor. But, as I > have stated, this doesn't work if there are VCCs or GNDs in the > design. Thanks for your hints. I just notice that I cannot follow the steps since there will be both VCC/GND and TBUF route in the macro. It seams that the tools are still a way from perfect even provided by the venders themselves. Anyway, thanks for the info. My problem is just about a finished project. ---- BrittleArticle: 42895
On Mon, 06 May 2002 03:24:34 GMT, Peter Alfke <palfke@earthlink.net> wrote: > >You cannot get any help >3.3 V, but you may get a much faster rise time for the >first 2 to 2.5 V, and that reduces the rising delay significantly. > What might really be interesting would be to add a small series inductor. With mainly capacitive loading, the initial rising edge can theoretically overshoot to twice the FPGA supply voltage, at which time the tristate could be switched off, leaving the line high. In real life, this could probably extend your trick another volt or so. JohnArticle: 42896
Jay, Please send me the entire design archive as the .zip file. (austin@xilinx.com) I will send it to the software person to look into this. You should be able to use 2GB for this part (we do here in the FPGA Lab). Austin Lesea, Manager FPGA Lab Jay wrote: > It appears that on a fully utilized XC2V6000, there is no solution to > be able to run the FPGA Editor. The program hits the 2GB memory limit > and quits. How did Xilinx test there code? I know that the memory > limit is imposed by Microsoft, and it is what it is, and there is no > changing that any time soon. So why can't Xilinx recode to use the > available memory space more efficiently or store data on the HD so at > least I can run (albeit more slowly). > > And another thing, guess I can accept waiting 30 minutes to load a > database into a tool, but it seems crazy to have to wait another 30 > minutes to exit without even saving just to get my memory back.Article: 42897
"Noddy" <g9731642@campus.ru.ac.za> schrieb im Newsbeitrag news:1020627016.36637@turtle.ru.ac.za... > I just need a conversion from 5Mhz to an adjustable frequency ratio which ^^^^^^^^^^^^ I wouldn call this "just". Anyway, in this case, you need the DDS (for high resolution) and a analog cleanup PLL with a very narrow loop bandwidth. Use the plain 5 Mhz maser signal as the clock for you DDS. This gives you output frequencyies up to 2.5 MHz, lets say only 2 MHz with almost any arbitrary resolution (even microHertz if you want). Then use a PLL to multiply this frequncy by 20. So you need to adjust your DDS output frequency in the range of 31 MHZ/20 = 1.55 MHz. -- MfG FalkArticle: 42898
Hi, While going through appnotes, I see that clock to the BRAM is always sent through a clk buffer. Why is this? In my case I only have one clock that goes to block ram as well as rest of the logic. And synplify, correctly identifies that as a system clock and uses global clock lines to route that clock. I am assuming, that in this case I will not necessarily have to route the clock to the bram via clk buffer. I would appreciate your feedback. Thanks. -sanjayArticle: 42899
I will be interested to know the pin outs of Virtex FG256, and
FG680 package, Spartan-II FG256 and FG456 package, Virtex-E BG432,
FG256, FG676, and FG680 package, Spartan-IIE PQ208 and FG456 package,
and Virtex-II FG456 package.
Remove "ihatespam99" twice when replying.
Kevin Brace
Stephan Neuhold wrote:
>
> Hi Anthony,
>
> If you let me know what device you are targetting I can send you the pinouts for
> that particular device.
>
> Cheers,
> Stephan
>
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