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"Thomas" wrote: > I am a complete Newbie to FPGA´s, but now i must work with them. > I have a Spartan II Demo Board (Insight) with XC2S100 FPGA and > want to use ISE Webpack for programming it. I have searched > for documentations, tutorials but have not found yet any good results. > Does anyone have suggestions where to find good eplainations using ISE Webpack??? Why not using the Tutorials delivered with the ISE Webpack? Under Help->Ise Help Contents->Ise FPGA WebPack ISE->Tutorials->VHDL I found everything i needed to Work with the ISE Webpack. HolgerArticle: 44401
> Hi ALL, > > Its me again, first I want to thank earlier contributors to my subject. > I am still looking for more comments before I take the plunge. > So far I have seen XESS, TRENZ, BURCH etc > Europian boards cost 2X more for less fns. > > Anyway I am still undecided! > > Cheers Have you checked the CESYS boards ? http://www.cesys.com/english/ebene2/producto.htm Prices start from 329 Euro -ManfredArticle: 44402
I am pretty sure the ATA-5 still uses 5v, although it may limit the signal excursions
to 3.3v. The cable requirements are for the higher modes (don't remember which one it
starts on). Basically, there is a length restriction and it requires every other
conductor to be a ground. If you are using strictly a UDMA100 drive, you can design
to that interface, but if you need backwards compatibility you need to be able to
accept 5v signalling.
I think getting an IBIS model for the interface is the stuff of fairy tales. There
are too many variations between manufacturers and installations, although if it is a
strictly UDMA100 installation it will be a lot more consistent.
Rick Filipkiewicz wrote:
> Ray Andraka wrote:
>
>
> I think that for IDE drives supporting UDMA100 (ATA mode 5) the IO supply and
> signalling are supposed to be 3.3V and there are some heavy requirements on the
> cable & connector for modes > 2. Any IBIS modelling might have to take the ribbon
> cable into account if the disk is not being directly mounted on the PCB with a
> right-angled socket.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44403Block ram is not intended to be the same as a RAM chip. There is no tri state buffer on the output. If you want to connect it to a bus, you need to add the tri state buffer or use a mux. Do you know how to do that in an HDL? Nagaraj wrote: > > Its good that I learnt some more features of BlockRAM (I am new to > this). Thanx Peter. > Still I have some questions. Suppose the data output of one of the > dual ports > which I am using as read port is directly connected to the data bus of > the system. Then, FPGA should put data onto the databus only when the > system master selects the FPGA device AND gives the read clock. But as > I see in the dual port BlockRAM module, whenever there is a clock, > data is read and put onto the port unconditionally (may create clashes > on system databus). Eventhough controlling the "read address latching" > is possible, controlling the "read operation" is not possible. > Is the above argument correct? If so, Could you please tell me what > to do in such cases (reading conditionally)? > > Peter Alfke <palfke@earthlink.net> wrote in message news:<3D0F5456.26153CA8@earthlink.net>... > > This is a fundamental misunderstanding. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 44404
Not trying to start an argument. But I have read that IDE is not used in the specs anywhere and ATA has been the sole name for quite a while. To quote your reference. "Most companies now call the interface by its proper name: ATA or ATAPI" IDE is still used a lot, but mostly by consumers and marketing. All the specs use ATA. Davis Moore wrote: > > rickman wrote: > > > ATA is correct. In fact I have been told that IDE is not really the > > correct name anymore and it sould ONLY be called ATA. > > > > Historically IDE and ATA meant the same thing. > Perhaps the industry is moving towards a preference. > > A brief history on ATA/IDE interface: > http://www.ata-atapi.com/hist.htm > > -- > Davis Moore > Software Engineer -- PLP Implementation Tools > Xilinx, Inc. davism@NO_SPAMxilinx.com -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 44405
homework on the 19 of June!!! anyhow , want to tell pipe-line architecture -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 44406
Hi guysm Any idea why I get the error at the last line? Behavioral simulation & XST mapping, routing etc. all execute/complete correctly but now I am trying to functionally simulate the gate-level. Note this error also appears when one merely tries to simulate the "simprim.x_tri_v". Thanks Anthony # Loading C:/DesignTools/ModelSim/win32pe/../std.standard # Loading C:/DesignTools/ModelSim/win32pe/../ieee.std_logic_1164(body) # Loading C:/DesignTools/ModelSim/win32pe/../ieee.numeric_std(body) # Loading C:/DesignTools/ModelSim/win32pe/../std.textio(body) # Loading C:/DesignTools/ModelSim/win32pe/../ieee.vital_timing(body) # Loading C:/DesignTools/Xilinx_Simulation_Libraries/simprim.vcomponents # Loading C:/DesignTools/ModelSim/win32pe/../ieee.vital_primitives(body) # Loading C:/DesignTools/Xilinx_Simulation_Libraries/simprim.vpackage(body) # Loading C:/Projects/DAU30/ARINC_FPGA/Ver_xx/WORK.top_level_tb(struct) # Loading C:/DesignTools/ModelSim/win32pe/../ieee.std_logic_arith(body) # Loading C:/DesignTools/ModelSim/win32pe/../ieee.std_logic_unsigned(body) # Loading C:/Projects/DAU30/ARINC_FPGA/Ver_xx/WORK.top_level(structure) # Loading C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_zero(x_zero_v) # Loading C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_lut4(x_lut4_v) # Loading C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_lut3(x_lut3_v) # Loading C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_lut2(x_lut2_v) # Loading C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_mux2(x_mux2_v) # Loading C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_ff(x_ff_v) # Loading C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_sff(x_sff_v) # Loading C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_inv(x_inv_v) # Loading C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_one(x_one_v) # Loading C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_buf(x_buf_v) # Loading C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_tri(x_tri_v) # ** Fatal: (vsim-3420) Array sizes do not match. Left is 8. Right is 4231879. # Time: 0 ns Iteration: 0 Region: /top_level_tb/m_top_level/c_trdy_n_obuftArticle: 44407
When I try to use Webpack (Release 4.2WP2.x) under Win98SE on one of the sample programs I get the following error: Starting: 'D:/xilinx_webpack/bin/nt/xst.exe -ifn jc.xst -ofn jc.syr ' fatal error(0031): A device attached to the system is not functioning. Unable to run the process due to a system error. Done: failed with exit code: 0031. I haven't used it for some time. I'm not even sure if I've actually used this version before. I can't find anything about this on the Xilinx web site. Can anyone help? Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_heller Low-cost Altera Flex design kit: http://www.leonheller.comArticle: 44408
Any experience/opinions on ATMEL CPLD development? After struggling with CYPRESS and XILINIX, it looks like my present choice is ATMEL. I am trying to work thru one of their local representatives. He seems to be OK.Article: 44409
hi, i am in need of a uart code for my project. please anybody help me fast. harshaArticle: 44410
Did somebody managed to load a xilinx .bit fiel for spartan-2 devices via the jtag port. Xilinx has the xsvf file format, but the supplied file to load this contains a lot of overhead and uses too much RAM for small embedded systems, so I want to just to put the tap in the config state and shift the bit file in. But after comparing the bitfile with a generated svf file it seems that the data in the svf file is different. Any experience here ? MarcelArticle: 44411
You seem to be looking for a 3-state control on the BlockRAM data output. This does not exist. The data output is always active. If you connect to an off-chip data bus, use the 3-state option in the IOB. If you drive an internal bus, use a 3-state driver or a mux. Peter Alfke, Xilinx Applications Nagaraj wrote: > Its good that I learnt some more features of BlockRAM (I am new to > this). Thanx Peter. > Still I have some questions. Suppose the data output of one of the > dual ports > which I am using as read port is directly connected to the data bus of > the system. Then, FPGA should put data onto the databus only when the > system master selects the FPGA device AND gives the read clock. But as > I see in the dual port BlockRAM module, whenever there is a clock, > data is read and put onto the port unconditionally (may create clashes > on system databus). Eventhough controlling the "read address latching" > is possible, controlling the "read operation" is not possible. > Is the above argument correct? If so, Could you please tell me what > to do in such cases (reading conditionally)? > > Peter Alfke <palfke@earthlink.net> wrote in message news:<3D0F5456.26153CA8@earthlink.net>... > > This is a fundamental misunderstanding.Article: 44412
"Nicholas Weaver" <nweaver@CSUA.Berkeley.EDU> schrieb im Newsbeitrag news:aeq9vj$17mj$1@agate.berkeley.edu... > In article <5e39bc74.0206190753.44360369@posting.google.com>, > harsha <harsha_kondajji@rediffmail.com> wrote: > >hi, > >i am in need of a uart code for my project. > > > >please anybody help me fast. www.opencores.org -- MfG FalkArticle: 44413
hard&software&downloads? try this site -- http://www.skyworld.beArticle: 44414
"Marcel" <marcelgl@hatespam.xs4all.nl> schrieb im Newsbeitrag news:3d10aa88$0$52042$e4fe514c@dreader3.news.xs4all.nl... > Did somebody managed to load a xilinx .bit fiel for spartan-2 devices via > the jtag port. Sure, via the JTAG-progammer (now called IMPACT) > Xilinx has the xsvf file format, but the supplied file to load this contains > a lot of overhead and uses too much RAM for small embedded systems, so I > want to just to put the tap in the config state and shift the bit file in. Do you really want to load the FPGA via JTAG? For this purpose, Serial Slave mode is MUCH more appropriate. You only need to clock in the data sequentially and you are done. If you try to configure a FPGA via JTAG, you need to process the JTAG protocoll, which has much overhead. > But after comparing the bitfile with a generated svf file it seems that the > data in the svf file is different. Sure, these are very different files. -- MfG FalkArticle: 44415
In article <aeqc93$9568o$1@ID-84877.news.dfncis.de>, Falk Brunner <Falk.Brunner@gmx.de> wrote: >www.opencores.org B'ah, at least MY response would have forced him to do a little work on his class project. :) -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 44416
DAVID WRIGHT wrote: > > Any experience/opinions on ATMEL CPLD development? > > After struggling with CYPRESS and XILINIX, it looks like my present choice > is ATMEL. I am trying to work thru one of their local representatives. He > seems to be OK. That Atmel people are good folks. Sometimes the company can't seem to figure out how to help you, but they usually come through once you get in touch with your local people. What problems do you have with Xilinx and Cypress? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 44417
answered in the Xilinx General Forum... PatrickArticle: 44418
I am looking at a new machine as well. I would like to get an idea of what a faster P3 would do in your tests. Any chance you can run your PAR on a faster P3 or even a laptop? I believe they had P3s running at 1.3 GHz before they released the P4. It would be very instructive to see how that compares to the current P4s. Mark wrote: > > Hello, > > From a single recent very unofficial PC performance comparison .... > > Target: Virtex II XC2V6000 > Xilinx: ngdbuild, map, par, trce using Design Manager. 4.1i, sp3 > > PC A: 650 MHz Pentium III, 1GB PC100 > Execution time: ~1 hr: 30 min (+/- 5 min) > > PC B: 2.4 GHz Pentium IV, 2 GB PC2100 > Execution time: 40 min > > Caveate: This is only one comparison of a single run on each computer. > Most of the time (A: 1hr, 11 min B: 35 min) was spent in par, where the CPU > utilization was 100%, according to NT 4.0, sp6 task manager. par execution > time ratio: 71/35 ~= 2.03. Memory speed ratio: 266/100 ~= 2.66. CPU speed > ratio: 2400/650 ~= 3.69. Although CPU utilization was 100%, the execution time > ratio seems to imply that memory bandwidth was the limiting factor. But, the > CPU was not <100%, so it's unclear why the execution time was not shorter. > (IOW, I don't know what else the CPU was doing.) Screen saver, virus scanner, > email, etc. were off. > > I've heard several times that FPGA tools are CPU intensive, but I think that > machine specification should consider factors in addition to CPU speed, e.g., > memory bandwidth, size of memory (to hold database), and M/B/chipset. We also > considered a dual-CPU M/B. Unfortunately, no tools, that we have, can take > advantage of multiprocessor PCs. A multiprocessor PC, in our case, would allow > us to do synthesis/simulation, while the Xilinx tools are running. (I've tried > to script the flow, but cannot since we're using ChipScope.) > > I believe that Xilinx on Linux needs Wine (from Xilinx installation notes), > which I "heard" elsewhere ends up being slightly slower than native code. For > front-end tools, we use the Mentor tools, which I believe have been ported to > Linux, but, I haven't tried any, yet.... (I've been hoping ISD Mag will do > another "annual" comparison.) Microsoft and Linux seem close as fas as speed, > but, Linux seems to be ahead wrt stability. > > I haven't used Altera since the Flex 10K and MaxPlusII, so I don't have any > experience with the latest Altera FPGAs. I also have no experience with the > Xeon CPUs. > > Hope this helps, > Mark > > mac teh knife wrote: > > > We have started development using the new fpgas. We are evaluating the > > virtex 2 and stratix devices. > > What I'm finding out is my 2 year old machine ain't got what it takes to > > crunch the files that can fill up > > these multi million gate chips. I was wondering if anybody would care to > > share with us the machine (PC) > > they are using. Also has anybody evaluated linux vs window performance as > > far as fpga applications are concerned. > > > > I'm looking at a P4 2.4ghz / 2 gig ram and 533 mhz front bus. I'm also > > looking at a Xeon 2.4 g with 400 mhz > > front bus. Does anybody know if there is a performance difference between > > these two type of processors? > > > > Mac the knife is of course not my real name, I'm just so tired of spam that > > posting to use net generates. > > > > thanks > > Jerry -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 44419
For thermal management please see: http://support.xilinx.com/publications/products/packaging/xapp415.pdf Xilinx does not have a list of recommended heat sinks to use with virtex devices. Please refer to the 1999 Databook under Packages and Thermal Characteristics page 12->14 for third party heat sink vendors mand heat management resources. http://www.support.xilinx.com/partinfo/pkgs_pdf/pkgs1.pdf PatrickArticle: 44420
In article <3D10BA33.BBB6983B@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >I am looking at a new machine as well. I would like to get an idea of >what a faster P3 would do in your tests. Any chance you can run your >PAR on a faster P3 or even a laptop? I believe they had P3s running at >1.3 GHz before they released the P4. It would be very instructive to >see how that compares to the current P4s. I'd definatly look at the Athlons as well. Although I don't have the numbers to back them up, my intuition is that the tools are memory and cache bound as much as CPU bound, and the athlons have a much better cache heirarchy. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 44421
Via Impact I know, but I don`t know if Impact alteres the bitfile before sending. I know that jtag has much more overhead, but I`m stuck with the hardware design now, so no way to change to slave serial mode :-( "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:aeqc95$9568o$2@ID-84877.news.dfncis.de... > "Marcel" <marcelgl@hatespam.xs4all.nl> schrieb im Newsbeitrag > news:3d10aa88$0$52042$e4fe514c@dreader3.news.xs4all.nl... > > Did somebody managed to load a xilinx .bit fiel for spartan-2 devices via > > the jtag port. > > Sure, via the JTAG-progammer (now called IMPACT) > > > Xilinx has the xsvf file format, but the supplied file to load this > contains > > a lot of overhead and uses too much RAM for small embedded systems, so I > > want to just to put the tap in the config state and shift the bit file in. > > Do you really want to load the FPGA via JTAG? For this purpose, Serial Slave > mode is MUCH more appropriate. You only need to clock in the data > sequentially and you are done. If you try to configure a FPGA via JTAG, you > need to process the JTAG protocoll, which has much overhead. > > > But after comparing the bitfile with a generated svf file it seems that > the > > data in the svf file is different. > > Sure, these are very different files. > > -- > MfG > Falk > > > >Article: 44422
I have a 18 bits barrel shifter to design , it is speed oriented I will use a virtexII multiplier to shift the datas The 18x18 option is signed which means only 17x17 can be done Does anybody has an idea to built up a 18 bits barrel shifter with a 17+sign bits multiplier ? thanks -- Use our news server 'news.foorum.com' from anywhere. More details at: http://nnrpinfo.go.foorum.com/Article: 44423
"Marcel" <marcelgl@hatespam.xs4all.nl> schrieb im Newsbeitrag news:3d10c058$0$3877$e4fe514c@dreader4.news.xs4all.nl... > Via Impact I know, but I don`t know if Impact alteres the bitfile before > sending. I know that jtag has much more overhead, but I`m stuck with the > hardware design now, so no way to change to slave serial mode :-( Hmm. So you may consider using the xapp58 (which contains the JTAG player) and search for a compression possiblility. (I did a Huffman decompression on a 68HC11, it is small and efficiant) -- MfG FalkArticle: 44424
"Nicholas Weaver" <nweaver@CSUA.Berkeley.EDU> schrieb im Newsbeitrag news:aeqcr7$19b5$1@agate.berkeley.edu... > In article <aeqc93$9568o$1@ID-84877.news.dfncis.de>, > Falk Brunner <Falk.Brunner@gmx.de> wrote: > >www.opencores.org > > B'ah, at least MY response would have forced him to do a little > work on his class project. :) ;-) Right. But if he really thinks he will win by copy & paste, he will soon realize (at least when he hit the ground of a real job) that he had better done it himself. So he will (sadly) end up in marketing ;-)) -- MfG Falk
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Compare FPGA features and resources
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