Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
hamish@cloud.net.au wrote: > Rick Filipkiewicz <rick@algor.co.uk> wrote: > > absolutely!! If the instantiated FF is a domain crosser then replication is a > > total killer [I wonder if any of the s/w engineers writing Synplify code have ever > > Spent part of last week working around automatic duplication of inferred > domain crossers. Ouch. Found that using the new clock groups in 7.x > helps. > > syn_keep and syn_preserve did not stop it from duplicating the critical > FFs. Only syn_maxfan = big plus setting the clock groups helped. > I couldn't go to 7.1 to use syn_replicate, as I discovered another > bug in that which has just about scared me off for life. > > Come on Hamish, tell us the bug - it sounds bad. Don't be shy since yu're pretty safe from the legal vultures down under :-)).Article: 44251
Hello Tom, Thank you for responding to my question.We were suspecting that the author of the application note expected us to provide pull-down resistors at the driver side. I feel much better now that I have a confirmation from you. The app note was kind of misleading when it did not mention anything about driver-side pull down. I have read appnote HFAN-1.0 from Maxim before, but have not seen the one from OnSemi yet. The one from OnSemiconductor has much more details. As for the termination, we will probably use Thevenin termination on the receiver side. This should provide the pull-down for the emitters as well. Again, thank you. Huy ------------- Tom Burgess wrote: > As noted, you need pulldown resistors for PECL outputs. You can terminate a differential PECL > pair by either combining the DC bias and line termination functions - a pair of 50 ohm pulldowns to > VCC-2V (or the Thevenin equivalent) at the load, or provide the DC bias current through pulldown > resistors to ground close to the driver and line termination by 100 ohms across the pair at the > load - so-called "Standard pair" termination. It was this second method that the app note writer > had in mind, perhaps because it would work with both the Xilinx drive scheme and (LV)PECL devices. > The messy part is choosing the optimum PECL pulldown resistor to balance AC and DC requirements - > it's somewhere between 142 and 200 ohms for 3.3V supplies depending on the tradeoffs chosen. > > There's a fairly recent (2001) app note on termination of modern ECL devices at http://www.onsemi.com > (formerly Motorola) - look for AND8020/D. Also Maxim has a good one: "Introduction to LVDS, PECL, and CML", > HFAN-1.0. > > Huy Nguyen wrote: > > > > Hello, > > > > I am trying to interface a Virtex-II chip to a standard LVPECL device with open-emitter output driver. This type of circuit requires a sink current for emitters, which is not provided by the differential termination scheme in Xilinx AppNote133. > > > > Is this differential termination scheme applicable for Xilinx's pseudo LVPECL drivers only, or also for standard LVPECL as well ? > > > > Thank you. > > > > Huy > > -- > Tom Burgess > Digital Engineer > Dominion Radio Astrophysical Observatory > P.O. Box 248, Penticton, B.C. > Canada V2A 6K3Article: 44252
I was wondering if there is any way I can use TTL IC's in Xilinx foundation (ver 1.5). Is there a special library that I can download or can I use one of the existing libraries that is somehow compatible with TTL? Thanks in advance, PouyaArticle: 44253
The Xilinx I am having right now is the ver. 1.5, which is from my textbook. Is there any way for me to get an upgrade version, or a free-trial? Thanks. DerrickArticle: 44254
You can use HOTMan ($69). There is a demo that does readback through the Xilinx Parallel III cable. You can read back through JTAG or select map. Steve www.vcc.com "David de Andrés Martínez" <ddandres@disca.upv.es> wrote in message news:ae9nsb$9ug$1@polaris.cc.upv.es... > I am working with a XCV800 and I want to perform a Readback-Capture of the > contents of the FPGA. > It seems (I am not sure) that it is necessary to use the Xilinx MultiLINX > cable to perform this operation, but it is no software available that > supports this operation. > > Anyone can tell me if there is any commercial software to perform a > readback-capture and which hardware I need to use? > > Please, reply to this address: ddandres@disca.upv.es > > Thank you very much.best regards, > David de Andrés. > >Article: 44255
No, It took us a lot to talk them into dropping that library a number of
years ago. If you drop TTL equivalent components into an FPGA design you
get very poor utilization and performance. If you want to use ready made
components use the coregen components instead.
Pouya Razavi wrote:
> I was wondering if there is any way I can use TTL IC's in Xilinx
> foundation (ver 1.5). Is there a special library that I can download
> or can I use one of the existing libraries that is somehow compatible
> with TTL?
>
> Thanks in advance,
> Pouya
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44256
continued...
TTL was very pin-limited, so the functions were pretty much designed
around 14 and 16 pin packages. As a result of that and some
peculiarities caused by the unsymmetric drive, there are many compromises
in the TTL library. With FPGAs, you don't have a pin limit on internal
functions so why design using a library built up around those limits?
You also get some features like the fast carry chain that make many of
the TTL parts non-applicable (no need to do carry lookahead or counter
cascades).
Pouya Razavi wrote:
> I was wondering if there is any way I can use TTL IC's in Xilinx
> foundation (ver 1.5). Is there a special library that I can download
> or can I use one of the existing libraries that is somehow compatible
> with TTL?
>
> Thanks in advance,
> Pouya
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44257
Go to the Xilinx website. In exchange for your name and contact info, you can
download the webpack at no charge. It includes everything you need to do the
smaller devices.
Derrick Cheng wrote:
> The Xilinx I am having right now is the ver. 1.5, which is from my textbook.
> Is there any way for me to get an upgrade version, or a free-trial? Thanks.
>
> Derrick
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44258
John Williams <j2.williams@qut.edu.au> wrote in message news:<3D081A8E.82F3A57B@qut.edu.au>...
> Peter Alfke wrote:
> >
> > Are you reading and writing the same location?
> > Virtex-II does that for free, with one clock edge ( read the old, then
> > write the new data value, if you wish)
>
> Yes, I am doing that, (read, update, write) however for now I am
> constrained to target a Virtex.
>
> Out of interest though, what is the VHDL template to do this dual
> read/write on a single clock edge?
Let the synthesis tool infer your ram...
entity ram is
port (
addr : in STD_LOGIC_VECTOR; -- address bus
rddat : out STD_LOGIC_VECTOR; -- read port data bus
wrdat : in STD_LOGIC_VECTOR; -- write port data bus
wrclk : in STD_LOGIC; -- write port clock
we : in STD_LOGIC); -- write enable
end ram;
architecture ram of ram is
type mem_type is array (2 ** addr'length - 1 downto 0) of
std_logic_vector (rddat'length - 1 downto 0);
signal mem: mem_type; -- memory array
begin
-- Data is always available on the read data bus 'rddat'.
rddat <= mem(conv_integer (addr));
--
wr_ram: process (wrclk)
begin
if falling_edge(wrclk) then
if (we = '1') then
mem(conv_integer (addr)) <= wrdat;
end if;
end if;
end process wr_ram;
end ram;
If you're using XST, you don't have the luxury of unconstrained
logic vectors yet, (they've promised the fix is coming), so you
have to explicitly define the size of your address and data vectors
in the entity declaration and type declaration. I.e., use:
addr : in STD_LOGIC_VECTOR(3 downto 0); -- address bus
rddat : out STD_LOGIC_VECTOR(1 downto 0); -- read port data bus
wrdat : in STD_LOGIC_VECTOR(1 downto 0); -- write port data bus
and:
type mem_type is array (15 downto 0) of
std_logic_vector (1 downto 0);
signal mem: mem_type; -- memory array
to define a 2-bit 16 deep ram.
What makes this a falling clock edge RAM is the
"falling_edge" macro, no need to gate anything.
In the Virtex, the clock edge for the SelectRAM
is the same as it's associated FF. Try opening up a
small Virtex part in the FPGA editor and have a
look around.
Or are you using the BlockRAM in dual port mode?
with a rising edge on one side, falling edge on
the other, to get around that read clock delay.
Ah, that makes sense. In that case,
expand the example above to include a read clock
and a write clock, with falling_edge macro for
write clock and rising_edge for read clock.
Polarity is independently selectable for the
two sides of BlockRAM.
entity dpbram is
port (
addr_A : in STD_LOGIC_VECTOR; -- Read address bus
rddat_A : out STD_LOGIC_VECTOR; -- read port data bus
rdclk_A : in STD_LOGIC; -- Read port clock
addr_B : in STD_LOGIC_VECTOR; -- Write address bus
wrdat_B : in STD_LOGIC_VECTOR; -- write port data bus
wrclk_B : in STD_LOGIC; -- write port clock
we_B : in STD_LOGIC); -- write enable
end dpbram;
architecture ram of ram is
type mem_type is array (2 ** addr'length - 1 downto 0) of
std_logic_vector (rddat'length - 1 downto 0);
signal mem: mem_type; -- memory array
begin
rd_ram: process (rdclk_A)
begin
if rising_edge(rdclk_A) then
rddat_A <= mem(conv_integer (addr_A));
end if;
end process rd_ram;
wr_ram: process (wrclk_B)
begin
if falling_edge(wrclk_B) then
if (we_B = '1') then
mem(conv_integer (addr_B)) <= wrdat_B;
end if;
end if;
end process wr_ram;
end ram;
I don't know if the synth tools are sharp enough
yet to infer BlockRAM like that though, haven't
tried it yet. Do they choke on this?
BUT DON'T GATE CLOCKS, unless you are only
ever going to build one piece, and have a lot
of time to verify that one works.
Regards,
John
>
> Regards,
>
> John
Article: 44261I think the simple answer is no, you can't route to a GCLK except from its associated pin. However, you can route from a regular IO pad to a BUFG and then distribute the clocks from there. The output of the BUFG goes straight to the global routing resources as you probably need. However, you should note that there may be some disadvantages to this approach depending on the specific details of your design. For example, if you are trying to clock in data off of the same bus with that clock, then the delay introduced by routing from the pin to the BUFG and back may skew the clock so that it can no longer meet your input timing. Also, if you are routing to a DLL, this extra delay will not be compensated for. Vic "cfk" <cfk_alter_ego@pacbell.net> wrote in message news:nQpO8.3107$ob1.166624459@newssvr21.news.prodigy.com... > I have a board with a VirtexE2000 part on it that was developed for another > project and I am adapting it for a new project. One of the issues is that I > have a Mictor connector that I will be using to interface a 32bit bus at > 100Mhz from the FPGA to another *yet to be developed* board. It turns out > that a clock will be coming into the FPGA across this hi-speed connector (a > Mictor is a microstrip connector with 38 pins that is 50 ohms at 1NS, > according to AMP). The clock coming in will be coming to an IOPAD and not a > GCK input. > > So, here is my question: "Can I route an IOPAD from one bank to the GCK of a > different bank and then distribute clocks from that GCK?" > > Charles > >Article: 44262
I'm not sure what you have said makes sense. If you have these three clocks tied to the same clock, then they are all the same clock as far as PAR is concerned. Are you suggesting that your FPGA has a mode where the domain of the fast clock is completely unused? Because otherwise, you really need two separate clock inputs to have two different speed clocks in your design. Vic > I am trying do something that should be simple. I have one clock line > feeding 3 filter sections. I need the first two filter sections routed to a > 10 ns period spec. The last filter section only needs to route to 20 ns(it's > shut down when operating at fastest rate). > > I thought I could just get by using by renaming the clock into the third > section, i.e. > > Slo_Clk <= Clk; > > First two sections use Clk and the last section uses Slo_Clk. My .ucf is set > up to constrain Clk to 10ns and Slo_Clk to 20ns. > > The design compiles and PARs fine. The timing analysis, however, only shows > the request/actual times for Slo_Clk so I have no way of knowing whether the > fast clock really works to 10 ns. Should I assume because no timing errors > were reported that the 10ns spec was met? Is it possible that the PAR used > 20 ns for both Clk and Slo_Clk? Any suggestions for a better way to do this? > > Thanks, > Clark Pope > > > >Article: 44263
I have the following lines of VHDL code in my design: ClockFrequency <= (1 sec) / ClockPeriod; MaxClockCount <= ClockFrequency / (BaudRate*32); where ClockFrequency and MaxClockCount are integer signals and everything else is either a constant or a generic constant. Note that the signals should be synthesized as constants since everything they are generated from are constants. This was done so that the same code could be reused with different generic parameters. This works great in VHDL with the numeric_std package, but when I try to synthesize using Synplicity 7.1, I get: No matching overload for "/" How can I get Synplify to just do the math and figure out what the constant values should be?Article: 44264
HI: I am looking for Lattice download cable. Do somebody know that schematic or where I can get the schematic? Thanks! YHArticle: 44265
>ClockFrequency <= (1 sec) / ClockPeriod; >MaxClockCount <= ClockFrequency / (BaudRate*32); >where ClockFrequency and MaxClockCount are integer signals and everything >else is either a constant or a generic constant. Note that the signals >should be synthesized as constants since everything they are generated from >are constants. This was done so that the same code could be reused with >different generic parameters. >This works great in VHDL with the numeric_std package, but when I try to >synthesize using Synplicity 7.1, I get: >No matching overload for "/" You could avoid using the type time in your clock frequency signal. Thus: ClockFrequency <= (1000) / ClockPeriod; -- answer greater thatn 0 Where ClockPeriod is an integer. I believe that since synthesis does not support type time, it gives you this warning. Your other option is for you to provide the values as constants: CONSTANT ClockFrequency : Integer := 20; --------------------------------------------------------------------------- Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 http://www.vhdlcohen.com/ vhdlcohen@aol.com Author of following textbooks: * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 * Component Design by Example ", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 ------------------------------------------------------------------------------Article: 44266
"Pouya Razavi" <razavi@uiuc.edu> wrote in message news:bad5b81.0206141338.655b1029@posting.google.com... > I was wondering if there is any way I can use TTL IC's in Xilinx > foundation (ver 1.5). Is there a special library that I can download > or can I use one of the existing libraries that is somehow compatible > with TTL? Not with Xilinx, as others have said. Altera has several, though, in their MaxPlus libraries. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_heller Low-cost Altera Flex design kit: http://www.leonheller.comArticle: 44267
Leon Heller wrote: > "Pouya Razavi" <razavi@uiuc.edu> wrote in message > news:bad5b81.0206141338.655b1029@posting.google.com... > > I was wondering if there is any way I can use TTL IC's in Xilinx > > foundation (ver 1.5). Is there a special library that I can download > > or can I use one of the existing libraries that is somehow compatible > > with TTL? > > Not with Xilinx, as others have said. Altera has several, though, in their > MaxPlus libraries. > > Leon > - But, as Ray pointed out, a TTL library would lead to inefficient and poorly performing FPGA designs. The 7400 ( and 9300) TTL SSI and MSI families were created in the mid-to-late '60s, i.e. about 35 years ago, to fit the constraints of a 14- or 16-pin package. ( I remember, I was there, and was responsible for some of the MSI designs and their trade-offs). Such constraints are meaningless in an FPGA, which also has new features like carry logic stretching over long words. TTL libraries today would be a disservice to the FPGA designers. Peter Alfke, Xilinx Applications.Article: 44268
"Peter Alfke" <palfke@earthlink.net> wrote in message news:3D0AE8C2.76F49B8E@earthlink.net... > But, as Ray pointed out, a TTL library would lead to inefficient and poorly > performing FPGA designs. I wasn't advocating their use, it was just an observation. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_heller Low-cost Altera Flex design kit: http://www.leonheller.comArticle: 44269
The setup time of 2 ns in a Virtex is not so bad, so I will try it without a register in front of the ram. Thanks for the answers. (A little bit late, but there is so much to implement and so little time). HolgerArticle: 44270
newman wrote: > WebPack. But I don't see > >>any significant differences other than a very few. >> >>1) Support for older 4K device families and Spartan derivatives via >>pregenerated EDIF netlist. >> >>2) CORE Generator >> >>3) Timing Improvement Wizard - (What is it?) >> >>4) FPGA Editor >> >>Other differences are in the list of options, WebPack does not have the >>-- >> > > > > Good questions Rickman, > > Based on past posts that I remember, you appear to be a frugal tools > guy. I was a licensed Foundation BaseX guy, and when I saw the > features of the BaseX vs Webpack, I was disturbed that I paid > maintenance, while the Web pack guys almost got everything that I got, > but paid nothing. I rationalized it away that $299 / year was not too > much too pay for phone support and the additional features provided. > Last time I checked, the baseX for ISE was $695 / year, which may be > inconsequential to a large corporation, but is a hefty increase to to > the small business owner. > I am not a super duper power user, but IMHO, I think the FPGA Editor > and it's associated methodology separates the men from the boys, > although there has been some talk that it has suffered some > degradation from the days of 3.1i. Coregen is a useful tool, and I > cannot see myself without it for even $695 / year. > The timing wizard gives you a hypertext link in the timing analyzer > report that gives suggestions on how to improve upon a failed timing > path. From the couple of suggestions I have looked at, it has yet to > give me any earth shattering sugestions. > Overall, I think that the $695 / year is a reasonable price to pay > for baseX, cause it gives the user a better feel for what the full up > system can do. > > Newman I recently attended a free 1 day seminar for VHDL at the local Xilinx rep and with the seminar the ISE Base-X is available at S$99. Check with your local Xilinx rep, this is a Xilinx promotion. I am currently using the webpack, but will be ordering the Base-X package at the special proce. For me the added tools not found in the web pack look VERY usefull once you see what they actually do. I must commend Xilinx for their software support. I recently switched from another companies parts because of poor software support. The free webpack from Xilinx is significantly better that what I had paid $1500 for from the other company. The special offer for the Base-X tools shows that Xilinx is actually trying to get people to use their parts and not really excessive on the price. - TroyArticle: 44271
>TTL libraries today would be a disservice to the FPGA designers. Ahh, but the big green button could fix it all up. Big :) in case it's needed. [Why is the magic button always green?] -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 44272
That fixed it! Many thanks all. Ray Andraka <ray@andraka.com> wrote: :Try putting the type identifier in the generic declaration part of the :component declaration. I think it is complaining because the types don't :match: : :component FD : --synthesis translate_off : generic(TimingChecksOn: Boolean := FALSE); : --synthesis translate_on : port (D,C : in std_logic; : Q : out std_logic); : end component; : attribute syn_black_box of FD : component is true; : :Article: 44273
I'm using an XC9572XL part with Webpack schematic entry and I cannot figure out how to assign specific package pins to the IBUF and OBUF devices. I've blown several hours looking for this and would greatly appreciate any help.Article: 44274
My experience is based on using the previous one, foundation 1.5, but I suspect that if you right click in the IPAD or OPAD on your schematic, that you can set a property called "LOC" and that property will be the pin number. "Jim Stewart" <jstewart@jkmicro.com> wrote in message news:DBE581AC4D13488B.86DD1F2F267CB6BB.2098EC45139B163B@lp.airnews.net... > I'm using an XC9572XL part with Webpack schematic entry and I cannot > figure out how to assign specific package pins to the IBUF and OBUF > devices. I've blown several hours looking for this and would greatly > appreciate any help.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z