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Hello everybody, I have a question regarding "impact", the tool delivered with WebPack to program a device. What I need is a possibility to program the device in batch mode, that is without a gui. As far as I read the manual there exist such a mode in impact, but when I start the tool with impact.exe -batch I get the following message C:\xilinx_webpack\bin\nt>.\impact.exe -batch WARNING:Portability - Message file "iMPACT.msg" wasn't found. EXCEPTION:iMPACT:ConfigDevice.c:371:1.1.4.5 - ACD entry not found. So I wonder about the message "ACD entry not found". Anybody out there who can give me a hint how to start the interactive, non gui mode? What am I missing ? Something in the manual I've not read? Didn't found an answer in the Xilinx Answer Base... Any help appreciated Thanks in advance PeterArticle: 44301
Hello.
I can't work with a ram defined as:
ram unsigned char RAM[160*120];
dk1.1 gives an enormous EDIF an uses 10e6 logical gates. ???
Xilinx Foundation crushes when attempting to do the mapping.
We have VirtexE 2000ebg560-6 FPGA on a RC1000, and we use
DK1.1.
I really need to use the internal FPGA RAM. I know how to use
the external RC1000 SRAM (4 modules)... but don't know what's
wrong with my code.
Could you please contact me or give me an example for doing that.
I work on image processing. I can send my little code.
What I attempt to do:
1.- I have a frame in the host program. a 160*120 matrix if unsigned
bytes.
2.- I send this matrix to SRAM
3.- I want to read the SRAM and write the matrix to the FPGA's RAM
4.- Manipulate the frame... for example adding 1 to every pixel...
whatever (then we need to write a filter)
5.- Pass the new rewritten frame to the SRAM
6.- Then the host program loades the frame.
I've do that with SRAM. But FPGA's RAM doesn't work. Any suggestion
Thank you.
--
Antonio Martínez Álvarez, <amartinez@atc.ugr.es>
Departamento de Arquitectura y Tecnología de Computadoras
Universidad de Granada (Spain)
Article: 44302Up to now, I use XST that comes with the ISE package. A friend compiled my code with Leonardo spectrum. The number of needed slices was decreased by 30%. XST seems to be much bader, then I always thought. Before I buy Leonardo, I would like to know, if other VHDL compilers are even better (e.g. synplify). Besides, any idea about the prices for theese tools ? -ManfredArticle: 44303
System generator uses the coregen cores.
Ken Mac wrote:
> Hello Folks,
>
> Can anyone give me an idea on how System Generator and Core Generator
> perform relative to each other in terms of slice cost/clock speed when
> defining FIR filters (e.g. single-rate, interpolating and decimating).
>
> Does either have an advantage or are they both using the same base code to
> generate filters? (I know CoreGen uses distributed arithmetic for fir
> filters - does System Generator do the same?).
>
> Thanks for your time,
>
> Ken
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44304Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote: > The second problem will be that when the design hierarchy is kept (In my > case to avoid the aforementioned bug.), XST cannot "bubble up" tri-state > buffers unlike other synthesis tools (I know at least LeonardoSpectrum > can "bubble up" tri-state buffers even when the design hierarchy is > kept.). What does "bubble up" mean? Do you mean push-through? If so you must be the only person on this newsgroup who thinks that's a desirable feature. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 44305
rickman wrote: > > But how do you deal with the anti resonance? One of the other posts > gives a link to a lengthly discussion of power supply bypassing and > shows how using caps with different SRFs gives a HIGHER impedance at > points between the SRFs. Seems to me that it can be very tricky to get > this right. "Anti resonance" isn't a problem is the SRFs are "close enough." In the same sense that two 1uF caps with 3% differences in SRFs won't give you a poor impedance at the 1.5% midpoint, in caps with values where the inductance (for the low SRF) and capacitance (for the high SRF) are not the predominant part of the impedance, the ESR "bottom" will allow a clean transition. If you have to build an absolute minimum decoupling scheme, simulation is your friend. > The other issue I have is with the use of 1206 caps for bypassing. Size > is one parameter that does affect impedance at high frequencies, unlike > capacitance. So why use a 1 uF cap in a 1206 package with a low SRF > when a 0.1 uF cap in an 0603 package will work better at all frequencies > above the SRF? I don't think the freqs much below SRF are important for > these caps. If your clocks are above 40 MHz, for example, then your > switching noise will start at 80 MHz and go well up beyond 500 MHz. The > lower frequency noise by contrast is small and will be dealt with by the > bulk cap, < 10 MHz. The 0603 caps will be effective down to 10 MHz. So > the band of interest is covered. > > Am I missing something? All you are missing is that I pulled the 1206 curves for illustration from a graph comparing different caps. I didn't try to suggest any particular bypassing scheme in this thread but have been trying to talk about the mess of decoupling generically. Look at the impedance curves of your caps. Look at your *impedance* needs across the frequencies based on you *current draw* at those frequencies, usually the response to worst case time-domain current fluctuations at the system clock rate. I haven't spoken about power supply response time here which is also a large part of the lower frequency response. The original question was what to do about a design with *no room* for more caps. While I do advocate smaller packages for lower impedances, I don't suggest that the costs for "special" caps are necessarily worth the advantage. Package costs for an 0603 isn't much different than that for a 1206. An 0306 package is an even better consideration for comparable capacitance but this style of cap isn't terribly common. You could go to 0201 caps but the bulk capacitance can't hit as high a value and many people 1) don't like to mix cap sizes in their manufacturing and 2) don't want to deal with devices below a "manageable" size. Smaller is (typically) better. If there is virtually no board space left for decoupling, a better decoupling scheme could be implemented with some unusual - and costly - alternative to two-terminal discreetes. If you can develop a good decoupling methodology with the less expensive alternatives, do it! > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 44306
"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag > these caps. If your clocks are > above 40 MHz, for example, then your > switching noise will start at 80 MHz and go well up beyond 500 MHz. The > lower frequency noise by contrast is small and will be dealt with by the > bulk cap, < 10 MHz. The 0603 caps will be effective down to 10 MHz. So > the band of interest is covered. Warning, be carefull. The clock speed is NOT the thing that matters. Its the switching speed of the device. The FlipFlops will switch @ 1 MHz just as fast as @ 100 MHz. The decoupling must handle the same ammout of work (regarding the high speed decoupling, not low speed) -- MfG FalkArticle: 44307
hamish@cloud.net.au wrote: > Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote: > > The second problem will be that when the design hierarchy is kept (In my > > case to avoid the aforementioned bug.), XST cannot "bubble up" tri-state > > buffers unlike other synthesis tools (I know at least LeonardoSpectrum > > can "bubble up" tri-state buffers even when the design hierarchy is > > kept.). > > What does "bubble up" mean? > > Do you mean push-through? If so you must be the only person on this > newsgroup who thinks that's a desirable feature. > > Hamish > -- > Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au> Doesn't "bubble up" mean moving internal tri-state busses up to the top hierarchy level so that the tri-state drivers are at the outputs of the next level down instead of being buried further down. ?Article: 44308
Hello, I have a linear feedback shift register question. My focus is more coding theory than crypto ... I would like to add a pseudo random (PN) sequence of 7-bit symbols over GF(128) to my data sequence. The LFSR I am trying to implement is specified by a GF(128) polynomial defined as follows: f(x) = x^3 + x + alpha^3 where alpha^7 + alpha^3 + 1 = 0 The block diagram that I have shows this: --->z^-1-->xor--->z^-1--->z^-1--->--->xor---> out ^ ^ | ^ | | | | | | | | alpha^3 | | | | | \ / data ---------------------------------------- input The final xor, data input, and output are all 7 bits wide. My problem is that I don't understand the use of alpha in this context. I am more familiar with a polynomial such as x^3 + x + 1. Can someone enlighten me or point me to a reference which can help? Thanks, DougArticle: 44309
Hi All,
I want to emback on a series of RF type projects and needing some advice on
which development board to use. I am from ASIC background. My requirements
are as follows:
i) Size matters, in terms of gate count, bigger says better for me. ( Say
300k gates)
ii) Free Webpack compatible. As this is a home project for the unemployed
contractor.
What is the maximum design size this software allows, any ideas?
iii) Again size matters, in terms of physical size. PCCARD (i.e pcmcia or
compact flash) interface
for programming is desirable but not essential. i.e something I can
plug into my notebook in the
library where I do most of the mental development.
iv) Costs not more than $200 or £150.
I have seen burch-ed, anybody with experience of this company?
Thanks for reading.
Cheers
Femi.
Article: 44310
Hi All,
I have designed some digital RF type circuits which I am eager to try out
for real as a home project.
My development platform is Xilinx free webpack based.
Looking for advice on development kit for my RF type home projects. My
requirements are:
i) Size matters. Gate count has to be as high as possible (>100k).
Say Spartan II or Vertex II.
ii) Free Webpack support.
iii) Support for Serial, JTAG, let say as many standard IO as possible.
iv) Cost < $200(£150) .
v) Can I have something in PCMCIA(PCCARD) format ?
I have read about the following kits, but need advice from your
experience(s)
1) Insight
2) AVnet
Cheers
Femi.
Article: 44311Falk Brunner wrote: > "rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag > these caps. If > your clocks are > > > above 40 MHz, for example, then your > > switching noise will start at 80 MHz and go well up beyond 500 MHz. The > > lower frequency noise by contrast is small and will be dealt with by the > > bulk cap, < 10 MHz. The 0603 caps will be effective down to 10 MHz. So > > the band of interest is covered. > > Warning, be carefull. > The clock speed is NOT the thing that matters. Its the switching speed of > the device. The FlipFlops will switch @ 1 MHz just as fast as @ 100 MHz. The > decoupling must handle the same ammout of work (regarding the high speed > decoupling, not low speed) > > -- > MfG > Falk This subject comes up regularly and, although there's a fair amount of light, there's also quite a lot of heat. Does anyone know of any experimental [looking at the power/gnd pins of an FPGA/ASIC] or IBIS/SPICE modelling of this stuff with a real PCB, real FPGA doing its thing, and with real life Cap models ? Lets say a heavy example: e.g. a burst of 8x72-bit words with alternating all 1's & all 0's to a DDR DRAM clocking @ 133MHz and all the data pins are on the same ``side'' [maybe even the same bank] of the FPGA. ... then do the same modelling with all the Caps removed.Article: 44312
"Rick Filipkiewicz" <rick@algor.co.uk> schrieb im Newsbeitrag news:3D0E2D50.C7589606@algor.co.uk... > Does anyone know of any experimental [looking at the power/gnd pins of an > FPGA/ASIC] or IBIS/SPICE modelling of this stuff with a real PCB, real FPGA > doing its thing, and with real life Cap models ? A first attempt digital.burned-fuses.de -- MfG FalkArticle: 44313
Does the DLC4 aka Xchecker programmer work with the iMPACT programming software bundled with WebPack? If not, is there an inexpensive programmer available or a simple way to integrate the old Foundation JTAG programmer (which works fine with the DLC4) into the WebPack tool chain?Article: 44314
XST is continuously getting better coverage of VHDL'93 and better
quality of results for inferred logic. Meanwhile, Synplicity keeps
adding 'features' that make it more and more difficult to use
instantiated primitives (it has gotten the nasty habit of optimizing
instantiated code, which is a no-no). Not sure they recognize it as a
problem.
Kevin Neilson wrote:
> Synplify is much better than XST and somewhat better than Leonardo.
> "Manfred Kraus" <newsreply@cesys.com> wrote in message
> news:aekgtn$7gdrf$1@ID-22088.news.dfncis.de...
> > Up to now, I use XST that comes with the ISE package.
> > A friend compiled my code with Leonardo spectrum.
> > The number of needed slices was decreased by 30%.
> > XST seems to be much bader, then I always thought.
> > Before I buy Leonardo, I would like to know, if other
> > VHDL compilers are even better (e.g. synplify).
> > Besides, any idea about the prices for theese tools ?
> >
> > -Manfred
> >
> >
> >
> >
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44315
hamish@cloud.net.au wrote:
>
>
> What does "bubble up" mean?
>
Rick already explained it correctly, but the term "bubbling up
tri-state buffers" means when the design hierarchy is kept, moving
tri-state buffers to the top of the hierarchy, and converting them to
OBUFT or IOBUF IO pads.
LeonardoSpectrum's manual uses this term, and that's where I picked it
up.
> Do you mean push-through? If so you must be the only person on this
> newsgroup who thinks that's a desirable feature.
Nope, Synplicity's CTO is the guy who thinks tri-state
push-through is a desirable feature.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 44316
Why not you request an evaluation version of Synplify and
LeonardoSpectrum, and see it for yourself?
I believe both companies will give you an evaluation license if you ask.
Regarding the QoR (Quality of Results) of XST, when your friend
compiled your design with LeonardoSpectrum, did that person optimized
the design for area or speed?
Also, when you synthesized your design with XST, did you optimize it for
speed or area?
It only my speculation, but if your friend optimized your design for
area with LeonardoSpectrum, but you optimized your design for speed with
XST, then that might explain the results you got.
Another thing to consider will be the cost, since XST is free (In the
worst case, you can use the one from ISE WebPACK, and import an EDIF
netlist to your design environment.), but a perpetual license version of
Synplify or
LeonardoSpectrum costs about $8,000 to $10,000.
I have been using XST because it is free, and in general I am happy with
its QoR, but it has problems with "bubbling up" tri-state buffers and
using blackboxes when the design hierarchy is flattened.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Manfred Kraus wrote:
>
> Up to now, I use XST that comes with the ISE package.
> A friend compiled my code with Leonardo spectrum.
> The number of needed slices was decreased by 30%.
> XST seems to be much bader, then I always thought.
> Before I buy Leonardo, I would like to know, if other
> VHDL compilers are even better (e.g. synplify).
> Besides, any idea about the prices for theese tools ?
>
> -Manfred
Article: 44317...and based on the recent contact with the application engineers, a new Xilinx Mapper module is available for the Synplify tool (v7.1); ask an application engineer or wait for the next tool upgrade. I have yet to try it out but I have high hopes. Ray Andraka wrote: > XST is continuously getting better coverage of VHDL'93 and better > quality of results for inferred logic. Meanwhile, Synplicity keeps > adding 'features' that make it more and more difficult to use > instantiated primitives (it has gotten the nasty habit of optimizing > instantiated code, which is a no-no). Not sure they recognize it as a > problem. > > Kevin Neilson wrote: > > > Synplify is much better than XST and somewhat better than Leonardo. > > "Manfred Kraus" <newsreply@cesys.com> wrote in message > > news:aekgtn$7gdrf$1@ID-22088.news.dfncis.de... > > > Up to now, I use XST that comes with the ISE package. > > > A friend compiled my code with Leonardo spectrum. > > > The number of needed slices was decreased by 30%. > > > XST seems to be much bader, then I always thought. > > > Before I buy Leonardo, I would like to know, if other > > > VHDL compilers are even better (e.g. synplify). > > > Besides, any idea about the prices for theese tools ? > > > > > > -Manfred > > > > > > > > > > > > > > > > > > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 44318
Hi. I trying to put together a really small, cheap circuit using a CPLD (probably Xilinx 9500). I don't want to have to use a seperate oscillator chip, so I'm trying to figure a way to generate a 1 - 2 MHz (doesn't need to be accurate) clock wtih only the CPLD. I checked the archives, and a Xilinx data book, but didn't see anything. Thanks! DavidArticle: 44319
The manual MUXCY chain I had problems with going from 7.0.3 to 7.1 is now working with the new mapper but the FDRE primitive is still being optimized, so Synplify still knows better than I do about some instantiations :-) John_H wrote: > ...and based on the recent contact with the application engineers, a new > Xilinx Mapper module is available for the Synplify tool (v7.1); ask an > application engineer or wait for the next tool upgrade. I have yet to try > it out but I have high hopes. > > Ray Andraka wrote: > > > XST is continuously getting better coverage of VHDL'93 and better > > quality of results for inferred logic. Meanwhile, Synplicity keeps > > adding 'features' that make it more and more difficult to use > > instantiated primitives (it has gotten the nasty habit of optimizing > > instantiated code, which is a no-no). Not sure they recognize it as a > > problem. > > > > Kevin Neilson wrote: > > > > > Synplify is much better than XST and somewhat better than Leonardo. > > > "Manfred Kraus" <newsreply@cesys.com> wrote in message > > > news:aekgtn$7gdrf$1@ID-22088.news.dfncis.de... > > > > Up to now, I use XST that comes with the ISE package. > > > > A friend compiled my code with Leonardo spectrum. > > > > The number of needed slices was decreased by 30%. > > > > XST seems to be much bader, then I always thought. > > > > Before I buy Leonardo, I would like to know, if other > > > > VHDL compilers are even better (e.g. synplify). > > > > Besides, any idea about the prices for theese tools ? > > > > > > > > -Manfred > > > > > > > > > > > > > > > > > > > > > > > > > > > > -- > > --Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com > > > > "They that give up essential liberty to obtain a little > > temporary safety deserve neither liberty nor safety." > > -Benjamin Franklin, 1759Article: 44320
No idea about MicroBlaze...tried it but never got as far as looking for an OS. There is a uClinux port & kit available for the Nios processor, however. The company that did the port is Microtronix, out of Canada: http://www.microtronix.com/ The fledgling Nios Hacker's World website has a very brief, but nice review of the hardware that comes with the Microtronix uClinux kit for Nios: http://twistedminds.org/nios/modules.php?name=Content&pa=showpage&pid=4 Overall the kit is pretty cool - you can be off and running using a compact flash card for data storage and communicating via Ethernet in minutes. - Jesse Petter Gustad <newsmailcomp2@gustad.com> wrote in message news:<87fzzso6ai.fsf@filestore.home.gustad.com>... > Is there a uClinux or other MMU-less Linux/xBSD port available for > MicroBlaze? > > PetterArticle: 44321
???
------
|B
+----|---'\/\/\,--+
| |A |
+-<|-|-----||-----+
| | |
+|>o-|---'\/\/\,--+
|C
------
This looks like the junction of the three devices will always be
(Voh+Vol)/2. I feel like I'm missing something big but there's a real
interesting concept here that I've misinterpreted. I'd love to
understand the details.
Peter Alfke wrote:
>
> If you can afford to dedicate three pins ( 2 outputs and one input) to
> this task, it is easy:
> Input A internally drives output B non-inverted, and also output C
> inverted.
> Connect a resistor to pin A, the same value resistor to pin C, and a
> capacitor to pin B, and interconnect the other ends of these three
> components together.
> Start with two 1 kilohm resistors and 470 pF
> Surprisingly (not really, there is mathematical proof) stable over
> temperature and voltage.
>
> Peter Alfke, Xilinx Applications
> ====================================
> David Rogoff wrote:
>
> > Hi.
> >
> > I trying to put together a really small, cheap circuit using a CPLD
> > (probably Xilinx 9500). I don't want to have to use a seperate
> > oscillator chip, so I'm trying to figure a way to generate a 1 - 2 MHz
> > (doesn't need to be accurate) clock wtih only the CPLD. I checked the
> > archives, and a Xilinx data book, but didn't see anything.
> >
> > Thanks!
> >
> > David
Article: 44322You've got the resistor on B and the cap on A around the wrong way... should be cap on B and resistor on A. Cheers, James John_H wrote: > ??? > > ------ > |B > +----|---'\/\/\,--+ > | |A | > +-<|-|-----||-----+ > | | | > +|>o-|---'\/\/\,--+ > |C > ------ > > This looks like the junction of the three devices will always be > (Voh+Vol)/2. I feel like I'm missing something big but there's a real > interesting concept here that I've misinterpreted. I'd love to > understand the details. > > > Peter Alfke wrote: > >>If you can afford to dedicate three pins ( 2 outputs and one input) to >>this task, it is easy: >>Input A internally drives output B non-inverted, and also output C >>inverted. >>Connect a resistor to pin A, the same value resistor to pin C, and a >>capacitor to pin B, and interconnect the other ends of these three >>components together. >>Start with two 1 kilohm resistors and 470 pF >>Surprisingly (not really, there is mathematical proof) stable over >>temperature and voltage. >> >>Peter Alfke, Xilinx Applications >>==================================== >>David Rogoff wrote: >> >> >>>Hi. >>> >>>I trying to put together a really small, cheap circuit using a CPLD >>>(probably Xilinx 9500). I don't want to have to use a seperate >>>oscillator chip, so I'm trying to figure a way to generate a 1 - 2 MHz >>>(doesn't need to be accurate) clock wtih only the CPLD. I checked the >>>archives, and a Xilinx data book, but didn't see anything. >>> >>>Thanks! >>> >>> David >> -- James Kennedy Electronics/Computer Design Engineer IntelliDesign Brisbane, Australia Tel: +61 7 3366 6478 Fax: +61 7 3366 6471Article: 44323
> Ananth wrote: > > > Hi. > > > > Im new to FPGA world. I must say I havent stepped in. But am very > > interested. Ive access to some fpga material mostly data books of > > Xilinx. Could you pls suggest where do I start learning the > > programming. Have a look at our free Xilinx and Altera tutorials: http://www.al-williams.com/pictutor Enjoy! Al Williams AWCArticle: 44324
John_H wrote:
>
> ???
>
> ------
> |B
> +----|---'\/\/\,--+
> | |A |
> +-<|-|-----||-----+
> | | |
> +|>o-|---'\/\/\,--+
> |C
> ------
>
> This looks like the junction of the three devices will always be
> (Voh+Vol)/2. I feel like I'm missing something big but there's a real
> interesting concept here that I've misinterpreted. I'd love to
> understand the details.
------
|A Ri
+------|---'\/\/\,--+
| |B |
+-|>-+-|-----||-----+ \ |\ |
| | C | \ | \ |
+----+ | | | / | /
| |C Rf | |/ |/
+|>o---|---'\/\/\,--+
|
--------
This is the best performance topology for a 3 terminal oscillator.
Note that A -> B is positive feedback (non inv),
and that B -> C is megative feedback (inv).
Importantly, the REGEN output _must_ occur first, so
C = !B; is better than C = !A;
The circuit is stable at DC, but unstable at AC, and so oscillates.
Terminal A, is very noise prone, and should be adjacent to a GND pin,
terminal B should be adjacent to A, to give parasitic C
positive feedback.
Ri is a limiting resistor, and for best stability is larger than Rf,
but they
can be the same to reduce the BOM.
Osc time constant is Constant.Rf.C, with a small Ri influence.
Also, check that terminal A has a Vcc clamp diode, and is not a Vpp pin
:)
- jg
> Peter Alfke wrote:
> >
> > If you can afford to dedicate three pins ( 2 outputs and one input) to
> > this task, it is easy:
> > Input A internally drives output B non-inverted, and also output C
> > inverted.
> > Connect a resistor to pin A, the same value resistor to pin C, and a
> > capacitor to pin B, and interconnect the other ends of these three
> > components together.
> > Start with two 1 kilohm resistors and 470 pF
> > Surprisingly (not really, there is mathematical proof) stable over
> > temperature and voltage.
> >
> > Peter Alfke, Xilinx Applications
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