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Hi, I am currntly on H1-B visa, and since my current employer has decided to close our office, I am looking for a new job, and a company to take over my H1-B visa while my green card application goes through (my wife is American). Here is some higlights from my resume: · Proven digital ASIC, FPGA, and board design (mixed analog/digital) skills with 12 years of electronic engineering design experience in multi-national companies in the US and Europe · Extensive knowledge of various processor, u-controllers such as Intel's x86,. Motorola's 68k, 683xx, PowerQuick, PowerPC, AMD's Sharc DSP, TI's DSPs, Philips& Intel 8051-based u-controllers and Atmel's AVR. · Extensive experience in computer programming languages such as C, C++, ADA, Basic and Java, assembly language for different computer systems and u-processors (8-32 bits) · Product development experience from idea to specification, design, simulation, verification, test of device and board-level as well as manufacturing support and mass production. · Expert Knowledge of Mentor Graphics Applications in both Unix and PC · Solid background in support of Mentor based EDA (DA, DMGR, BA, LMS and all Mentor Based FPGA design programs) · Very good knowledge of Unix (HP and Sun), and Windows operating systems · Expert knowledge of Altera, Xilinx and Lattice CPLD and FPGA devices. · Excellent knowledge of DOS, Windows, and Unix operating systems · Excellent written and verbal communication skills in 3 different languages I am looking for a job as: * HW design engineer * FPGA design and verification * ASIC verification engineer * Mentor Graphics administration I live in New York at the moment, but I am willing to relocate. Please feel free to contact me if you have any questions, or if you want to get my complet resume. Best regards, Farhad Abdolian Astoria, New YorkArticle: 44326
John, just follow the instructions: resistor to A and to C, capacitor to B. Peter John_H wrote: > ??? > > ------ > |B > +----|---'\/\/\,--+ > | |A | > +-<|-|-----||-----+ > | | | > +|>o-|---'\/\/\,--+ > |C > ------ > > This looks like the junction of the three devices will always be > (Voh+Vol)/2. I feel like I'm missing something big but there's a real > interesting concept here that I've misinterpreted. I'd love to > understand the details. > > Peter Alfke wrote: > > > > If you can afford to dedicate three pins ( 2 outputs and one input) to > > this task, it is easy: > > Input A internally drives output B non-inverted, and also output C > > inverted. > > Connect a resistor to pin A, the same value resistor to pin C, and a > > capacitor to pin B, and interconnect the other ends of these three > > components together. > > Start with two 1 kilohm resistors and 470 pF > > Surprisingly (not really, there is mathematical proof) stable over > > temperature and voltage. > > > > Peter Alfke, Xilinx Applications > > ==================================== > > David Rogoff wrote: > > > > > Hi. > > > > > > I trying to put together a really small, cheap circuit using a CPLD > > > (probably Xilinx 9500). I don't want to have to use a seperate > > > oscillator chip, so I'm trying to figure a way to generate a 1 - 2 MHz > > > (doesn't need to be accurate) clock wtih only the CPLD. I checked the > > > archives, and a Xilinx data book, but didn't see anything. > > > > > > Thanks! > > > > > > DavidArticle: 44327
You can always request an evaluation license. Just got two, Leonardo Spectrum and synplify. And remember the first price is just the asking one. Jerry "Manfred Kraus" <newsreply@cesys.com> wrote in message news:aekgtn$7gdrf$1@ID-22088.news.dfncis.de... > Up to now, I use XST that comes with the ISE package. > A friend compiled my code with Leonardo spectrum. > The number of needed slices was decreased by 30%. > XST seems to be much bader, then I always thought. > Before I buy Leonardo, I would like to know, if other > VHDL compilers are even better (e.g. synplify). > Besides, any idea about the prices for theese tools ? > > -Manfred > > > > > >Article: 44328
Hi, I am using Xilinx Virtex series devices which provides BlockRAMs. However instantiating or inferring BlockRAMs has lot of its own stringent constraints like read and write address should be same, etc. If I want to implement a memory module in the FPGA (memory should be read when READ transits from low to high and CS is high, memory should be written into when WRITE transits from low to high and CS is high) with different read and write address, synthesis tool doesn't infer a BlockRAM. My question is, when the embedded memory can't be used as a full fledged memory, why are they included in the gate count of the device? For the cases like my application, I have to buy a higher gate count device (investing too much extra money). For example, if I want 32K bits of memory in my design, I need to realize it with Distributed RAM or Flip Flops. Hence I need more slices, higher gate count device and all the blockRAM blocks are wasted. (Unfortunately the option in Xilinx 4.2i "map slice logic into unused block RAMs" doesn't seem to work). Can anybody please suggest some solutions/alternatives (I have to use Virtex series devices).Article: 44329
I hate it when I just don't see. Thanks all for pointing out my
temporary blindness :-) Ever look for something you *know* is there
but you just can't find it?
Particular thanks to Jim for a little more detail. I started thinking
the resister to A (Ri) had some unusual role beyond my immediate grasp.
It's nice to know it's indeed to limit the current into A (since the
swing at the junction is beyond the rails).
John_H wrote:
>
> ???
<edit>
------
|B
+----|-----||-----+
| |A |
+-<|-|---'\/\/\,--+
| | |
+|>o-|---'\/\/\,--+
|C
------
</edit>
[ much better ]
> This looks like the junction of the three devices will always be
> (Voh+Vol)/2. I feel like I'm missing something big but there's a real
> interesting concept here that I've misinterpreted. I'd love to
> understand the details.
>
> Peter Alfke wrote:
> >
> > If you can afford to dedicate three pins ( 2 outputs and one input) to
> > this task, it is easy:
> > Input A internally drives output B non-inverted, and also output C
> > inverted.
> > Connect a resistor to pin A, the same value resistor to pin C, and a
> > capacitor to pin B, and interconnect the other ends of these three
> > components together.
> > Start with two 1 kilohm resistors and 470 pF
> > Surprisingly (not really, there is mathematical proof) stable over
> > temperature and voltage.
> >
> > Peter Alfke, Xilinx Applications
> > ====================================
> > David Rogoff wrote:
> >
> > > Hi.
> > >
> > > I trying to put together a really small, cheap circuit using a CPLD
> > > (probably Xilinx 9500). I don't want to have to use a seperate
> > > oscillator chip, so I'm trying to figure a way to generate a 1 - 2 MHz
> > > (doesn't need to be accurate) clock wtih only the CPLD. I checked the
> > > archives, and a Xilinx data book, but didn't see anything.
> > >
> > > Thanks!
> > >
> > > David
Article: 44330Hi Femi, There are a few links to customer's sites, and some resources at: http://www.burched.com.au/appnotes.html I see you already found our board, which is based on the SpartanIIe XC2S300E, works with the excellent free WebPACK software, and is US$190: http://www.burched.com.au/B5Spartan2.html Well, I guess I have had some experience with the company:) All good, of course;) Best regards Tony Burch http://www.BurchED.com Low cost FPGA boards, for System-On-Chip prototyping and education "FEMI" <femioye@hotmail.com> wrote in message news:aela28$fsa$1@knossos.btinternet.com... > Hi All, > > I want to emback on a series of RF type projects and needing some advice on > which development board to use. I am from ASIC background. My requirements > are as follows: > > i) Size matters, in terms of gate count, bigger says better for me. ( Say > 300k gates) > ii) Free Webpack compatible. As this is a home project for the unemployed > contractor. > What is the maximum design size this software allows, any ideas? > iii) Again size matters, in terms of physical size. PCCARD (i.e pcmcia or > compact flash) interface > for programming is desirable but not essential. i.e something I can > plug into my notebook in the > library where I do most of the mental development. > > iv) Costs not more than $200 or £150. > > I have seen burch-ed, anybody with experience of this company? > > Thanks for reading. > > Cheers > > Femi. > > >Article: 44331
Hello, I am new to CPLD/FPGA and would greatly appreciated any help in selecting a solution that matches our requirements. Our main requirements are as follow: 1. Pin count in the range 120 to 200 (ideal size around 150 I/O pins) 2. Must work on 5V (or higher) 3. Speed is not critical (very slow operation) 4. Logic complexity is very limited (the chip acts more or less as an I/O extension of a small microcontroller). 5. Can be easily converted to a mask based equivalent chip (a full ASIC is not possible at this stage, maybe for second generation). 6. Cost of the masked version is very critical (and having a reasonable conversion/tooling cost is also very nice to have). Any help will be greatly appreciated. You can post your reply here or if you prefer, email me directly to tal@zapta.com. Solicitations from vendors are welcome (we are located at south Bay Area, CA). Thanks, TalArticle: 44332
Femi, we offer a board with a 300k-gate Spartan-IIe. The board is configured and powered from USB, which makes it especially convenient when used in mobile setups. It offers all the peripherals required to build an FPGA-centric processor application (e.g. using MicroBlaze): - 1M x 8 (512k x 16) flash memory - 512k x 8 (256k x 16) static ram - 2 x 16 LC display - USB, RS232, VGA, JTAG - push buttons, dip switches, leds - up to 100 user I/O - 100x160mm Please refer to the following links for further information: http://www.trenz-electronic.de/prod/proden10.htm http://www.trenz-electronic.de/prod/proden12.htm http://www.trenz-electronic.de/prod/ps-TE-XC2Se.pdf In case you are looking for something smaller, we offer a board with a 200k-gate Spartan-II. Refer to the following links for further information: http://www.trenz-electronic.de/prod/proden7.htm http://www.trenz-electronic.de/prod/proden8.htm http://www.trenz-electronic.de/prod/proden9.htm http://www.trenz-electronic.de/prod/TE-XC2S.pdf Femi, I hope this helps finding a decision, best regards Felix _____ Dipl.-Ing. Felix Bertram Trenz Electronic GmbH Brendel 20 D - 32257 Buende Tel.: +49 (0) 5223 4939755 Fax.: +49 (0) 5223 48945 Mailto:f.bertram@trenz-electronic.de http://www.trenz-electronic.deArticle: 44333
kempaj@yahoo.com (Jesse Kempa) writes: > No idea about MicroBlaze...tried it but never got as far as looking > for an OS. There is a uClinux port & kit available for the Nios > processor, however. The company that did the port is Microtronix, out > of Canada: > http://www.microtronix.com/ > > The fledgling Nios Hacker's World website has a very brief, but nice > review of the hardware that comes with the Microtronix uClinux kit for > Nios: > http://twistedminds.org/nios/modules.php?name=Content&pa=showpage&pid=4 > > Overall the kit is pretty cool - you can be off and running using a > compact flash card for data storage and communicating via Ethernet in > minutes. I've seen a demo of the NIOS kit<m3y9evrlix.fsf@scimul.dolphinics.no>, but I was looking for something similar kit for the MicroBlaze. There seems to be a gcc (mb-gcc) port for the MicroBlaze: http://www.xilinx.com/ipcenter/processor_central/microblaze/doc/mb_tutorial_c2bits.pdf But I haven't seen a Linux (MMU'less) port for it yet. Anybody else? Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 44334
Hello all, I was just going through altera FPGA architectures. One of the observations is that the arch of FLEX was row based, arch of APEX and APEX-II was row based and had one level of hierarchy, which is known as megalab and Mercury & Stratix again doesn't have any level of hierarchy. What do u feel about these changes, specially in the terms of hierarchy? does it mean that hierarichal architecures doesn't provide and benifit for bigger devices. -DigariArticle: 44335
Hello to everybody, We have to deal with a slowly rising reset signal. Now, to avoid that our FPGA would sometimes think 'yes it's a reset, o no, wait, not yet, now, yes reset' (so badly triggering on the reset signal) I would like to make the reset signal inside the FPGA a bit more stable. How can I do this? I somehow have difficulties in my XC4000 to put there flip flops (which I think is the basic solution for this) but I was wondering if buffers of so would also help. I would get some components out of the foundation library. Any suggestions? E.g. would a clock buffer be better than a normal buffer? Put some things in serial? Greetz, JerreArticle: 44336
I did get a note from Synplicity stating that their "policy is to not touch
instantiated stuff so we would consider this a bug", which is includes both the
muxcy bit and the FDREs, so perhaps there is some hope after all. As you know, I
abhor having to run a perl (or other) script on the netlist after synthesis. It is
one more tool that gets a chance to muck up your design and one more that the
customer can forget to use later, which generates a support call (usually at the
worst possible time).
Rick Filipkiewicz wrote:
> John_H wrote:
>
> > The manual MUXCY chain I had problems with going from 7.0.3 to 7.1 is now
> > working with the new mapper but the FDRE primitive is still being optimized,
> > so Synplify still knows better than I do about some instantiations :-)
> >
> >
>
> O.k. so it looks like Synplify are *determined* to optimise everything, no
> matter what our (esp. Ray's) opinion might say to the contrary [with this sense
> of righteousness I'd guess they must be s/w engineers :-)].
> So the only action we can take is defensive and fix it systematically.
>
> o Perl hack the Synplify black-box libs to put some easily recognisable string
> in front of the prim names. e.g.
>
> ????_synth_tool_thinks_it_knows_better_than_me
>
> [Replace ???? with aggrieved word of choice].
>
> o Pre-process the source code looking for Xilinx prim instantiations and add the
> extra string. Easier in Verilog than VHDL I think. Perl's good for this.
>
> o Use Perl [actually ancient sed would do this] to remove the strings from the
> resulting EDIF.
>
> o (possibly) set up an auto-email that sends a bug report to Synplicity every
> time the 2nd Perl script runs.
>
> In fact the first step might not be needed since the second one could generate a
> list of prim instantiations, go get the relevant definitions from the BB lib,
> edit the name(s), and tack the results onto the bottom of the source file.
>
> I accept Ray A's reservations on this but needs must ....
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44337ted_jmt@zapta.com wrote: > > Hello, > > I am new to CPLD/FPGA and would greatly appreciated any help in > selecting a solution that matches our requirements. > > Our main requirements are as follow: > > 1. Pin count in the range 120 to 200 (ideal size around 150 I/O pins) > > 2. Must work on 5V (or higher) Interesting request - How much higher - and for what loads ? > > 3. Speed is not critical (very slow operation) > > 4. Logic complexity is very limited (the chip acts more or less as an > I/O extension of a small microcontroller). Then even the smallest FPGAs are probably too large :) 150 i/o is a lot in one package - what is this driving ? ( are all the loads in one place ? ) Is the IO by Serial or parallel BUS, 8 or 16 bits wide ? Better may be 32 io in 44 pin packages, and use 5 packages spread on the board(s). CPLDs come in 32/64/128/.. macrocells, the better ones can pack a shift and latch into one macrocell. Prices are appx $1/32MC > > 5. Can be easily converted to a mask based equivalent chip (a full > ASIC is not possible at this stage, maybe for second generation). > > 6. Cost of the masked version is very critical (and having a > reasonable conversion/tooling cost is also very nice to have). So too are the volumes :) - what is the budget per I/O pin ? > Any help will be greatly appreciated. You can post your reply here or > if you prefer, email me directly to tal@zapta.com. > > Solicitations from vendors are welcome (we are located at south Bay > Area, CA). -jgArticle: 44338
> Why not you request an evaluation version of Synplify and > LeonardoSpectrum, and see it for yourself? I will do so, but the experience of this groups' people is too valuable to exclude it from my choice. > I believe both companies will give you an evaluation license if you ask. > Regarding the QoR (Quality of Results) of XST, when your friend > compiled your design with LeonardoSpectrum, did that person optimized > the design for area or speed? No, we only adjusted the syntax of the attributes. > Also, when you synthesized your design with XST, did you optimize it for > speed or area? I tried both. Optimizing for area saves only 5 slices (out of about 350), but the speed constrains fail during P&R. > It only my speculation, but if your friend optimized your design for > area with LeonardoSpectrum, but you optimized your design for speed with > XST, then that might explain the results you got. Good thought, but this isnt the case. > Another thing to consider will be the cost, since XST is free (In the > worst case, you can use the one from ISE WebPACK, and import an EDIF > netlist to your design environment.), but a perpetual license version of > Synplify or > LeonardoSpectrum costs about $8,000 to $10,000. Today I got the offer from Altium: Leonardo Level 3 -- NodeLocked US$ 21.875 Leonardo Level 3 -- Floating US$ 32.815 Leonardo Level 3 Single Vendor -- Nodelocked US$ 13.690 Leonardo Level 3 Single Vendor -- Floating US$ 20.625 Optional Schematic Viewer Leonardo Insight Nodelocked -- US$ 5.625 Optional Schematic Viewer Leonardo Insight Floating -- US$ 8440 If it was about 8k to 10k, I would buy it immediately. > I have been using XST because it is free, and in general I am happy with > its QoR, but it has problems with "bubbling up" tri-state buffers and > using blackboxes when the design hierarchy is flattened. Maybe Ray is right and XST will get better with future ServicePacks ? > > > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.) > > > > Manfred Kraus wrote: > > > > Up to now, I use XST that comes with the ISE package. > > A friend compiled my code with Leonardo spectrum. > > The number of needed slices was decreased by 30%. > > XST seems to be much bader, then I always thought. > > Before I buy Leonardo, I would like to know, if other > > VHDL compilers are even better (e.g. synplify). > > Besides, any idea about the prices for theese tools ? > > > > -ManfredArticle: 44339
> You can always request an evaluation license. Just got two, > Leonardo Spectrum and synplify. > > And remember the first price is just the asking one. > > Jerry > Jerry, you are right. But I think the people in this NG share at least 500+ years of experience with different VHDL compilers. My own tests can only cover a few aspects. Also: Advice from current users is always better than the story that salesmen are telling. -ManfredArticle: 44340
In article <d4b00a9.0206180318.329d04b6@posting.google.com>, Jerre
<duvister@hotmail.com> writes
>We have to deal with a slowly rising reset signal.
How slow? If it's only a few milliseconds you could process it
with some kind of digital timeout. But this would mean relying
on the FPGA's power-on reset to provide reset-on-configuration, and
if you have a sloppy reset signal then you probably also have
poorly controlled power supply rise.
>Now, to avoid that
>our FPGA would sometimes think 'yes it's a reset, o no, wait, not yet,
>now, yes reset' (so badly triggering on the reset signal) I would like
>to make the reset signal inside the FPGA a bit more stable.
You can fake-up some kind of Schmitt trigger on the reset input
if you have a couple of spare I/O pins, but that is really a horrible
thing to do. Power-on reset is a tricky little analog function and
it is already very well implemented by standard reset generator
chips (look at Maxim's MAX707 for a simple example). It seems
silly to re-invent that wheel badly.
Some of the reset generators are available in tiny SOT-23 packages
so there is no excuse for not finding a few square millimetres of
board area for it!
--
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223 Email: jonathan.bromley@doulos.com
Fax: +44 1425 471573 Web: http://www.doulos.com
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Article: 44341I can only use defparam to initial a block ram in the behavior simulation and the clause of defparam can not be synthesized.In the language template, before the defparam there are a sentence of "//synthesis translate_off" and after the defparam there are "//synthesis translate_on".Does this mean I can not use this method to form a rom? But the ISE data sheet says I can do so.I am puzzled and thanks for answering.Article: 44342
Hi all, after reading virtex "5V tolerant I/Os" (see http://www.xilinx.com/products/virtex/techtopic/vtt002.pdf ) and Spartan II functional description, I would say that I can use a Spartan-II (PQ208 package) with all VccO=3.3V in LVTTL mode directly on a 5V ATA bus with no need of resistor or buffering. Right? Any comment/suggestion appreciated! Thx, StephaneArticle: 44343
I had this problem with initialisation of block ram - not i a Virtex, but in a Spartan-II, I think that these problems are related _The syntax given in the xapps doesn't work_ namely the synopsys_dc_script syntax It looks like your a verilog designer, I can't really comment on the valid method for the verilog, but I do know that http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID= 1&getPagePath=10695 provided the correct syntax for the BlockRam initialisation in VHDL, there surely exists a similar page for Verilog HTH -- Benjamin Todd European Organisation for Particle Physics SL SPS/LHC -- Control -- Timing Division CERN, Geneva, Switzerland, CH-1211 Building 864 Room 1 - A24 "hull" <hullhull@sina.com> wrote in message news:ee76ffc.-1@WebX.sUN8CHnE... > I can only use defparam to initial a block ram in the behavior simulation and the clause of defparam can not be synthesized.In the language template, before the defparam there are a sentence of "//synthesis translate_off" and after the defparam there are "//synthesis translate_on".Does this mean I can not use this method to form a rom? But the ISE data sheet says I can do so.I am puzzled and thanks for answering.Article: 44344
ah yes the verilog syntax is given in that link too <cut and paste from previous link> module RAMB (DO, ADDR, DI, EN, CLK, WE, RST); output [7:0] DO; input [8:0] ADDR; input [7:0] DI; input EN, CLK, WE, RST; // The defparam in this example are for simulation only //synthesis translate_off defparam RAMB_EXAMPLE.INIT_00 = 256'h1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100; defparam RAMB_EXAMPLE.INIT_01 = 256'h1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100; : : //synthesis translate_on //synthesis attribute INIT_00 of RAMB_EXAMPLE is "1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100" //synthesis attribute INIT_01 of RAMB_EXAMPLE is "1F1E1D1C1B1A191817161514131211100F0E0D0C0B0A09080706050403020100" : : RAMB4_S8 RAMB_EXAMPLE (.DO(DO), .ADDR(ADDR), .DI(DI), .EN(EN), .CLK(CLK), .WE(WE), .RST(RST)); endmodule </cut and paste from previous link> "Benjamin Todd" <Benjamin.Todd@cern.ch> wrote in message news:aencue$enn$1@sunnews.cern.ch... > I had this problem with initialisation of block ram - not i a Virtex, but in > a Spartan-II, I think that these problems are related > > _The syntax given in the xapps doesn't work_ > namely the synopsys_dc_script syntax > > It looks like your a verilog designer, I can't really comment on the valid > method for the verilog, but I do know that > > http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID= > 1&getPagePath=10695 > > provided the correct syntax for the BlockRam initialisation in VHDL, there > surely exists a similar page for Verilog > > HTH > > -- > Benjamin Todd > European Organisation for Particle Physics > SL SPS/LHC -- Control -- Timing Division > CERN, Geneva, Switzerland, CH-1211 > Building 864 Room 1 - A24 > > "hull" <hullhull@sina.com> wrote in message news:ee76ffc.-1@WebX.sUN8CHnE... > > I can only use defparam to initial a block ram in the behavior simulation > and the clause of defparam can not be synthesized.In the language template, > before the defparam there are a sentence of "//synthesis translate_off" and > after the defparam there are "//synthesis translate_on".Does this mean I can > not use this method to form a rom? But the ISE data sheet says I can do so.I > am puzzled and thanks for answering. > >Article: 44345
As a 'softie', I was dismayed to find that I needed to buy a 1.4GHz athlon with 1GB DDR ram just to be able to compile a design with handel-C, and then be able to do a PAR in less than one working day. this was for a XCV2000e which I managed to fill. This as when 1.4Ghz athlons were the hottest chip on the market. Pete "mac teh knife" <nospam@nowhere.com> wrote in message news:3d0d331a_3@news.chartertn.net... > We have started development using the new fpgas. We are evaluating the > virtex 2 and stratix devices. > What I'm finding out is my 2 year old machine ain't got what it takes to > crunch the files that can fill up > these multi million gate chips. I was wondering if anybody would care to > share with us the machine (PC) > they are using. Also has anybody evaluated linux vs window performance as > far as fpga applications are concerned. > > I'm looking at a P4 2.4ghz / 2 gig ram and 533 mhz front bus. I'm also > looking at a Xeon 2.4 g with 400 mhz > front bus. Does anybody know if there is a performance difference between > these two type of processors? > > Mac the knife is of course not my real name, I'm just so tired of spam that > posting to use net generates. > > thanks > Jerry > > >Article: 44346
Peter, I check the following link, and it say impact is supported by webpack http://toolbox.xilinx.com/cgi-bin/xilinx.storefront/1085522837/UserTemplate/1 When I type impact -batch on my ise4.2i SP3 system, i get a ">" prompt back. It sounds like you have a setup issue. NewmanArticle: 44347
Hi Femi, the CESYS FPGA development boards have SPARTAN-II with 200k capacity on it. They come with USB or PCI interface. You dont have to know anything about PCI or USB to use it because an external chip manages the interface. Just concentrate on your FPGA design. The required tools to download your design are included. You dont have to use JTAG or something. Download is done via the USB or PCI interface. If you like to get more information, please check the link http://www.cesys.com/english/ebene2/producto.htm -Manfred > Hi All, > > I want to emback on a series of RF type projects and needing some advice on > which development board to use. I am from ASIC background. My requirements > are as follows: > > i) Size matters, in terms of gate count, bigger says better for me. Say > 300k gates) > ii) Free Webpack compatible. As this is a home project for the unemployed > contractor. > What is the maximum design size this software allows, any ideas? > iii) Again size matters, in terms of physical size. PCCARD (i.e pcmcia or > compact flash) interface > for programming is desirable but not essential. i.e something I can > plug into my notebook in the > library where I do most of the mental development. > > iv) Costs not more than $200 or £150. > > I have seen burch-ed, anybody with experience of this company? > > Thanks for reading. > > Cheers > > Femi. > > >Article: 44348
>> >> 2. Must work on 5V (or higher) > >Interesting request - How much higher - and for what loads ? 10V will be optimal. Current requirements are very very low (250uA is more than enough) > >150 i/o is a lot in one package - what is this driving ? >( are all the loads in one place ? ) > >Is the IO by Serial or parallel BUS, 8 or 16 bits wide ? > >Better may be 32 io in 44 pin packages, and use 5 packages spread on the >board(s). >CPLDs come in 32/64/128/.. macrocells, the better ones can pack a shift >and latch >into one macrocell. Prices are appx $1/32MC Is the price per IO pin goes up with larger CPLD's (e.g. >100 pins) or is it cheaper to have one big CPLD ? We can go both ways depending on which option is cheaper. >> >> 5. Can be easily converted to a mask based equivalent chip (a full >> ASIC is not possible at this stage, maybe for second generation). >> >> 6. Cost of the masked version is very critical (and having a >> reasonable conversion/tooling cost is also very nice to have). > >So too are the volumes :) - what is the budget per I/O pin ? 1c per I/O in large quantities will be OK.Article: 44349
Doug, Very interesting. I believe that if you want a maximal length sequence, one needs to use a primitive polynomial of degree 7 for a GF(128). I am not an expert on this subject, but a book I have read, and keep re-reading is Error Coding Cookbook by C. Britton Rorabaugh. Hope this helps, Newman
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