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Rick Filipkiewicz wrote: > Is there any way of re-wrting the following simple counter code so that > Synplify will merge the or'ed incrementer into the 1st LUT of the adder > chain ? Or am I going to have to instantiate everything ? > > always @(posedge clk) > if (reset) > ra <= 0; > else > ra <= fra; > > wire [5:0] fra = ra + ((count_en[0] | count_en[1]) ? 1 : 0); In fact I think this is a small example of a bigger thing where Synplify fails to take advantage of the Xilinx architecture to synthesise fast [and predictable] wide logic functions using the carry chains. In the same struggle to grind down some timing paths I had to work on this function: reg [8:0] addr, mask; .... assign out = (addr & mask != 0); It had been o.k. when the 2 vectors were only 8 bits but failed when extended to 9. Doing it 2 bits at a time and using the carry chain to propagate and voila ... *that* part of problem solved even unto 10 bits and probably 12. Only downside was having to instantiate the MUXCYs although Synplify 7.x & ModelSim 5.5+ can handle arrays of instances so it wasn't too bad.Article: 44051
John_H wrote:
> Okay, so Synplify is getting edgy about forcing the .CI input...
> I actually synthesized my suggestion and saw your troubles.
> So. Assuming the LUT1_2 elements are all where they're really needed
> (sometimes they aren't), the following code synthesizes great:
>
> module counters ( clk, reset, count_en, ra );
>
> input clk, reset;
> input [1:0] count_en;
> output [5:0] ra;
>
> wire [5:0] fra;
> reg [5:0] ra;
>
> always @(posedge clk)
> if( reset ) ra <= 0;
> else ra <= fra;
>
> assign fra = {ra[5:1],|count_en} + ra[0];
>
> endmodule
>
> You can probably skip the wire and do the addition inline. I just
> convinced the synthesizer to do the carry-in differently by swapping the
> LSbits. Not pretty but it works. The synthesis SHOULD push everything
> into the bottom LUT without a carry-in. At least this way is "better."
>
Nice! I was so focussed on trying to presuade Synplify to put ra[0] and count
into the same LUT I hadn't thought of just getting it to swap the CIN signal.
Just a couple of additional complications:
o Synplify doesn't seem to use the carry chain for the increment-by-1
function for widths < 6. => since I only need width 4 this has to go into a
module of width 6 and throw away 2 bits.
o I use the |count elsewhere so, cunningly, Synplify optimises and uses a
separate LUT for this which it then feeds into the adder !! => the counter
module needs to have syn_hier="hard".
Sometimes its hard to keep to the "pure RTL" paradigm ... sigh ... but maybe
it means there's a whole slew of performance improvements for Synplify v8.
Article: 44052
Since posting a reply about using Spice a while ago, I took a crack
at trying to use an IBIS model within a "free" Spice. The versions of
Spice I've been trying are:
http://sourceforge.net/projects/ngspice/ (under FreeBSD 4.5)
http://www1.linear.com/software/ (SwitcherCad for Windows)
I needed an IBIS to Spice translator, and had located a free one at
the Intusoft web site. This is also a tool that runs under Windows...
http://www.intusoft.com/utilities.htm (IBIS to SPICE converter)
Finally, for completeness, you can convert the SPICE deck back to IBIS
using the NCSU "S2IBIS2" package. In theory, this should give back the
original IBIS file (but it doesn't...)
http://www.eigroup.org/IBIS/tools.htm (pointer to tools)
http://www.eda.org/pub/ibis/s2ibis/s2ibis2_v1.1 (the two files)
The IBIS spec is available at:
http://www.eigroup.org/IBIS/specs.htm
********************************************************************
There have been a couple of requests over the years, as to how to
translate the output of the Intusoft IBIS2SPICE tool, so it can run
under Spice. Spice doesn't have the if-then-else clause used by
IBIS2SPICE, so I had to find another way to input a piecewise
linear data table into Spice. I started with unit step functions,
as they could switch on y=ax+b equations over the appropriate
interval.
When I first tried using unit step functions, I had syntax problems
which would cause both of the above Spice programs to hang in a
loop. I decided to try fitting a mathematical function to
the data instead -- to keep a long story short, the fitting method
wasn't successful, as the curve fitting I tried didn't have a low
enough error compared to the original data. (I tried a high order
Chebyshev polynomial basis set and also a rational P(x)/Q(x)
polynomial fit and both were bad, but for different reasons.)
Eventually, I added a few printf's to ngspice, to determine where in
the three pass parser that Spice was hanging. It turned out that
the current Spice parser doesn't like (a + -b), but does like
(a - b). So, a unary minus is not handled properly. Once I tracked
this down, the rest of the conversion was straight forward.
I've written an awk script that encapsulates the changes needed to
go from the Intusoft IsSpice acceptable format to Spice 3F5
acceptable format. Here is the script entitled "i2sfix.awk". Lines
with a # are comments -- you can snip these if you wish.
Note: I've only tried this with a 3.3V CMOS I/O. I don't know exactly
how many different I/O types the Intusoft tool supports, so other I/O
types are left as an exercise :-)
#****************************** i2sfix.awk *****************************
#
# Intusoft has graciously provided a free tool for converting IBIS
# models back to spice-like form. The "template.mdl" file provided
# with the tool is supposed to be customizable to work with any Spice
# but there are some limitations. There are two options in the
# ibis2spice, to format the power_clamp, gnd_clamp, pullup, and pulldown
# characteristics, and neither option is directly useful in Spice 3F5.
# This awk script finds "chunks" of these piecewise linear tables
# and replaces them with unit step functions. (Select "Option2" in
# the ibis2spice format pulldown.) My efforts have concentrated on
# ngspice (Spice 3F5 based), so I don't know if this will work in 2G6.
# Tested with version 1.4 of ibis2spice (see their Help:About menu).
#
# To use:
# 1) ibis2spice - generate blah.lib from blah.ibs
# select the option that generates lines like
# + (V(1,2) < -3.300 ) ? 1.000n * V(1,2) + -1.286 :
# + (V(1,2) < -3.200 ) ? 540.000m * V(1,2) + 496.000m : ; -3.200 -1.232
#
# 2) Find a copy of awk and execute
#
# awk -f i2sfix.awk blah.lib >blah.fix
#
# 3) Use .include blah.fix in the spice deck, to make the blah subcct
# available for simulation.
# 4) I recommend setting up the test load for the golden
# waveforms in the original blah.ibs and compare the
# waveforms with those obtained from the translated
# model. You may want to adjust the ramp generators RTR / RTF
# to get the rise/fall times listed in the original ibis file
# as the 20% to 80% time.
#
# Note: This conversion script modifies the Intusoft design intent
# slightly. The IBIS standard says only one of XPULLUP or XPULLDOWN
# should be turned on at any one time, so I added an enable pin to
# each model. This turned out to make a difference, only if the
# original model data didn't pass through (0,0). So, for good models,
# this doesn't do anything. Also, I replaced V7 with E7, to isolate
# the switching current from the ramp generators from the output --
# again only theoretically necessary.
#
# PN: June 10, 2002.
BEGIN {
# Please excuse my crappy awk scripting! I'm pretty rusty.
# a_chunk_line is 1 when a piecewise linear table entry is found
a_chunk_line = 0
# in_chunk is 1 when we're somewhere in the middle of a table
in_chunk = 0
# Bracket balance for PULLUP and PULLDOWN
extra_closing_bracket = 0
}
# computed boolean - 1 if matches the first three fields of...
#+ (V(1,2) < 900.000m) ? 27.300m * V(1,2) + 11.270m : ; 900.000m 35.840m
# Done here, as this is common to chunk processing
{ a_chunk_line = ( $1 == "+" && $2 == "(V(1,2)" && $3 == "<" )
# Note: The following adds a space between 900.000m and the ")"
if ( a_chunk_line == 1 ) {
gsub( "m)", "m )", $0 )
}
}
# No case statement in awk, so if-then-else
{ # Simple translations from Intusoft IsSpice to Spice3f5
if ( $1 == "*DEFINE" && $2 == "{RTF}=" ) {
rtf = $3
} else if ( $1 == "*DEFINE" && $2 == "{RTR}=" ) {
rtr = $3
} else if ( $0 == "B1 820 0 V=V(100) & V(500)" ) {
print "* Unit step functions replace the original syntax"
print "B1 820 0 V=2.4*U( V(100)-1.2 )*U( V(500)-1.2 )"
} else if ( $0 == "B2 830 0 V= V(500) & ~V(100)" ) {
print "B2 830 0 V=2.4*U( V(500)-1.2 )*U( 1.2-V(100) )"
} else if ( $1 == "B3" ) {
# B3 300 850 I= V(830) > 1.2 ? 0 : V(300,850) / {RTR}
print "B3 300 850 I=U( 1.2-V(830) )*V(300,850) / " rtr
} else if ( $1 == "B4" ) {
# B4 840 400 I= V(820) > 1.2 ? 0 : V(840,400) / {RTF}
print "B4 840 400 I= U( 1.2-V(820) )*V(840,400) / " rtf
} else if ( $0 == "XPULL_DOWN 2 400 8 840 PULL_DOWN" ) {
print "XPULL_DOWN 2 400 8 840 830 PULL_DOWN"
} else if ( $0 == "XPULL_UP 3 300 850 8 PULL_UP" ) {
print "XPULL_UP 3 300 850 8 820 PULL_UP"
} else if ( $0 == "V5 6 5 " ) {
print "V5 6 5 DC 0.0"
} else if ( $0 == "V6 8 6 " ) {
print "V6 8 6 DC 0.0"
} else if ( $0 == "V7 220 8 " ) {
print "* Using E7 to isolate S1/S2 switching noise from node 8"
print "E7 220 0 8 0 1.0"
} else if ( $0 == ".SUBCKT PULL_UP 3 4 1 2" ) {
print "* Added enable signal to PULL_UP model"
print ".SUBCKT PULL_UP 3 4 1 2 5"
print "* Connections Out+ Out In+ In Enable"
getline
} else if ( $0 == "BPULL_UP 3 4 V=" ) {
print "BPULL_UP 3 4 V=U( V(5)-1.2 )*("
extra_closing_bracket = 1
} else if ( $0 == ".SUBCKT PULL_DOWN 3 4 1 2" ) {
print "* Added enable signal to PULL_DOWN model"
print ".SUBCKT PULL_DOWN 3 4 1 2 5"
print "* Connections Out+ Out In+ In Enable"
getline
} else if ( $0 == "BPULL_DOWN 3 4 V=" ) {
print "BPULL_DOWN 3 4 V=U( V(5)-1.2 )*("
extra_closing_bracket = 1
} else if ( $1 == ".ENDS" ) {
extra_closing_bracket = 0
print
} else if ( a_chunk_line == 1 && in_chunk == 0 ) {
# + (V(1,2) < -3.300 ) ? 1.000n * V(1,2) + -1.000m :
# First line of a table. Only needs one unit step to handle
# less than or equal to this voltage. Intusoft adds this
# entry to define voltages outside the defined range.
in_chunk = 1
# Spice hates unary - and + !
if ( substr($11,1,1) == "-" ) {
sub( "-", "", $11 )
$10 = "-"
}
printf("+ U( %s-V(1,2) )*( %s%s%s%s%s )\n",
$4, $7, $8, $9, $10, $11)
# Now, remember the voltage limit used,
# for lines other than the first or last of a chunk.
lower_v = $4
} else if ( a_chunk_line == 1 && in_chunk == 1 ) {
# + (V(1,2) < -2.500 ) ? -500.000u * V(1,2) + -2.050m
sign = "-"
if ( substr(lower_v,1,1) == "-" ) {
sub( "-", "", lower_v )
sign = "+"
}
if ( substr($11,1,1) == "-" ) {
sub( "-", "", $11 )
$10 = "-"
}
# 2nd to n-1 th line case.
# The first of two plus signs is the "continuation" character.
printf("++ ( U( V(1,2)%s%s )+U( %s-V(1,2) )-1 )*",
sign, lower_v, $4)
printf("( %s%s%s%s%s )\n", $7, $8, $9, $10, $11)
lower_v = $4
} else if ( a_chunk_line == 0 && in_chunk == 1 ) {
# last line of a chunk. Intusoft adds this entry to define
# voltages outside the defined range (a good thing).
# + 1.000n * V(1,2) + -1.300
sign = "-"
if ( substr(lower_v,1,1) == "-" ) {
sub( "-", "", lower_v )
sign = "+"
}
if ( substr($6,1,1) == "-" ) {
sub( "-", "", $6 )
$5 = "-"
}
printf("++ U( V(1,2)%s%s )*( %s%s%s%s%s )",
sign, lower_v, $2, $3, $4, $5, $6)
if (extra_closing_bracket == 1) {
print " )"
} else {
print ""
}
in_chunk = 0
# invalidate lower_v - this value should never be printed
lower_v = "FIX_ME"
} else { # for all other lines, just print them
print
}
}
#************************** end i2sfix.awk *****************************
(I placed a PostScript picture in a second post. This text description
is with respect to the picture, so convert the "part 2" post before
reading this...)
I understand some of this model, but not all of it. The model starts in
the upper right corner. Two logic gates (emulated with unit step
functions), turn on the upper or the lower half of the driver circuit.
The rise and fall times of the model are controlled by the ramp
generators (upper and lower left corners of the figure).
Before a 0 to 1 transition, switch S1 is closed, which causes node 850
to be at 0.0 volts. When the INPUT changes from 0 to 1 (and ENABLE is
asserted), switch S1 releases, and the B3 switched resistor is turned
on. B3 pulls the lower side of capacitor C1 to the plus rail, with time
constant RTR*C1 (parameter RTR is the rise time in the IBIS file).
When the ramp reaches the positive rail voltage, the XPULLUP applies
the full value of the lookup table inside it. The "force" applied is
a function of how much difference there is between the current output
voltage (node 8) and the voltage the driver is trying to make (the
logic 1 provided by node 850). When the driver output (as seen at node
8) reaches the positive rail, XPULLUP stops requesting more drive.
The PULLUP drive consists of several conversion steps. The input to
XPULLUP is effectively Vtable = VCC-Voutput, and since XPULLUP is a
VCVS (voltage controlled voltage source), a voltage is produced which
is referenced to the positive rail. This, in turn, is applied to
VCCS (voltage controlled current source) G2, which has a 1:1 gain. If
XPULLUP outputs 1 volt, then G2 will output 1 amp. Now, the curious
part is the role of resistors R1 and R2. Instinct says they are being
used to convert from current to voltage (as if a voltage source is
desired as the output characteristic of the driver). By using S2IBIS2,
the proper output impedance characteristic is seen, looking into this
network (because it is the slope of V versus I that counts, as opposed
to the instantaneous value). However, be aware that if you are using
node 300 to monitor power consumption, you will find too much current
flowing into this node.
I tried constructing my own driver, by using a B element to place a
non-linear resistance between the positive rail and the output node,
and the output waveform had the right shape, but it had small
stairsteps along its edge. So, the voltage-current-voltage chain used
by Intusoft has more merit than going directly with a non-linear
resistor.
Another question is the design of the ramp generator. To me, the shape
of the ramp is arbitrary. Intusoft chose an RC charging curve, whereas
I would have chosen a linear ramp (which can be achieved with
a switched constant current source into a capacitor). A linear ramp
would at least make it easier to adjust the subcircuit to get the
correct value of rise/fall times. I don't think the IBIS spec defines
how PULLUP or PULLDOWN turn on.
Voltage sources V7, V6, and V5 are zero volt sources, used to allow
Spice to monitor the current flow. The XPWRCLAMP and XGNDCLAMP are
non-linear resistors which are always enabled, and these give the
clamping characteristic of the input gate ESD protection diodes.
************************************************************************
Miscellaneous notes:
Software issues:
1a) ngspice:
The LTRA transmission line doesn't work in ngspice-rework14. Since
I don't understand all the matrix stuff/time steps/Newton-Raphson in
Spice, I don't know exactly why. What I notice is that someone has
removed some heuristic time stepping cruft from the original code and
replaced it with a simplified approach. The observed symptoms are that
at the propagation delay time of the line (24 inches would be roughly
4.4ns), I get a "time step too small" error. I can change the PULSE
source delay from the shown value of 1ns, and the time step error
still occurs at 4.38ns. Here is a test deck (that works in
SwitcherCad). This test is of a matched series damped termination
into a transmission line. It should give a delayed and correct
amplitude signal at the output node 3.) Placing loads on the output of
the transmission line doesn't help. The option method=gear usually
helps with time step too small problems.
From ltra_1.cir of Spice3F5, simplified, 24inch lossy line
.options method=gear
v1 1 0 pulse(0 4 1ns 1ns 1ns 20ns 40ns)
rseries 1 2 50
o2 2 0 3 0 lline
.model lline ltra r=0.2 g=0 l=9.13e-9 c=3.65e-12 len=24 truncnr
.save v(1) v(2) v(3)
.tran 0.01ns 60ns 0 0.1ns
.end
doAnalyses: TRAN: Timestep too small; time = 4.3812e-09,
timestep = 1.25e-22: cause unrecorded.
1b) ngspice:
Parser has a few problems. Firstly, for B models, if there is a syntax
error, ngspice will hang without printing any details about the error.
In particular, expressions of the form (a + -b) cause problems. To
debug this, I added printf statements to inppas1.c, inppas2.c, and
inppas3.c, to identify where the hang might be occurring. I changed
the source deck to suit the parser.
1c) ngspice:
Include files don't work. If you place ".include blah.lib" in the main
.cir file, the program complains about freeing some pointer. This
turned out to be an uninitialized pointer in inpcom.c. The fix was
"copys = NULL" just before "if (*s == '~')".
2a) s2ibis2:
The program had trouble creating the golden waveforms for the IBIS
file. Turned out that it was duplicating its own dummy node names.
In s2ispice.c, around line 2137, there are some references to
nodelist[]. There is a potential order of evaluation problem, as
"nodelist[nodeIndex]" and "nodeList[++nodeIndex]" appear in the same
line. I changed the second one to "nodeList[nodeIndex+1]" and did
the increment in a separate statement. There are multiple lines
like this.
s2ibis2 also has some strange ideas about data reduction. The IBIS
standard says that tables should have 100 or fewer entries. s2ibis2
removes data points from the table according to its own definition
of "interesting" areas of the curve. This is dangerous, because it
assumes that no one will be using a novel pad design. This is why
some commercial IBIS files are missing data between -1.0 and -1.5
volts. If you are making IBIS models professionally, I'd consider
taking this clever code out. Similarly, there are comparisons to
"clamptol" and the like, for current values in V/I tables. Why
not just leave the data points alone, in the form they were
delivered from the spice simulation? Changing the data can
affect the following test...
Right now, if I use IBIS2SPICE, followed by s2ibis2, I don't get
back the original driver impedance characteristic. I'm not sure
the IBIS standard is rigorous enough to pass this test. Maybe
someone who has access to HSPICE can test s2ibis2 against the
HSPICE built-in IBIS conversion method, to see if it is possible
to get back an IBIS model with the same drive strength.
(When downloading the source, there is a fix file as well, which
has a replacement source file. Do "make depend" and "make sun4"
if using FreeBSD. You may also want to set YACC=yacc.)
3a) Switchercad:
I'm getting the occasional internal error from this program, while
running a converted ibis subckt along with a length of LTRA
transmission line. The message is "internal error #62 - read 20480
expected 22876". I'm using version 1.12j. The workaround is to
restart the program and try again. The output of the LTRA model
reminds me of stuff I was seeing 10 years ago -- it is not the
same as Hspice and seems too pessimistic when it comes to
reflections. So, the final hurtle to a free simulation environment
is finding a better transmission line model. (Some suggests of how
to do this can be found in the ltra test circuits in the examples
directory of the Berkeley 3F5 package.
See ftp://ic.eecs.berkeley.edu/pub/Spice3/sp3f4.kit.tar.Z which
contains these examples. I haven't tried the alternatives yet.)
Enjoy,
Paul
Article: 44053Hi all, firstly apologies for the double post; but i'm having a bit of difficulty: I've already tried Xilinx Forum with this one and no luck there either! I need some feedback on a problem: I have just moved from a -5 Spartan II to the faster -6... not a big change, i know, but I have observed a strange effect in two test cards; the PCB is not to blame, it is something more sinister than that... I am using tried and tested circuit techniques, that work well in other designs, but for some reason i've managed to break two Spartan-II FPGA in as many days: Firstly the symptoms: when I first power up the FPGA, a pin (number 41 in the TQ144 package) becomes connected to both GND and VCCO - causing a short circuit. physiclly this pin is +5 or 0V, admittedly this is higher than 3.3V (VCCO) but why should it cause the FPGA to break like this? What should I change on my PCB to stop this happenning again? Anyways I thought that all pins on the FPGA, not connected with the configuration were high-Z before configuration was completed? I also thought that Spartan II was 5 v compliant? Could this be to do with the 1.8A current spike I have read about on various newsgroups? I have a regulator that can deliver 1.0A per channel (i.e. both on VCCO and VCCINT) would you think that is too low (although the junction temperature is definitely above freezing)? any suggestions more than welcome Many thanks for any feedback. -- Benjamin Todd European Organisation for Particle Physics SL SPS/LHC -- Control -- Timing Division CERN, Geneva, Switzerland, CH-1211 Building 864 Room 1 - A24Article: 44054
This figure is to accompany the text description in my previous post.
It is a PostScript picture of the Intusoft subcircuit representation
of the IBIS driver. The picture should be viewable in GhostScript or
distillable with Acrobat Distiller. Keep everything from
"%!PS-Adobe-3.0" to "%%EOF".
***************** Intusoft IBIS2SPice Subcct Schematic *****************
%!PS-Adobe-3.0
%%BeginResource: procset (Tailor_Mac_Gen) 2.0 7
/TailorDict 200 dict def TailorDict begin/bd{bind def}bind def/ld{load
def}bd/setoverprint where{pop}{/setoverprint{pop}bd}ifelse/setcmykcolor
where{pop}{/setcmykcolor{1 exch sub dup dup 6 -1 roll sub dup 0 lt{pop
0}if 5 1 roll 4 -1 roll sub dup 0 lt{pop 0}if 3 1 roll exch sub dup
0 lt{pop 0}if setrgbcolor}bd}ifelse/TailorGroupBegin{pop}bd
/TailorGroupEnd{}bd/TailorSetUniformStroke{pop}bd/TailorSetSpotColor
{pop pop}bd/setdefaults{0 setgray false setoverprint 1 setlinewidth 0
setlinecap 0 setlinejoin 10 setmiterlimit[]0 setdash false
TailorSetUniformStroke M0 setmatrix 1 0 0 1 0 0 M1 astore pop}bd/S0 0
def/M0 matrix def/M1 matrix def/BP {/S0 save def 0 ne{90 rotate 0 6
index neg translate}if translate 0 eq{pop pop pop pop}{moveto 1 index
0 rlineto 0 exch rlineto neg 0 rlineto closepath clip newpath}ifelse M0
currentmatrix pop setdefaults}bd/EP {S0 restore}bd/BG{TailorGroupBegin}
bd/EG{TailorGroupEnd}bd/BM{gsave TailorGroupBegin}bd/EM{TailorGroupEnd
grestore setdefaults}bd/N{M0 setmatrix 1 0 0 1 0 0 M1 astore pop}bd/M
{M0 setmatrix M1 astore concat}bd/X{M0 setmatrix M1 exch 4 exch put M1
concat}bd/Y{M0 setmatrix M1 exch 5 exch put M1 concat}bd/Z{M0 setmatrix
M1 exch 5 exch put M1 exch 4 exch put M1 concat}bd/G{setgray}bd
/R{setrgbcolor}bd/K{setcmykcolor}bd/S{TailorSetSpotColor}bd/O
{0 ne setoverprint}bd/W/setlinewidth ld/C/setlinecap ld/J/setlinejoin
ld/L/setmiterlimit ld/D/setdash ld/U {0 ne TailorSetUniformStroke}bd
/m/moveto ld/l/lineto ld/c/curveto ld /h/closepath ld/r/stroke ld
/f/fill ld/g/eofill ld/p{clip newpath}bd/q{eoclip newpath}bd end
%%EndResource
%%BeginResource: procset (Tailor_Mac_Text) 2.0 7
TailorDict begin/TailorEncoding[StandardEncoding 0 39 getinterval aload
pop/quotesingle StandardEncoding 40 56 getinterval aload pop/grave
StandardEncoding 97 31 getinterval aload pop 128{/.notdef}repeat]def
/EncodingsDict 0 def/BE{/EncodingsDict exch dict def}bd/DE
{TailorEncoding 256 array copy dup 128 4 -1 roll putinterval
EncodingsDict 3 1 roll put}bd/FontsDict 0 def/BF{/FontsDict exch dict
def}bd/EF{cvn findfont dup length dict begin{1 index/FID ne{def}{pop
pop}ifelse}forall dup type/nametype eq{/Encoding exch EncodingsDict
exch get def}{pop}ifelse dup currentdict end definefont dup setfont
FontsDict 3 1 roll put}bd/F{FontsDict exch get setfont}bd/s{0.0 0.0
moveto show}bd/a{0.0 0.0 moveto exch 1000.0 div exch 0.0 exch ashow}bd
/b{0.0 0.0 moveto 3 1 roll 1000.0 div 3 1 roll 1000.0 div 3 1 roll
ashow}bd/v{0.0 0.0 moveto 3 2 roll 1000.0 div 0.0 4 2 roll widthshow}bd
/w{0.0 0.0 moveto 4 2 roll 1000.0 div 4 1 roll 1000.0 div 4 1 roll
widthshow}bd/z{0.0 0.0 moveto 6 1 roll 1000.0 div 6 1 roll 1000.0 div 6
2 roll 1000.0 div 6 1 roll 1000.0 div 6 1 roll awidthshow}bd end
%%EndResource
%%BeginPageSetup
TailorDict begin 576 694 0 0 0 0 0 0 BP 1 BE 1 BF
%%EndPageSetup
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27.91667 (Clamp)a 180 650 Z 14.16667 0 32 1.416667 0
(Intusoft IBIS2SPICE I/O Driver Subcct)z EM EP end showpage
%%PageTrailer
%%Trailer
%%EOF
************* end Intusoft IBIS2SPice Subcct Schematic *****************
Article: 44055
This figure is to accompany the text description in my previous post.
It is a PostScript picture of the Intusoft subcircuit representation
of the IBIS driver. The picture should be viewable in GhostScript or
distillable with Acrobat Distiller. Keep everything from
"%!PS-Adobe-3.0" to "%%EOF".
***************** Intusoft IBIS2SPice Subcct Schematic *****************
%!PS-Adobe-3.0
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%%BeginResource: procset (Tailor_Mac_Text) 2.0 7
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(Intusoft IBIS2SPICE I/O Driver Subcct)z EM EP end showpage
%%PageTrailer
%%Trailer
%%EOF
************* end Intusoft IBIS2SPice Subcct Schematic *****************
Article: 44056Hello folks, I have a design that ISE 4.1.03i reports as having a maximum clock freq. of 103.082MHz after par. This is achieved by setting the clock period as follows in my UCF: TIMESPEC "TS_CLK" = PERIOD "CLK" 10 ns HIGH 50 %; i.e. I am looking for 100MHz. Here is the mad thing: if I set the clk period contstraint to 7.5 ns (133MHz) instead of 10, the maximum frequency comes out as 95.274MHz !!!!!! Why? Surely if I ask for a higher clock rate that cannot be met by the tools then at worst the tools should maintain my 103.082 MHz max freq and just report all paths that are preventing the design reaching the higher rate - thus allowing me to try and tweak these paths in some way to kcik them into shape! Or have I missed a trick somewhere? Thanks for your time, KenArticle: 44057
I think the router gives up if it notices that further iterations are not closing in on the goal. If it sees that it MIGHT make it, it will continue, and if it is nowhere close, it will give up early. This is partly speculation. Like, you would work harder to date the waitress across the street than you would to date Heidi Klum, because you have no chance at all with Heidi, but it's possible the waitress might say yes. Usually it's bad to overconstrain. "Ken Mac" <aeu96186@yahoo.co.uk> wrote in message news:ae4k8u$p6e$1@dennis.cc.strath.ac.uk... > > Hello folks, > > I have a design that ISE 4.1.03i reports as having a maximum clock freq. of > 103.082MHz after par. This is achieved by setting the clock period as > follows in my UCF: > > TIMESPEC "TS_CLK" = PERIOD "CLK" 10 ns HIGH 50 %; > > i.e. I am looking for 100MHz. > > Here is the mad thing: if I set the clk period contstraint to 7.5 ns > (133MHz) instead of 10, the maximum frequency comes out as 95.274MHz !!!!!! > > Why? Surely if I ask for a higher clock rate that cannot be met by the > tools then at worst the tools should maintain my 103.082 MHz max freq and > just report all paths that are preventing the design reaching the higher > rate - thus allowing me to try and tweak these paths in some way to kcik > them into shape! > > Or have I missed a trick somewhere? > > Thanks for your time, > > Ken > >Article: 44058
You can get a SpartanII XC2S50 for between $14 and $20 depending on the
package, and that gives you about 15x the gate capacity, plus RAM
capabilities, plus is supported by the current free tools. You'll spend
way more than that $10 difference trying to find a programming solution
for the antique parts. The cheapest package is, IIRC, the TQ144 package
which you can reasonably handle putting on the board manually. There is
also a PQ208 package which is also more hobbyist friendly than the ball
grid arrays. My guess is that you'll wind up spending more than the
$100 budget in the process of making a board that is suitable to
reliable operation of an FPGA. If you are really bent on using the
3030, there are lots of the old xilinx eval boards around with those on
it that you could probably get for not much more than the $4 you are
spending for the part. Again, the trouble comes with programming it.
Thijs wrote:
> >The 3030A is an antique, and is not supported with the current
> >tools. The cost of the board and support for programming the part
> >is going to cost you much more than the part itself. Very
> >seriously consider instead working with one of the current parts
> >such as the SpartanII. There are a number of eval boards with
> >current parts available on the market for under $200 that are
> >compatible with the free development software available on the FPGA
> >vendor sites.
>
> thanks, but i could get this 3030 for about $4, it's just for
> a hobby project, so buying a board for $100 or more is way
> out of my budget.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44059Kevin Neilson wrote: > I think the router gives up if it notices that further iterations are not > closing in on the goal. If it sees that it MIGHT make it, it will continue, > and if it is nowhere close, it will give up early. This is partly > speculation. > This is correct [a change in behaviour between the 3.x and 4.x tools] and there's a magic env variable you can set to tell PAR to not give up and continue with the number it iterations you've defined with the -i flag. For Windows set XIL_ROUTE_CONTINUE_ON_DESIGN_IMPOSSIBLE=1; but generally, after the first routing 2-3 iterations, PAR doesn't make much more progress beyond a few 100s of ps per failing route. > > Like, you would work harder to date the waitress across the street than you > would to date Heidi Klum, because you have no chance at all with Heidi, but > it's possible the waitress might say yes. > > Usually it's bad to overconstrain. > To continue the analogy - using huge amounts of effort if the futile chase for Heidi Klum can cause the rest of your life to fall apart.Article: 44060
Greetings, I'm using a xi 4000 series and I'm trying to get the reset synchronous e.g. by using the following process (D-flip flop) process(clock) begin if(Clock'event and Clock = '1') then Reset_synchr <= Reset_asynchr; end if; end process; When I try to implement it, foundation complains that it can't find a general reset (other processes use the reset_synchr signal to reset). But when I have to put some reset on my D -flip flop then my reset is actually not synchronous anymore or is it? JerreArticle: 44061
Hi all, I interface FPGAs/CPLDs quite frequently to various types of memory. The wide busses regularly mess up the routing resources when the device approaches 100% utilization. Things are bad in CPLDs and worse in FPGAs. Now, I know that I don't care about the bit order on the memory busses, but the fitter software always does. One option is to not constrain the pins, but that means PCB redesign. My wish is to be able to constrain a group of signals (e.g. a bus) to a group of pins. That way, the fitter has more freedom and I don't have to change the board. Do any of the available tools support this? Kind regards, IwoArticle: 44062
Some more weird results: If I put 9.24 ns as my period in UCF, I get a min period of 9.128 ns after par (109.553MHz). If I then put in 9.128 ns in UCF I get a min period of 9.694 ns after par (103.157MHz). So - with a bit of black magic and stabbing in the dark I will find my max clock rate! Ken "Kevin Neilson" <kevin-neilson@removethistextattbi.com> wrote in message news:6KkN8.12115$6m5.1979@rwcrnsc51.ops.asp.att.net... > I think the router gives up if it notices that further iterations are not > closing in on the goal. If it sees that it MIGHT make it, it will continue, > and if it is nowhere close, it will give up early. This is partly > speculation. > > Like, you would work harder to date the waitress across the street than you > would to date Heidi Klum, because you have no chance at all with Heidi, but > it's possible the waitress might say yes. > > Usually it's bad to overconstrain. > > "Ken Mac" <aeu96186@yahoo.co.uk> wrote in message > news:ae4k8u$p6e$1@dennis.cc.strath.ac.uk... > > > > Hello folks, > > > > I have a design that ISE 4.1.03i reports as having a maximum clock freq. > of > > 103.082MHz after par. This is achieved by setting the clock period as > > follows in my UCF: > > > > TIMESPEC "TS_CLK" = PERIOD "CLK" 10 ns HIGH 50 %; > > > > i.e. I am looking for 100MHz. > > > > Here is the mad thing: if I set the clk period contstraint to 7.5 ns > > (133MHz) instead of 10, the maximum frequency comes out as 95.274MHz > !!!!!! > > > > Why? Surely if I ask for a higher clock rate that cannot be met by the > > tools then at worst the tools should maintain my 103.082 MHz max freq and > > just report all paths that are preventing the design reaching the higher > > rate - thus allowing me to try and tweak these paths in some way to kcik > > them into shape! > > > > Or have I missed a trick somewhere? > > > > Thanks for your time, > > > > Ken > > > > > >Article: 44063
Is 20,000 gates enough for creating a nice project? What are some projects one can create by using 20,000 gates? I am trying to decide if 20,000 gates fpga board would be sufficient for a hobbyist that wants to use it for about 2 years. I have another question. How many megs of RAM will I be able to develop using 20,000 gates fpga? I mean if I want to use the fpga as a ram.Article: 44064
Which Spartan part exactly? Damir "Benjamin Todd" <Benjamin.Todd@cern.ch> wrote in message news:ae4ii0$9nt$1@sunnews.cern.ch... > Hi all, firstly apologies for the double post; but i'm having a bit of > difficulty: I've already tried Xilinx Forum with this one and no luck there > either! > > I need some feedback on a problem: > > I have just moved from a -5 Spartan II to the faster -6... not a big change, > i know, but I have observed a strange effect in two test cards; the PCB is > not to blame, it is something more sinister than that... > > I am using tried and tested circuit techniques, that work well in other > designs, but for some reason i've managed to break two Spartan-II FPGA in as > many days: > > Firstly the symptoms: when I first power up the FPGA, a pin (number 41 in > the TQ144 package) becomes connected to both GND and VCCO - causing a short > circuit. physiclly this pin is +5 or 0V, admittedly this is higher than > 3.3V (VCCO) but why should it cause the FPGA to break like this? > What should I change on my PCB to stop this happenning again? > Anyways I thought that all pins on the FPGA, not connected with the > configuration were high-Z before configuration was completed? > I also thought that Spartan II was 5 v compliant? > > Could this be to do with the 1.8A current spike I have read about on various > newsgroups? I have a regulator that can deliver 1.0A per channel (i.e. both > on VCCO and VCCINT) > would you think that is too low (although the junction temperature is > definitely above freezing)? > > any suggestions more than welcome > Many thanks for any feedback. > -- > Benjamin Todd > European Organisation for Particle Physics > SL SPS/LHC -- Control -- Timing Division > CERN, Geneva, Switzerland, CH-1211 > Building 864 Room 1 - A24 > >Article: 44065
I did something creative with a ( val[23:3]<(en?17:9) ) kind of
quantity. Try a structure like:
assign out = { addr[ 8] & mask[ 8]
, addr[7:6] & mask[7:6]
, addr[5:4] & mask[5:4]
, addr[3:2] & mask[3:2]
, addr[1:0] & mask[1:0]
} < 5'h1;
I'm using the < in your example rather than the == because Synplify
*used* to not implement the equality. Maybe it does now. If I had my
synthesizer in front of me I'd try it for you.
Rick Filipkiewicz wrote:
>
> Rick Filipkiewicz wrote:
>
> > Is there any way of re-wrting the following simple counter code so that
> > Synplify will merge the or'ed incrementer into the 1st LUT of the adder
> > chain ? Or am I going to have to instantiate everything ?
> >
> > always @(posedge clk)
> > if (reset)
> > ra <= 0;
> > else
> > ra <= fra;
> >
> > wire [5:0] fra = ra + ((count_en[0] | count_en[1]) ? 1 : 0);
>
> In fact I think this is a small example of a bigger thing where Synplify
> fails to take advantage of the Xilinx architecture to synthesise fast [and
> predictable] wide logic functions using the carry chains. In the same
> struggle to grind down some timing paths I had to work on this function:
>
> reg [8:0] addr, mask;
> ....
>
> assign out = (addr & mask != 0);
>
> It had been o.k. when the 2 vectors were only 8 bits but failed when
> extended to 9. Doing it 2 bits at a time and using the carry chain to
> propagate and voila ... *that* part of problem solved even unto 10 bits and
> probably 12. Only downside was having to instantiate the MUXCYs although
> Synplify 7.x & ModelSim 5.5+ can handle arrays of instances so it wasn't
> too bad.
Article: 44066Spartan II TQ144 -6 (Commercial) "Damir Danijel Zagar" <dzagar@srce.hr> wrote in message news:ae51kc$qck$1@sunce.iskon.hr... > Which Spartan part exactly? > > Damir > > "Benjamin Todd" <Benjamin.Todd@cern.ch> wrote in message > news:ae4ii0$9nt$1@sunnews.cern.ch... > > Hi all, firstly apologies for the double post; but i'm having a bit of > > difficulty: I've already tried Xilinx Forum with this one and no luck > there > > either! > > > > I need some feedback on a problem: > > > > I have just moved from a -5 Spartan II to the faster -6... not a big > change, > > i know, but I have observed a strange effect in two test cards; the PCB is > > not to blame, it is something more sinister than that... > > > > I am using tried and tested circuit techniques, that work well in other > > designs, but for some reason i've managed to break two Spartan-II FPGA in > as > > many days: > > > > Firstly the symptoms: when I first power up the FPGA, a pin (number 41 in > > the TQ144 package) becomes connected to both GND and VCCO - causing a > short > > circuit. physiclly this pin is +5 or 0V, admittedly this is higher than > > 3.3V (VCCO) but why should it cause the FPGA to break like this? > > What should I change on my PCB to stop this happenning again? > > Anyways I thought that all pins on the FPGA, not connected with the > > configuration were high-Z before configuration was completed? > > I also thought that Spartan II was 5 v compliant? > > > > Could this be to do with the 1.8A current spike I have read about on > various > > newsgroups? I have a regulator that can deliver 1.0A per channel (i.e. > both > > on VCCO and VCCINT) > > would you think that is too low (although the junction temperature is > > definitely above freezing)? > > > > any suggestions more than welcome > > Many thanks for any feedback. > > -- > > Benjamin Todd > > European Organisation for Particle Physics > > SL SPS/LHC -- Control -- Timing Division > > CERN, Geneva, Switzerland, CH-1211 > > Building 864 Room 1 - A24 > > > > > >Article: 44067
t.t.withaar@student.etc.etc (Thijs) wrote in message news:<3d05a467.1112599@news.student.utwente.nl>... > >The 3030A is an antique, and is not supported with the current > >tools. The cost of the board and support for programming the part > >is going to cost you much more than the part itself. Very > >seriously consider instead working with one of the current parts > >such as the SpartanII. There are a number of eval boards with > >current parts available on the market for under $200 that are > >compatible with the free development software available on the FPGA > >vendor sites. > > thanks, but i could get this 3030 for about $4, it's just for > a hobby project, so buying a board for $100 or more is way > out of my budget. I think that the tail is wagging the dog. You are willing to commit a lot of your time in order to utilize a $4 part with a dead end process. NewmanArticle: 44068
20k gates is awfully tiny for what's readily available these days. You can get evaluation boards at reasonable cost with a small 40k gates and advanced features (including 72kbits RAM) or 300k gates and good features (including 64kbits RAM) using the Xilinx devices. You can find links to demo boards in this newsgroup - search groups.google.com for full history. Keep in mind these gate numbers (as with all demo boards) are "marketing gates" and don't necessarily reflect reality. The number of flops may be more interesting. I'm not familiar with demo boards with other manufacturers' devices, but they are out there and they are affordable. Different hobbyists have different scales of "fun" in their projects. I'd probably go with the Spartan-IIE 300 based eval board, myself. Good speed, decent cost, healthy functionality. You might be able to do all you need with the WebPack tool at no cost (?). Happy hobbying! Roger King wrote: > Is 20,000 gates enough for creating a nice project? What are some projects > one can create by using 20,000 gates? I am trying to decide if 20,000 gates > fpga board would be sufficient for a hobbyist that wants to use it for about > 2 years. > > I have another question. How many megs of RAM will I be able to develop > using 20,000 gates fpga? I mean if I want to use the fpga as a ram.Article: 44069
I recently discovered the Xilinx LOC constraint can apply to a group of signals. I ended up specifying all the pads in a single IOB group as my LOC groups to help me keep track of which signals are on which rows. The group capability was a nice discovery. Iwo Mergler wrote: > Hi all, > > I interface FPGAs/CPLDs quite frequently to various types > of memory. The wide busses regularly mess up the routing > resources when the device approaches 100% utilization. Things > are bad in CPLDs and worse in FPGAs. > > Now, I know that I don't care about the bit order on the > memory busses, but the fitter software always does. One > option is to not constrain the pins, but that means PCB > redesign. > > My wish is to be able to constrain a group of signals > (e.g. a bus) to a group of pins. That way, the fitter > has more freedom and I don't have to change the board. > > Do any of the available tools support this? > > Kind regards, > > IwoArticle: 44070
Aren't modern tool results great? Ken Mac wrote: > Some more weird results: > > If I put 9.24 ns as my period in UCF, I get a min period of 9.128 ns after > par (109.553MHz). > > If I then put in 9.128 ns in UCF I get a min period of 9.694 ns after par > (103.157MHz). > > So - with a bit of black magic and stabbing in the dark I will find my max > clock rate! > > KenArticle: 44071
"Roger King" <roger@king.com> schrieb im Newsbeitrag news:CUmN8.248826$ah_.140060@news01.bloor.is.net.cable.rogers.com... > Is 20,000 gates enough for creating a nice project? What are some projects > one can create by using 20,000 gates? I am trying to decide if 20,000 gates > fpga board would be sufficient for a hobbyist that wants to use it for about > 2 years. You can do a lot for funny things with 20k gates, but why using such a small device? You can get 200k gates for 99$, which is very cheap. www.nuhorizons.com Its a nice board. To develop for such a device, 128 MB of RAM are good, but more is always welcome. -- MfG FalkArticle: 44072
What about the 50,000 gate Spartan2 board from xess? "John_H" <johnhandwork@mail.com> wrote in message news:3D06235A.F1E32B99@mail.com... > 20k gates is awfully tiny for what's readily available these days. You can get > evaluation boards at reasonable cost with a small 40k gates and advanced > features (including 72kbits RAM) or 300k gates and good features (including > 64kbits RAM) using the Xilinx devices. You can find links to demo boards in > this newsgroup - search groups.google.com for full history. Keep in mind these > gate numbers (as with all demo boards) are "marketing gates" and don't > necessarily reflect reality. The number of flops may be more interesting. I'm > not familiar with demo boards with other manufacturers' devices, but they are > out there and they are affordable. > > Different hobbyists have different scales of "fun" in their projects. I'd > probably go with the Spartan-IIE 300 based eval board, myself. Good speed, > decent cost, healthy functionality. You might be able to do all you need with > the WebPack tool at no cost (?). > > Happy hobbying! > > > Roger King wrote: > > > Is 20,000 gates enough for creating a nice project? What are some projects > > one can create by using 20,000 gates? I am trying to decide if 20,000 gates > > fpga board would be sufficient for a hobbyist that wants to use it for about > > 2 years. > > > > I have another question. How many megs of RAM will I be able to develop > > using 20,000 gates fpga? I mean if I want to use the fpga as a ram. >Article: 44073
The Spartan2 is a great part. The difference in cost between an XC2S50 and an XC2S300E is a fraction of any demo board price. I don't know any specific demo boards but the xess board should be very capable for many projects. Roger King wrote: > What about the 50,000 gate Spartan2 board from xess? > > "John_H" <johnhandwork@mail.com> wrote in message > news:3D06235A.F1E32B99@mail.com... > > 20k gates is awfully tiny for what's readily available these days. You > can get > > evaluation boards at reasonable cost with a small 40k gates and advanced > > features (including 72kbits RAM) or 300k gates and good features > (including > > 64kbits RAM) using the Xilinx devices. You can find links to demo boards > in > > this newsgroup - search groups.google.com for full history. Keep in mind > these > > gate numbers (as with all demo boards) are "marketing gates" and don't > > necessarily reflect reality. The number of flops may be more interesting. > I'm > > not familiar with demo boards with other manufacturers' devices, but they > are > > out there and they are affordable. > > > > Different hobbyists have different scales of "fun" in their projects. I'd > > probably go with the Spartan-IIE 300 based eval board, myself. Good > speed, > > decent cost, healthy functionality. You might be able to do all you need > with > > the WebPack tool at no cost (?). > > > > Happy hobbying! > > > > > > Roger King wrote: > > > > > Is 20,000 gates enough for creating a nice project? What are some > projects > > > one can create by using 20,000 gates? I am trying to decide if 20,000 > gates > > > fpga board would be sufficient for a hobbyist that wants to use it for > about > > > 2 years. > > > > > > I have another question. How many megs of RAM will I be able to develop > > > using 20,000 gates fpga? I mean if I want to use the fpga as a ram. > >Article: 44074
Hello, this question may be stupid, I think What happens with CCLK when in Asynchronous Pheriperal Mode (010)? AFAIK, in the other modes CCLK counts until n, where n is the lenght of the bitstream. So, in this mode, CCLK should be counting in something as bursts? To clarify, suppose that I send a byte of data, wait for the RDY/-BUSY to go high, send another byte, etc. and between every byte my delay is variable, suppose, 2us to 3 or 4us. CCLK should count at the internal rate, stop until the FPGA accepts a new byte, count again, etc? If that were not the case, what could happen if I wait too much without sending data to the FPGA? Note: I am using a XC4010XL FPGA Thank you very much Mauricio Lange
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