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"Peter Alfke" <peter.alfke@xilinx.com> ha scritto nel messaggio news:3CC46ACE.53D03EC8@xilinx.com... > suggesting you > make a fast, monotonic power supply. If you can alter > your power supply > easily, I recommend it. I can't, I'm in production stage. Unfortunately this problem appeared only in this revision (probably it is due to board design, which is very chaotic, and the power rise is indeed very noisy). > First, if you supply us the date code (basically all of > the writing on > the top of the chip) Here it is: XC95144XL TQ144BEN0209 F1207470A 10I > Second, as you noted, the JTAG command > basically > "heals" the device. I wasn't clear in the first message: the JTAG emulator is connected only to the CPU (a TI's DSP; I haven't connected both DSP and CPLD in a single JTAG chain because I had some compatibility problems). Meanwhile I think I have found the problem: I think that the startup values of internal sequential logic (latches and flip-flops) aren't set properly at power on. So I'm expecting that the outputs connected to a latch would be all "0", while they are't; some of these output are connected to the address lines of a flash in which resides the system boot code, hence the startup failure. I tried to use a register with asyncrounous control instead of data latches, connected the asyncronous control to the system reset line and made the reset pulse longer (1-2 seconds instead of 250 ms). Sometimes it works, some other it doesn't. :( Technical support suggested me to use the INIT constraint in my UCF file; I will test it tomorrow. -- LorenzoArticle: 42426
try using "fake" pull-ups (downs) to put the inputs in a known state, hope this helps ! "Theron Hicks" <hicksthe@egr.msu.edu> wrote in message news:3CC58B82.75B7A03C@egr.msu.edu... > Hi, > I am trying to simulate a system with a bidirectional bus. Half of > the system resides in an FPGA and half resides elsewhere (actually a > second FPGA on a different board). > the data in the testbench is correct but when the output of the UUT is > tristated, the data being generated in the test bench does not show up > in the FPGA. Thus the FPGA thinks its input is unknown (really > tri-stated), even though the actual value is being determined by the > testbench. > > The data is declared as inout std_logic_vector and the tri-state control > line is being generated in the testbench and is declaed as input > std_logic in the UUT. > > basicly my logic is as follows > > in the testbench > > if tristate='1' then > data<= test_bench_data > else > data<="ZZZZZZZZZZZZZZZZ" > end if; > > in the UUT > > if tristate='0' then > data<= UUT_data > else > data<="ZZZZZZZZZZZZZZZZ" > end if; > > Of course these snippets are greatly simplified and don't include the > process lines, etc. > > I hope this makes sense, as the actual code is far to complex to try to > attach to this post. Can anyone help me? > > I am using ise 4.1 and have simulated at every level but "Post Place and > Route". > > Thanks, > Theron Hicks >Article: 42427
Hi, I am looking into the idea of code reuse with Xilinx Foundation software (version 4.1i/service pack 3, most recent IP updates: 4x_ip_update1.zip, eip1_tp1.zip) and I'm having difficulties. I figured it would be a good idea to start off with creating a simple core, such as a multiplexer. So I create an HDL-flow project, type in my multiplexer code, and implement the project. Next step is to create the core. From within CoreGenerator, IP Capture is launched. Various files are required, the most important being the .edn edif netlist. In my multiplexer project directory, I have a .edn netlist file named time_sim.edn: it must be renamed to <name of multiplexer module>.edn. So I supply the .edn netlist file, the .vhd source file, the port mapping is entered, etc etc... IP Capture creates a zip file for the core, which is to be extracted to the Xilinx directory. Please note that I have inspected the contents of this .edn file and it seems appropriate - I'm specifying this because the file's original name, time_sim, seems totally inappropriate. So far so good. I create a new project, in which I launch CoreGenerator: my newly created core is exactly where it should be. I can successfully generate it. In my project, I open a new schematic page, and in the parts list my generated multiplexer is there. I instantiate it, add hierarchy connectors, add the sheet to the project, make it the top-level file, and click the 'implement' button. This is where things get ugly: ---------- Annotating constraints to design from file "lasttry.ucf" ... Checking timing specifications ... Checking expanded design ... ERROR:NgdBuild:455 - logical net 'DA<0>' has multiple drivers WARNING:NgdBuild:463 - input pad net 'DA<0>' has an illegal input buffer ERROR:NgdBuild:466 - input pad net 'DA<0>' has illegal connection ERROR:NgdBuild:455 - logical net 'DA<1>' has multiple drivers WARNING:NgdBuild:463 - input pad net 'DA<1>' has an illegal input buffer ERROR:NgdBuild:466 - input pad net 'DA<1>' has illegal connection ERROR:NgdBuild:455 - logical net 'DB<0>' has multiple drivers WARNING:NgdBuild:463 - input pad net 'DB<0>' has an illegal input buffer ERROR:NgdBuild:466 - input pad net 'DB<0>' has illegal connection ERROR:NgdBuild:455 - logical net 'DB<1>' has multiple drivers WARNING:NgdBuild:463 - input pad net 'DB<1>' has an illegal input buffer ERROR:NgdBuild:466 - input pad net 'DB<1>' has illegal connection ERROR:NgdBuild:455 - logical net 'N_SEL' has multiple drivers WARNING:NgdBuild:463 - input pad net 'N_SEL' has an illegal input buffer ERROR:NgdBuild:466 - input pad net 'N_SEL' has illegal connection ERROR:NgdBuild:467 - output pad net 'O<0>' has an illegal buffer ERROR:NgdBuild:467 - output pad net 'O<1>' has an illegal buffer WARNING:NgdBuild:483 - Attribute "INIT" on "U1/GTS" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute. WARNING:NgdBuild:452 - logical net 'U1/GTS' has no driver NGDBUILD Design Results Summary: Number of errors: 12 Number of warnings: 7 --------- The 'implement' step always produces these errors. I am however able to simulate the core. I seem to have narrowed the problem down to the .edn netlist file I supply when creating the core. I got to this conclusion as follows. Within CoreGenerator, there is a multiplexer exactly similar to mine (same # of ports of same bit-width) which ships with CoreGenerator. I take the .edn netlist file supplied with this core, edit it by renaming the ports to match *my* multiplexer and use this modified .edn file to create my multiplexer core. Then I have no problems! I've spent a large amount of time trying different things but to no avail... By poking around I was able to create some slightly different .edn files, but none of them work either. How do you generate an edif netlist file appropriate for use with IP Capture??? Any help would be greatly appreciated, Mike Hubert xiphos.caArticle: 42428
Mike Hubert wrote: > and implement the project. The following pertains to the synthesis step of implementation. This could be where you went wrong. When you implement the project, did you disable I/O buffer insertion? If you did not do this, your "core" has I/O buffers on all the pins. You don't want that if the "core" is going to be reused as a subcircuit in a larger design. Another thing to consider for cores that have sequential logic, do you want the synthesis tool to infer and insert a global clock buffer on the "clock" nets? Probably not. Most synthesis tools have a way to disable these things... It varies from tool to tool. Consult the documentation for your particular implementation tool. If you are entering from schematic, it is a bit easier because you have direct control over what is in the EDIF netlist; you just don't put I/O buffers or clock buffers in the schematic. If you have I/O buffers on the pins, inside the EDIF netlist of your core, you will run into implementation problems with illegal connections, etc... > Checking expanded design ... > ERROR:NgdBuild:455 - logical net 'DA<0>' has multiple drivers > WARNING:NgdBuild:463 - input pad net 'DA<0>' has an illegal input buffer > ERROR:NgdBuild:466 - input pad net 'DA<0>' has illegal connection Hope that helps, EricArticle: 42429
hello, i am a newbie. our company wants to put a gps signal processor on a fpga. i took a 3-day intensive VHDL programming course and now i need to get a software suite to compile the code, simulate the design, and then do the synthesis. the course i took used synplicity. its a nice package, but i was told that it was close to $30,000 for the compiler and simulator. but i see Xilinx ISE with about 4 flavors, ranging upwards to $2500 for a one-year license. right now i don't really mind if the software is tied to one vendor's parts. i only need one part to do this project. but i am finding it impossible to look at the different versions of ISE and tell the difference, or even what their capabilities are. they use the word "support" often, such as when they are talking about a simulator, but i don't know if they mean it con- tains the feature or merely has linking capabilities to a separ- ately priced simulator package. can someone recommend a modestly priced ($2500 for a year's license is ok with me.) software package for either a Xilinx or Altera entry-level FPGA? thank you, mikerArticle: 42430
Have you tried the -timing switch on map. In our benchmarking it improves results when there is a lot of unrelated logic packing. There isn't any recommended percentage utilization for a device. A good rule of thumb is that for larger devices lower utilization (about 70-80%) is a good place to start. However, depending on your design you could run all the way to 95+% utilizations on 2v6000 as we have seen in house. For the smaller devices like the xcv50 you can go substantially higher on the utilization - there is an awful lot of routing for these smaller devices. Regards, Rajeev Jock wrote: > What is the recommended maximum usage in a Virtex FPGA. I've heard on the > grapevine that more than 80% full will give sub-optimal timing in a typical > design. > > I'm using an XCV50 which various between being 99% and 103% of slices being > used (about 20% of these having unrelated logic), depending on how I set > options such as resource sharing, etc. > > When I change one function, I find a completely unrelated function will stop > working. -- Rajeev Jayaraman, Ph.D Director, Physical Implementation Tools, Xilinx Inc.Article: 42431
Tim, Aw, come on. Be serious for a moment. Is 2 Mbytes enough for video, or is that just not even close for something like a high performance MPEG4 coder? Is 1 Mbyte enough for a packet processor? What if you are using a 405PPC? How much code space do you need for a control program? For a DSP support program (with all of the hard stuff in the FPGA like the FFT cores, etc.)? If you look at SDRAM prices, are you willing to pay twice the commodity price in an FPGA? Three times? How much is it worth to you? I already know that programs grow to fit the available memory space, and that data grows to fill the disk..... Austin Tim wrote: > Austin Lesea wrote > > > How much RAM is enough? > > Dorothy Parker isn't always quoted in full, but as the lady said: > "you cannot be too thin or too rich, or have too much RAM" > > Maybe 640K would be enough :-) > > Of course, almost any on-chip RAM hugely increases the bandwidth > compared with off-chip memory, so we immesurably better off than > we were five years ago.Article: 42432
Kevin Brace wrote: > "Theron Hicks (Terry)" wrote: > > > > > > I agree whole heartedly. I would never count on a design until I had done a Post > > P&R simulation. On the otherhand, I would never waste time with a post P&R > > simulation until I had the other levels of simulation working correctly. > > I am glad I am not the only one who advocates doing a Post P&R > simulation to make sure the synthesis tool synthesized the design > correctly. Not just that reason alone. Post P&R ( post-NGDBUILD or post-MAP) is the best way to (a) track down tool bugs, (b) generate a test case that shows it *is* a bug. Most recent example, for me anyway, is last November tracking down a MAP bug in the 2.1i tools I was still using for one design. Best example is the Virtex ``disappearing inverter'' problem for M1.5.Article: 42433
Ray Andraka wrote: > You mention all timing constraints were met. What about constraint coverage? > It is entierly possible to have all constraints met with only a small portion > of the design actually constrained. If your design is passing a functional > simulation and timing, but does not work, the next step is to carefully examine > your timing constraints to make sure you haven't got something important > unconstrained, followed by doing a post-route simulation to verify that the > routed design does indeed match the input design. There have been a few cases > where the xilinx tool is the culprit, but much more often it is the result of a > change in the synthesizer. > The other thing that can bite are multi-cycle relaxation contraints that some small logic change has invalidated. I will go to some lengths to avoid having to use multicycle but under pressure and in desperation ... managed to let myself get bitten by this one last week.Article: 42434
ZSpider <zspider@gte.net> wrote in message news:uMkx8.19685$t65.16692@nwrddc02.gnilink.net... > the course i took used synplicity. its a nice package, but i was > told that it was close to $30,000 for the compiler and simulator. > but i see Xilinx ISE with about 4 flavors, ranging upwards to > $2500 for a one-year license. right now i don't really mind if > the software is tied to one vendor's parts. i only need one part > to do this project. Last I checked, Synplify for Xilinx-only is about $6K, with another $6K for HDL Analyst (schematic viewer). I think Exemplar Leonardo is comparably priced. Synplify-Pro has some additional bells and whistles and maybe that's what is $30K. Also bear in mind the Synplicity products cut their price 50% if you limit to a single vendor. > but i am finding it impossible to look at the different versions > of ISE and tell the difference, or even what their capabilities > are. they use the word "support" often, such as when they are > talking about a simulator, but i don't know if they mean it con- > tains the feature or merely has linking capabilities to a separ- > ately priced simulator package. I believe the free Xilinx tools are basically the same as the $2500 tools. The difference is that the free tools are limited to the smaller and medium size parts, relatively speaking. The more expensive tools get you quicker hotline support also, I think. The Xilinx bundled synthesizer XST is actually pretty acceptable in my experience, although it doesn't have a schematic viewer. I used Synplify for several years and was worried when I had to switch over to XST, but it has been smooth sailing so far on a XC2S100 design. If you are really aggressively pushing the limits of a design Synplify or Leonardo would be your best bet. Also the schematic viewer might be especially good for a newbie. For simulation, Xilinx does not provide a simulator, though they do resell a version of the ModelSim simulator called XE for $1K. The xilinx libraries are already bundled in and compiled which can save a day or two of floundering. They also have a free version of the MT simulator that is identical except that it drags to a crawl when you go over 500 statements (including testbench!). MT sells their PE version for about $6K that is just like the $1K version except it is about 5 times faster. MT also has their EE version for something like $18K that is like 3 times faster than PE, plus it has fancy bells and whistles like code coverage tools that aren't on the cheaper versions. I have heard good things about the $3K Aldec simulator also, but haven't tried it. > can someone recommend a modestly priced ($2500 for a year's > license is ok with me.) software package for either a Xilinx or > Altera entry-level FPGA? Probably your minimum priced solution is the free-$2500 Xilinx tools plus the $1K ModelSim XE. If the Xilinx XST synthesizer doesn't cut it you could try the Synplicity or Exemplar tools for 30 day eval. I would stay away from Synopsis if you are only targeting FPGAs. If you need faster simulation, maybe try Aldec. Disclaimer: I don't know much about Altera's offerings. Prices are what I remember from about a year ago. -JeffArticle: 42435
hi, I need to connect an SDRAM to a processor and a VirtexII so that both can access it with VirtexII having the priority. The processor has an SDRAM controller on it. I am thinking about daisy chaining all the signals (everything going from CPU through VirtexII to SDRAM) and implementing an SDRAM controller in VirtexII too. This doesn't have to be very fast. 60 MB/s throughput would be enough. Does this make sense? Any other simpler/easier solutions ? Anyone has done anything similar ? thanks, Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 42436
In article <a9q3it$5enur$1@ID-115042.news.dfncis.de>, Johann Glaser <Johann.Glaser@gmx.at> wrote: >Would it be possible to offer medium size and large size parts (like >XC2S200, ...) for hobbyists, prototyping (or even production) at a really >low price, but with some small errors. E.g. that one or several (of the >many available) CLBs are defect. Anything with a Spartan in the name is SMALL by xilinx and silicon standards, probably 30-60mm^2 of silicon: So much that packaging can cost as much as the die, and the defect rate is so close to 0 that defective parts are best used as keychains. Now, a Virtex2Pro, largest part, THAT would be useful with a defect map. :) -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 42437
ZSpider wrote: (snip) > > but i am finding it impossible to look at the different versions > of ISE and tell the difference, or even what their capabilities > are. I'm maybe a little bit farther along than you are. So I can help you in some of these things. Xilinx, whether by omission or design, does not tell newbies what languages their development tools support. If you look at one of their feature charts, such as the following one for their Webpack, http://www.xilinx.com/ise/products/webpack_config.htm you will note that nowhere do they say if they support Verilog or VHDL, or anything. In fact, Webpack supports both ! If you download Webpack and start a new project, you will see a New Project dialog box that has three properties, one of which is Design Flow. Now, the Design Flow box says "EDIF". As a newbie you wonder, what is that ? You've heard of Verilog and VHDL, but they're not mentioned. So you could shut down Webpack and dismiss it, and go spend $500 on ISE BaseX. That's exactly what Xilinx wants you to do. Here's the critical thing: If you CLICK ON THE DESIGN FLOW box, a down arrow magically appears, and all of a sudden, you see options for Verilog and VHDL ! Nowhere in the Windows User Interface have I ever seen hidden combo boxes like this. The whole essence of Windows is to show you your options. Xilinx hides them. Why ? So you don't have to spend $500 on BaseX. Just get the free Webpack. It does it all. I wish I could tell this to every newbie. If someone from Xilinx reads this, please modify your feature matrix boxes for your development tools to say that they support Verilog and VHDL. Especially do this for the Webpack feature box ! One more thing -- Xilinx sells incredibly expensive, but poorly equiped demo boards. Their Spartan II board goes for $450, and has NO voltage regulators on it. You have to buy, or build your own 2.5v power supply. It doesn't even come with a Xilinx chip. You gotta buy that too. Save your $450, and go to Insight, and buy one of their cheap demo boards. I did have a problem with my Insight board, in which the chips seemed to have an infant mortality problem. Replacing them solved the problem. So if it doesn't work correctly right out of the box, I suggest you return it immediately. But their Spartan II board is $125 and comes with voltage regs, a Xilinx chip, an LCD, etc. It's a much better value. -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 42438
Muzaffer Kal <kal@dspia.com> writes: > I need to connect an SDRAM to a processor and a VirtexII so that both > can access it with VirtexII having the priority. The processor has an > SDRAM controller on it. I am thinking about daisy chaining all the > signals (everything going from CPU through VirtexII to SDRAM) and > implementing an SDRAM controller in VirtexII too. This doesn't have to > be very fast. 60 MB/s throughput would be enough. Does this make > sense? Any other simpler/easier solutions ? Anyone has done anything > similar ? The Intel StrongARM SA1110 processor's on-board SDRAM controller actually provides a request/grant mechanism for arbitrating the SDRAM bus away from the processor. This feature is used by their companion chip, but since the companion chip doesn't do what I want (and does a lot of things I don't need), I've considered using a Spartan II with it. But I suppose most other SDRAM controllers don't have that feature. And I've switched to using an Alchemy (AMD) Au1500 instead of the StrongARM.Article: 42439
One possibility may be to put location constraints into the ucf file by hand. You can use your VHDL net names. For example: INST "/module/myff*" LOC=CLB_R11C5; Please look up the syntax of the location because it changes with the FPGA families. It is also possible to use RLOCs and other location constraints. And the use of wildcards is a nice option, which makes you more indepandant of the tools. FPGA Express renames all registers with "_reg". I don't know what XST does. This strategy does not work for combinatorical logic, though. Because you have to name the instance, and it's the task of the synthesizer to optimize the logic, so don't know the name. You can come around this problem when you instantiate LUT directly in you VHDL source code. The "assumed way" is to do the synthesis and then do iterations with the floorplanner, I think. But if you resynthesize you you have to redo your work. An application engineer will know this better than I do. Chris In <c3771dbf.0204230731.1fb51677@posting.google.com> rjshaw@iprimus.com.au (russell) wrote: >Hi, > >Trying to floorplan a hierarchial design done in XST VHDL, >i couldn't really get the hang of, because of the tedious >net names. Previous messages have mentioned that the net >names can change from just a slight modification in the >source code. > >There must have been an assumed way the tools were to be >used when the floor planner was being done. I'd guess one >assumption was that schematics were used atleast for the >top level of a hierarchial design. > >I was wondering, if i did all the various parts of the >hierarchy as schematic blocks, and just filled in the >simple blocks with vhdl such as state machines, counters, >filters etc, would the end result give an easy to interpret >netlist amenable to sane routing in the floor planner? > >After reading lots of C.A.F. messages, it seems the xilinx >floor-planning tools are a bit dated/broken/etc.Article: 42440
Like what several other people have said, I will also recommend Xilinx's ISE WebPACK. I have synthesized a design with both XST and LeonardoSpectrum, and I felt like XST did a better job synthesizing a circuit that runs faster than LeonardoSpectrum, although the LeonardoSpectrum I used here was an Altera OEM version (LeonardoSpectrum-Altera). The devices used here for comparison were Xilinx Spartan-II-5 (XST) and Altera FLEX10KE (LeonardoSpectrum-Altera). The free ModelSim XE-Starter that comes with ISE WebPACK is supposedly much slower compared to the paid version, but I find the simulation speed acceptable for my project. I have also used Altera's LeonardoSpectrum-Altera and Quartus II 2.0 Web Edition which are both free, but tools tend to be much buggier (LS-Altera's GUI sometimes crashes, and I have seen QII's fitter crash several times.) than ISE WebPACK, and Altera doesn't let you use a free 'crippled' version of ModelSim, so I don't recommend using Altera's free tools. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.)Article: 42441
Hello Newsgroup, I have a problem with Chip Viewer as a part of of Xilinx ISE 4.2. Program is coming up, but if I want to load a design the programs hangs up. The 'Reading Data' keeps forever up, I have to kill the task. Due to the fact this is a Java based program, the system environment (java-plugins) haven't been set the right way?! I have installed Java 1.4 from Sun. Thank you, and regards SteffenArticle: 42442
> can someone recommend a modestly priced ($2500 for a year's > license is ok with me.) software package for either a Xilinx or > Altera entry-level FPGA? >From the Altera point of view, $2000 per year gets you: Quartus II Max+Plus II Leonardo Spectrum OEM Level 1 ModelTech ModelSim-Altera Excalibur Tools for the ARM Embedded Processor All Software Updates (taken from https://buy.altera.com/ecommerce/software.asp) These tools support the whole range of Altera devices. Things to note: LeoSpec doesn't support mixed-Verilog/VHDL synthesis I've heard that ModelSim is somewhat crippled (at least in terms of speed) Hope this helps, JamesArticle: 42443
James Srinivasan wrote: > > > can someone recommend a modestly priced ($2500 for a year's > > license is ok with me.) software package for either a Xilinx or > > Altera entry-level FPGA? > > From the Altera point of view, $2000 per year gets you: > > Quartus II > Max+Plus II > Leonardo Spectrum OEM Level 1 > ModelTech ModelSim-Altera > Excalibur Tools for the ARM Embedded Processor > All Software Updates > > (taken from https://buy.altera.com/ecommerce/software.asp) > > These tools support the whole range of Altera devices. Things to note: > > LeoSpec doesn't support mixed-Verilog/VHDL synthesis > I've heard that ModelSim is somewhat crippled (at least in terms of speed) From memory it runs at 1/2 the speed of the 'full' verson of modelsim, but there is no limit on design size. Also note that at the end of your subscription year all the Altera tools still work although if you want more upgrades/service packs you need a new subscription. The Xilinx tools don't work at the end of the year. When I took out an Altera subscription the Altera rep told me that the 3rd party tools should work indefinitely too, although looking at the license file there's a data against Modelsim so I'll have to wait to see what happens (the date's ~1 year after the subscription runs out). Nial.Article: 42444
> When I took out an Altera subscription the Altera rep told me that > the 3rd party tools should work indefinitely too, although looking > at the license file there's a data against Modelsim so I'll have > to wait to see what happens (the date's ~1 year after the subscription > runs out). I've encountered both ModelSim and LeoSpec licenses expiring and refusing to work. However, we're licensed through the University Partnership Programme so things might be different. JamesArticle: 42445
I am making a small (XC2S30) project and have a few questions: 1. DLL's Is the usage of DLLs obligatory or not? I am shifting data to the Spartan synchronously with external 4,096MHz clock. Another clock in my project is about 11MHz. Do such clocks need DLLs? 2. I/Os I have to interface to 5V devices. Which I/O standard should I use: LVTTL or PCI_33_5? In what they differs (both are 5V tolerant)? Only in current sink/source capabilities? 3. Configuration I will use Master Serial mode. What is the Preconfiguration Pull-ups option? Should I turn it on or off? -- Regards, Pawel J. RajdaArticle: 42446
Hy, I am using a ROM in my design on a VirtexE-1000. This ROM is made as a RAM block where the WE signal is always inactive. To write the initial value to the ROM I regenerate the core (core generator) assigning a new init file to the memory. The problem is that doing it I have to re-synthetize and P&R the whole design everytime I want to change some value in the ROM. Is there any way to change the ROM content without synthesis and P&R?? (I am using Xilinx ISE 4.2 tools and the XST synthetizer) Thaks in advance!! Paul.Article: 42447
hello, i want to give a BIG thanks to everybody who responded. i checked the news server as soon as i got in to work today (well, i did get a cup of coffee first). i was thrilled with all the responses. i immediately printed them out so i can go thru them all carefully. i have a feeling that decisions made up front concerning a software platform and the hardware FPGA will either cause or eliminate a lot of grief. thanks again, mikerArticle: 42448
Hi, I made a JTAG programmer to connect a spartan2 to a pc. Do the pins nPROGRAM, DONE, or nINIT need pullups when configuring a single device?Article: 42449
Dear All Dir Xilinx XC2S150 PQ208 slave parallel mode for flash download program error !!! CCLK = 1.832MHZ Flash AT29C040-12, PROG. INIT push high 10k (PROG link at push putton). M0=0,M1=1,M2=1 1. push putton 2. wr.cs go lo, busy = lo 3. init goto lo 1uS go hi 4. flash addr counting and data output to XC2S150 5. about 40uS init go hi , why? 6. stop all Help Me please!
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