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You're initializing the RAM with strings instead of hex values. Each character in a string represents an 8-bit ASCII value, so a "0" is 8'h30, "1" is 8'h31, and so on... Try changing the intialization to something like the following : (note the 256'h and no double quotes) defparam ram.INIT_00 = 256'h81f124203440241473f572fc71f6000a0908070600050403020100f210015000; HTH, Jim jimwu88NOOOSPAM@yahoo.com (remove capital letters) http://www.geocities.com/jimwu88/chips "Kelvin" <kelvin8157@hotmail.com> wrote in message news:c3l5r0$g4v$1@reader01.singnet.com.sg... > Thanks for your reply...I did put the defparam...but the problem is i can't > correlate the numbers > on simulator with the RAM contents... > > Kelvin > > // synthesis translate_off > defparam ram.INIT_00 = > "81f124203440241473f572fc71f6000a0908070600050403020100f210015000"; > defparam ram.INIT_01 = > "a2f183f10cf810042401243472f573fc70f01e007efe101f06f81001a3f182f1"; > defparam ram.INIT_02 = > "00000000000000000000080006fc1004b7f0a8f177f4100100f0100306f41003"; > defparam ram.INIT_03 = > "0000000000000000000000000000000000000000000000000000000000000000"; > defparam ram.INIT_04 = > "0000000000000000000000000000000000000000000000000000000000000000"; > defparam ram.INIT_05 = > "0000000000000000000000000000000000000000000000000000000000000000"; > defparam ram.INIT_06 = > "0000000000000000000000000000000000000000000000000000000000000000"; > defparam ram.INIT_07 = > "0000000000000000000000000000000000000000000000000000000000000000"; > defparam ram.INIT_08 = > "0000000000000000000000000000000000000000000000000000000000000000"; > defparam ram.INIT_09 = > "0000000000000000000000000000000000000000000000000000000000000000"; > defparam ram.INIT_0A = > "0000000000000000000000000000000000000000000000000000000000000000"; > defparam ram.INIT_0B = > "0000000000000000000000000000000000000000000000000000000000000000"; > defparam ram.INIT_0C = > "0000000000000000000000000000000000000000000000000000000000000000"; > defparam ram.INIT_0D = > "0000000000000000000000000000000000000000000000000000000000000000"; > defparam ram.INIT_0E = > "0000000000000000000000000000000000000000000000000000000000000000"; > defparam ram.INIT_0F = > "0000000000000000000000000000000000000000000000000000000000000000"; > // synthesis translate_on > > > > > "Jim Wu" <jimwu88NOOOSPAM@yahoo.com> wrote in message > news:Buh7c.3517$vC.63@nwrdny03.gnilink.net... > > For simulation, you need to use "defparam" to intialize the ram. e.g > > > > defparam ram.INIT_00 = > > 256'h81f124203440241473f572fc71f6000a0908070600050403020100f210015000; > > > > HTH, > > Jim > > jimwu88NOOOSPAM@yahoo.com (remove capital letters) > > http://www.geocities.com/jimwu88/chips > > > > > > "Kelvin" <kelvin8157@hotmail.com> wrote in message > > news:c3k67m$aft$1@mawar.singnet.com.sg... > > > Hi, there: > > > > > > These are the contents of my block RAM, in simulator I inject 00~FF into > > > i_addr on ever negative edge of clock... > > > How come I got 0000/3530/3031/3130/6632/3030...instead of the numbers I > > put > > > in INIT? What is the document > > > to look for INIT values? > > > > > > Best Regards, > > > Kelvin > > > > > > > > > > > > RAMB4_S16_S16 ram( .DOA(do_a), .DOB(do_b), .ADDRA(i_addr[7:0]), > > .CLKA(clk), > > > .DIA(16'b0), > > > .ENA(1'b1), .RSTA(1'b0), .WEA(1'b0), .ADDRB(d_addr[7:0]), > > .CLKB(~clk), > > > .DIB(d_in), .ENB(1'b1), .RSTB(1'b0), .WEB(we_b)); > > > // synthesis attribute INIT_00 of ram is > > > "81f124203440241473f572fc71f6000a0908070600050403020100f210015000" > > > // synthesis attribute INIT_01 of ram is > > > "a2f183f10cf810042401243472f573fc70f01e007efe101f06f81001a3f182f1" > > > // synthesis attribute INIT_02 of ram is > > > "00000000000000000000080006fc1004b7f0a8f177f4100100f0100306f41003" > > > // synthesis attribute INIT_03 of ram is > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > // synthesis attribute INIT_04 of ram is > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > // synthesis attribute INIT_05 of ram is > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > // synthesis attribute INIT_06 of ram is > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > // synthesis attribute INIT_07 of ram is > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > // synthesis attribute INIT_08 of ram is > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > // synthesis attribute INIT_09 of ram is > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > // synthesis attribute INIT_0A of ram is > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > // synthesis attribute INIT_0B of ram is > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > // synthesis attribute INIT_0C of ram is > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > // synthesis attribute INIT_0D of ram is > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > // synthesis attribute INIT_0E of ram is > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > // synthesis attribute INIT_0F of ram is > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > > > > > > > > > >Article: 67876
Hi, I am new to FPGA's. I am trying to implement a RISC processor with some instruction set(arithmetic,logical) on VIRTEX-II FPGA,then I want to program it using the serial port,for this i want to use c++.is there any resources or any way i can change GCC compiler to work for my processor.I also want to try to port linux on this to work as RTOS,but i believe for this i first need the compiler for my CPU.so, i need help in finding the resources,tutorials.If there is something you know please let me know.I thank you in advance. sreeram koneru koneru.2@wright.eduArticle: 67877
"Hal Murray" <hmurray@suespammers.org> wrote in message news:105sh7fd8glmue6@corp.supernews.com... > >All clock inputs have to be synchronous. So, all your clock inputs have to > >be driven directly by an oscillator or by dedicated clock > >multiplier/divider/shifter such as Xilinx Digital Clock Manager (DCM). > > Nonsense, on two levels. > > First, not all clock inputs have to be synchronous. If that was true > we would only have one clock in the world. You do have to pay > attention when crossing clock domains. > > Even if all your clocks are synchronous, it's possible (but generally > unwise) to have several copies that are skewed from eachother. The > simple example is clocking on the other edge. Some software can > handle that case. You can also shift the clock a tiny bit in order > to trade off setup time for hold time. (Of course, that skews the > output too so analyzing timings gets more complicated.) You are suggesting from your previous thread that you can use the output of a combinational logic to drive the clock of a flip flop or enable of a latch. That's the one that I want to point out. If you have two system, such as a PC and an outside peripheral, such as a printer, of course you must have at least two clocks with a clock synchronizer in between. What I tried to point out is if you have two flip flops within the same system, you must have only one clock or you can have two clocks with the second one driven by a dedicated clock divider/multiplier/shifter, such as Xilinx Digital Clock Manager (DCM). > Second, you don't need a direct or dedicated connection to the > clock source. In many systems, it's common to gate the clock with > an AND/NAND gate fairly high up the clock tree. The idea is to save > power, both in the logic and in the clock tree, when that chunk of > logic isn't needed. That's probably a (very) bad idea on today's > FPGAs. You right. It is a bad idea to use GATED CLOCK. At least for FPGAs. What's going to happen if you disable the clock just slightly after the rising edge of the clock? You could have a clock with very narrow duty cycle. If you have an abnormally narrow clock pulse, with say 1 % duty cycle, and at the same time your flip flop want to sample the input, the output of that flip flop will be unpredictable. > They tend to have a clock-enable input at each local FF > rather than anything higher up the clock tree. (I think that's > generally a mux rather than a true clock enable.) But there is > no fundamental requirement for a direct or dedicated connection. > The general rule is that you have to meet setup/hold times, even > when you consider clock skew.Article: 67878
Try http://www.fpgacpu.org/ for some general info, or try having a look at Microblaze from Xilinx, Nios from Altera etc. If you want Linux running on it, have a look at http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/ Peter > I am new to FPGA's. I am trying to implement a RISC processor with > some instruction set(arithmetic,logical) on VIRTEX-II FPGA,then I want > to program it using the serial port,for this i want to use c++.is > there any resources or any way i can change GCC compiler to work for > my processor.I also want to try to port linux on this to work as > RTOS,but i believe for this i first need the compiler for my CPU.so, i > need help in finding the resources,tutorials.If there is something you > know please let me know.I thank you in advance. > sreeram koneru > koneru.2@wright.eduArticle: 67879
Have you tried the -timing option in map? Simply add the -timing option to map and then follow up with PAR with the same options that you used before. This will help in cases where the utilization is very high and we have had good success with it internally and with several customers. Regards, Rajeev Rajeev Jayaraman, Ph.D., Sr. Director, Implementation Tools, Xilinx Inc. "Sandi Posl" <tome@myhost.not> wrote in message news:WtD5c.6427$%x4.844057@news.siol.net... > Hello, > > I don't have much experience with RTL and implementing designs, but I > have encountered a strange problem. > > The design I am working on is rather large and I have been forced to > remove some RTL modules from the design to get the total LUT's used down > to 85% (during the synthesis phase, I'm using Synplify PRO) for the > XC2V6000-5FF1152 FPGA. I would prefer to have the complete design > implemented on the FPGA. > > As an experiment, I decided to synthesize my design by defining the > Xilinx Virtex-E XCV3200E-8FF1156 FPGA in Synplify Pro, and the total > LUT's used came to 95% (and the Virtex-II is almost twice the size!). > > Why is this happening, I thought that the Virtex-II is proportionally > 'larger' that the Virtex-E? > Am I not configuring options in Synplify correctly for the XC2V6000 FPGA > (Virtex-II)? > Could this be because the two FPGA's I have mentioned are so different, > that the design 'fits easier' into the Virtex-E? > > > The hardware platform I already have has the Virtex-II FPGA on it, so I > have to implement my design on this FPGA. > > Thank you in advance for any help. > > Regards > > Sandi > > P.S. I have not used my actual email address so that I don't get spam > sent to my email address. :-) If you would prefer to contact me > directly, my email address is sandip<at>flextronics<dot>si >Article: 67880
buchty@atbode100.informatik.tu-muenchen.de (Rainer Buchty) wrote in message news:<c3h8er$3aqqo$1@sunsystem5.informatik.tu-muenchen.de>...
> In article <slrnc5mm2o.7e0.ldoolitt@recycle.lbl.gov>,
> Larry Doolittle <ldoolitt@recycle.lbl.gov> writes:
> |> Infer flip-flops instead. In Verilog:
> |>
> |> reg foo;
> |> always @(posedge clk) foo <= some_expression;
> |>
> |> or the more verbose and not necessarily more useful:
> |>
> |> reg foo;
> |> always @(posedge clk or posedge rst) if (rst) begin
> |> foo <= 0;
> |> end else begin
> |> foo <= some_expression;
> |> end
> |>
> |> I'll leave the VHDL versions to someone else.
> |> My fingers get tired too quickly. ;-)
>
> As if
>
> if rst='0' then
> foo<='0';
> elsif clk'event and clk='1' then
> foo<=some_expression;
> end if;
>
> would be any more typing than your Verilog example...
... and the following is slightly simpler:
if rst = '0' then
foo <= '0';
elsif rising_edge(clk)
foo <= some_expression;
end if;
--a
Article: 67881hmurray@suespammers.org (Hal Murray) wrote in message news:<105qhjp3rdt8g71@corp.supernews.com>... > > And combinational logic is subject to > >glitches. So, if you are going to use a latch, you have to make sure that > >during the entire time when the enable of your latch is asserted, the output > >from your combinational logic will never have any glitches. > > That's not obvious to me. Am I missing something? When the latch enable is in the not-latching state (and I can never remember whether "latch enable" means "hold data" or "let data flow through"), the latch adds some extra delay to the data path. If what's feeding the latch comes from combinatorial logic, then of course the latch output (again when in the flow-through mode) will glitch if the input glitches. An example is the 8051's ALE signal; the micro drives the address on port 0 during ALE and latches it when ALE goes away. If you decode that address and use it to drive, say, an async FIFO's write enable, and if the address glitches, well, you're hosed. (Yes, this is one of the things you learn not to do when you're a junior engineer. If I could re-design that mess, I would!) I think the only reason one would need a transparent latch these days is to get that head-start on address decoding in a system with async buses. Instead of using a latch, one could simply use a flip-flop clocked by the latch enable on the appropriate edge, if that "head start" isn't necessary. --aArticle: 67882
"Spike" <me.hates:spam@me.net> wrote in message news:<Cny6c.52754$mU6.219585@newsb.telia.net>... > ok, I would like to make my own PCI board (a stand-alone PCI card which I > can insert in an computer with a free PCI slot). Nothing fancy just a board > that could send out I/O data or what ever. > > For this task I've heard that FPGA would be a good choice. > > I don't know how to explain it better but if I've missed something, let me > know. On one hand, if the point is to learn all about PCI and how to implement a PCI target (or even master) in an FPGA, then an FPGA is a good choice. On the other hand, if the point is to actually get a product out the door, you will be better off using one of PLX' (http://www.plxtech.com/) PCI chips. The PLX part handles all of the PCI stuff that may very well drive you mad, and gives you a pretty simple local bus that is pretty easy to connect to your interesting custom hardware that may reside in a CPLD or small FPGA. I'm pretty sure that this route (PLX + CPLD/small FPGA) is cheaper than the big FPGA needed to do the PCI core + your custom logic. On the gripping hand, if the point is to use a single FPGA for the whole design, you might want to consider either the soft cores from Altera, Xilinx and Lattice, or you may use one of the QuickLogic devices that have a hard PCI core that talks to a bunch of FPGA gates. In these cases, someone's done the hard work of designing the PCI stuff; you get a local bus that you interface to your custom logic. It's worth noting that none of the soft cores are inexpensive. In all cases, you will find that a PCI bus analyzer (a non-trivial expense indeed) will be necessary when you're trying to figure out just what the hell is going on when your design fails for bizarre reasons. --aArticle: 67883
Hello, I dont have much experience on JAM files. I'm working with svf files. Xilinx and altera are providing this type of file. With it it's very simple to progam proms fpga cpld with a simple parallèle cable. (no proprietary cable). Xilinx is providing the sources for a svf player. So you can compile it under linux if you want. There is one problem (otherwise will be too simple). You must convert svf file to xsvf file (xilinx format). This parser is also providing by xilinx. I don't know if it's still available cause now the webpack 6.2 is including this parser. Good luckArticle: 67884
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:4058D4FE.3F94CC19@yahoo.com... > I don't know that you need a CPU to "direct" arithmetic operations. Don't read too much into my choice of words. I meant that I want special-purpose arithmetic hardware under program control. > It can be fun to use Forth or other interesting ideas in chips, but I > don't know of an application where this is a better way to go than an > off the shelf DSP or CPU. I'm not sure you're right. I've heard this argument a number of times, and I know of enough counter-examples to throw it very much into doubt. I wrote a networked multi-user virtual reality system in the early- and mid-nineties. It used Forth as the programming language for the object behavior. It ran usably over a 28.8 modem, on a Pentium 90, with software-only 3D rendering. The other VR efforts of the day couldn't match the performance of my system because they chose programming languages with high overhead. After all, they argued, cpu cycles and memory are cheap and getting cheaper -- another false argument I hear again and again. Would you, with your current experience, have recommended Forth for VR as a better way to go than an off-the-shelf solution? I know of another counter-example involving military reconnaissance, an expert system, and the first Forth processor, the Novix NC4000. I imagine that very few people would have predicted that Forth would prove superior for expert systems, but one member of the team claimed they couldn't have done it without Forth. Mind you, this was a team working for the military, not the stereotypical undisciplined garage coder writing inscrutable Forth code. One thing I can tell you from my days doing VR is that it's a lot less tedious in Forth than it is in C to write code that does multiplies by sines and cosines. That already is a win. Another win is that it is much easier to debug custom hardware from a Forth command prompt. Another is that Forth is great for experimental software development, and that is one of the things I will be doing as I work with audio processing and synthesis. While Forth is relatively unknown in the mainstream, it has small yet very devoted followings in various nooks and crannies of the industry, such as aerospace. I suspect that somewhere, someone is using Forth for signal processing with great success. I was hoping, when I asked my original question, to turn up information about such people. -DavkaArticle: 67885
In article <F9x7c.103$Dr5.124194@news.uswest.net>, "Davka" <mygarbagepail@hotmail.com> writes: |> ... After all, they argued, cpu cycles and memory are cheap |> and getting cheaper -- another false argument I hear again and |> again. No, it's not a false argument - but, like most such arguments, it becomes false if used in an inappropriate context or if taken to the limit. Regards, Nick Maclaren.Article: 67886
Wolfgang <wp@it-effektiv.de> wrote in message news:<c3kmro$uq2$00$1@news.t-online.com>... > Ulrich programmed a cpu on a Xilinx and you can download the VHDL code. > http://www.it-effektiv.de/Download2/downloads2.php > > GNU License! Hi, Interresting, but is any one know another 64-bits CPU core in GNULicense to be able to compare it ??? ThanksArticle: 67887
Oh, yeah...Thank you jim... Kelvin Jim Wu <jimwu88NOOOSPAM@yahoo.com> wrote in message news:Nes7c.16545$GT2.8482@nwrdny01.gnilink.net... > You're initializing the RAM with strings instead of hex values. Each > character in a string represents an 8-bit ASCII value, so a "0" is 8'h30, > "1" is 8'h31, and so on... Try changing the intialization to something like > the following : (note the 256'h and no double quotes) > > defparam ram.INIT_00 = > 256'h81f124203440241473f572fc71f6000a0908070600050403020100f210015000; > > HTH, > Jim > jimwu88NOOOSPAM@yahoo.com (remove capital letters) > http://www.geocities.com/jimwu88/chips > > > > > "Kelvin" <kelvin8157@hotmail.com> wrote in message > news:c3l5r0$g4v$1@reader01.singnet.com.sg... > > Thanks for your reply...I did put the defparam...but the problem is i > can't > > correlate the numbers > > on simulator with the RAM contents... > > > > Kelvin > > > > // synthesis translate_off > > defparam ram.INIT_00 = > > "81f124203440241473f572fc71f6000a0908070600050403020100f210015000"; > > defparam ram.INIT_01 = > > "a2f183f10cf810042401243472f573fc70f01e007efe101f06f81001a3f182f1"; > > defparam ram.INIT_02 = > > "00000000000000000000080006fc1004b7f0a8f177f4100100f0100306f41003"; > > defparam ram.INIT_03 = > > "0000000000000000000000000000000000000000000000000000000000000000"; > > defparam ram.INIT_04 = > > "0000000000000000000000000000000000000000000000000000000000000000"; > > defparam ram.INIT_05 = > > "0000000000000000000000000000000000000000000000000000000000000000"; > > defparam ram.INIT_06 = > > "0000000000000000000000000000000000000000000000000000000000000000"; > > defparam ram.INIT_07 = > > "0000000000000000000000000000000000000000000000000000000000000000"; > > defparam ram.INIT_08 = > > "0000000000000000000000000000000000000000000000000000000000000000"; > > defparam ram.INIT_09 = > > "0000000000000000000000000000000000000000000000000000000000000000"; > > defparam ram.INIT_0A = > > "0000000000000000000000000000000000000000000000000000000000000000"; > > defparam ram.INIT_0B = > > "0000000000000000000000000000000000000000000000000000000000000000"; > > defparam ram.INIT_0C = > > "0000000000000000000000000000000000000000000000000000000000000000"; > > defparam ram.INIT_0D = > > "0000000000000000000000000000000000000000000000000000000000000000"; > > defparam ram.INIT_0E = > > "0000000000000000000000000000000000000000000000000000000000000000"; > > defparam ram.INIT_0F = > > "0000000000000000000000000000000000000000000000000000000000000000"; > > // synthesis translate_on > > > > > > > > > > "Jim Wu" <jimwu88NOOOSPAM@yahoo.com> wrote in message > > news:Buh7c.3517$vC.63@nwrdny03.gnilink.net... > > > For simulation, you need to use "defparam" to intialize the ram. e.g > > > > > > defparam ram.INIT_00 = > > > 256'h81f124203440241473f572fc71f6000a0908070600050403020100f210015000; > > > > > > HTH, > > > Jim > > > jimwu88NOOOSPAM@yahoo.com (remove capital letters) > > > http://www.geocities.com/jimwu88/chips > > > > > > > > > "Kelvin" <kelvin8157@hotmail.com> wrote in message > > > news:c3k67m$aft$1@mawar.singnet.com.sg... > > > > Hi, there: > > > > > > > > These are the contents of my block RAM, in simulator I inject 00~FF > into > > > > i_addr on ever negative edge of clock... > > > > How come I got 0000/3530/3031/3130/6632/3030...instead of the numbers > I > > > put > > > > in INIT? What is the document > > > > to look for INIT values? > > > > > > > > Best Regards, > > > > Kelvin > > > > > > > > > > > > > > > > RAMB4_S16_S16 ram( .DOA(do_a), .DOB(do_b), .ADDRA(i_addr[7:0]), > > > .CLKA(clk), > > > > .DIA(16'b0), > > > > .ENA(1'b1), .RSTA(1'b0), .WEA(1'b0), .ADDRB(d_addr[7:0]), > > > .CLKB(~clk), > > > > .DIB(d_in), .ENB(1'b1), .RSTB(1'b0), .WEB(we_b)); > > > > // synthesis attribute INIT_00 of ram is > > > > "81f124203440241473f572fc71f6000a0908070600050403020100f210015000" > > > > // synthesis attribute INIT_01 of ram is > > > > "a2f183f10cf810042401243472f573fc70f01e007efe101f06f81001a3f182f1" > > > > // synthesis attribute INIT_02 of ram is > > > > "00000000000000000000080006fc1004b7f0a8f177f4100100f0100306f41003" > > > > // synthesis attribute INIT_03 of ram is > > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > > // synthesis attribute INIT_04 of ram is > > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > > // synthesis attribute INIT_05 of ram is > > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > > // synthesis attribute INIT_06 of ram is > > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > > // synthesis attribute INIT_07 of ram is > > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > > // synthesis attribute INIT_08 of ram is > > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > > // synthesis attribute INIT_09 of ram is > > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > > // synthesis attribute INIT_0A of ram is > > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > > // synthesis attribute INIT_0B of ram is > > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > > // synthesis attribute INIT_0C of ram is > > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > > // synthesis attribute INIT_0D of ram is > > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > > // synthesis attribute INIT_0E of ram is > > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > > // synthesis attribute INIT_0F of ram is > > > > "0000000000000000000000000000000000000000000000000000000000000000" > > > > > > > > > > > > > > > > > > > >Article: 67888
Now I have read two CPU/Assembler designs...They look simple enough, but who can write a working C compiler for these custom instruction sets? It must be extremely difficult... Kelvin john <cdufourfour@yahoo.ca> wrote in message news:79cc958c.0403220115.79f493c7@posting.google.com... > Wolfgang <wp@it-effektiv.de> wrote in message news:<c3kmro$uq2$00$1@news.t-online.com>... > > Ulrich programmed a cpu on a Xilinx and you can download the VHDL code. > > http://www.it-effektiv.de/Download2/downloads2.php > > > > GNU License! > > Hi, > > Interresting, but is any one know another 64-bits CPU core in > GNULicense to be able to compare it ??? > > ThanksArticle: 67889
On Wed, 10 Mar 2004 22:41:25 -0500, rickman <spamgoeshere4@yahoo.com> wrote: >I'm curious, which CPUs did you feel were not worth the port? We spent a lot of time on MIPS R3xxx and R4xxx for very little return, and in retrospect the TMS320C3x/4x DSPs were probably not a good investment. Stephen -- Stephen Pelc, stephenXXX@INVALID.mpeltd.demon.co.uk MicroProcessor Engineering Ltd - More Real, Less Time 133 Hill Lane, Southampton SO15 5AF, England tel: +44 (0)23 8063 1441, fax: +44 (0)23 8033 9691 web: http://www.mpeltd.demon.co.uk - free VFX Forth downloadsArticle: 67890
interesting - while doing wire wrapping to create a development board with XCV2000E (BGA FG860) I accidently connected VCCINT to 3.3V supply - I would guessed to see smoke or at least dead FPGA (the power supply did deliver full 3.3V to VCCINT), but no! The FPGA was a little warm, but not hot. After fixing the VCCINT back to 1.8V I did get long time the famous error "DONE DID NOT GO HIGH" but after reading the datasheet and pulling PROGRAM to high the XCV2000E did come fully alive, i.e. it really survived several minutes of 3.3V on VCCINT. Antti Lukats PS if i get some time to breathe I will upload the picture of this 2M Gate development board (my self-costs $49!! ) just clarification: I am using a FPGA in BGA package that is removed from equipment and I am soldering wires directly to BGA pads. The FG860 is actually really easy to handle, and if I dont need many IO pins such a wire wrap development board can be made in 3 hours max.Article: 67891
Dear Sir or Madam, I want to synchronize 90MHz data which come from an external 90MHz clock domain (GMII transceiver device) to my internal FPGA 90MHz clock. So I have two clocks with the same frequency but they are asynchronous to each other. What possibilities can be used for synchronization? Is the following method possible and useful ? : http://mitglied.lycos.de/vazquez78/ Thank you for your time and help. Best regards Andrés Vázquez Guntermann & Drunck System DevelopmentArticle: 67892
This is probably the largest Confluence release to date. The major features include an open source license, executable simulation models, automatic HTML documentation, and a new standard library. ** Open Source License Starting with Confluence 0.9, the compiler is now released under the GNU General Public License and the standard libraries are covered with the GNU Lesser General Public License. ** Executable Simulation Models The Confluence compiler now returns executable models providing bit and cycle accuracy with high simulation performance. The executable simulation models are controlled by a simple command and query language, making it easy to connect Confluence to any verification environment or programming language (SystemC, Java, Python, OCaml, etc.). Because the simulation kernels run optimized native code, even a Perl test-bench will yield performance on par with compiled HDL simulation. Another added benefit of executable simulation models is IP design firms can deliver precise evaluation models that are ready to run and nearly impossible to reverse engineer. ** Automatic HTML Documentation Confluence 0.9 also introduces cfdoc: a tool for generating HTML documentation from Confluence source code comments. Similar to javadoc, cfdoc scans a source directory tree extracting comments from *.cf files. Currently the HTML is not the most attractive, but the formatting and capabilities of cfdoc will continue to improve. Here's a shot of the standard library: http://www.launchbird.com/lib/ ** New Standard Library (base.cf) The new standard library has been built from the ground up with more organization and clearer naming conventions to provide a robust foundation for Confluence designers. Aside from base.cf, the libraries have reserved space for higher-level components for DSP, communication, on-chip busing, processors, cryptography, and other categories. Hopefully the open source community will start elaborating on these areas. ** Download Confluence 0.9 source code and binary distributions are available at: http://www.launchbird.com/download.html ** Background Confluence is a declarative functional programming language for the design and verification of synchronous reactive systems including digital logic, hard-real-time software, and hardware-software co-design. >From one source, Confluence generates: - Verilog and VHDL netlists (synthesis, simulation) - Cycle accurate C models (software, simulation) - NuSMV models (formal verification) - XML netlists (custom back-end tooling) - Executable Models (open verification) Regards, Tom -- Tom Hawkins Launchbird Design Systems, Inc. http://www.launchbird.com/Article: 67893
"Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:<405ec63e$1@news.starhub.net.sg>... > Now I have read two CPU/Assembler designs...They look simple enough, > but who can write a working C compiler for these custom instruction sets? > It must be extremely difficult... > > Kelvin > > > > john <cdufourfour@yahoo.ca> wrote in message > news:79cc958c.0403220115.79f493c7@posting.google.com... > > Wolfgang <wp@it-effektiv.de> wrote in message > news:<c3kmro$uq2$00$1@news.t-online.com>... > > > Ulrich programmed a cpu on a Xilinx and you can download the VHDL code. > > > http://www.it-effektiv.de/Download2/downloads2.php > > > > > > GNU License! > > > > Hi, > > > > Interresting, but is any one know another 64-bits CPU core in > > GNULicense to be able to compare it ??? > > > > Thanks See fpgacpu.org for notes on how to port lcc to other 32b risc like cpus that are similar to those already there. Also the lcc book by Hanson & Fraser is a superb book for those jumping into C compiler deep end 1st. The 64b issue though sounds like the lxer, parser, semantic type checking would all have to be touched as well to get int64 in. regards johnjakson_usa_comArticle: 67894
Thanks for you tip, I'll take it under consideration. Has anyone tried this one: http://www.plxtech.com/tools/rdk/9030rdk-lite.htm Does PLX PCI chips require some sort of EEPROM to store PCI configuration space or any other information, if so what kind of ROM is needed? //SPike "Andy Peters" <Bassman59a@yahoo.com> skrev i meddelandet news:9a2c3a75.0403212304.715f920f@posting.google.com... > "Spike" <me.hates:spam@me.net> wrote in message news:<Cny6c.52754$mU6.219585@newsb.telia.net>... > > ok, I would like to make my own PCI board (a stand-alone PCI card which I > > can insert in an computer with a free PCI slot). Nothing fancy just a board > > that could send out I/O data or what ever. > > > > For this task I've heard that FPGA would be a good choice. > > > > I don't know how to explain it better but if I've missed something, let me > > know. > > On one hand, if the point is to learn all about PCI and how to > implement a PCI target (or even master) in an FPGA, then an FPGA is a > good choice. > > On the other hand, if the point is to actually get a product out the > door, you will be better off using one of PLX' > (http://www.plxtech.com/) PCI chips. The PLX part handles all of the > PCI stuff that may very well drive you mad, and gives you a pretty > simple local bus that is pretty easy to connect to your interesting > custom hardware that may reside in a CPLD or small FPGA. I'm pretty > sure that this route (PLX + CPLD/small FPGA) is cheaper than the big > FPGA needed to do the PCI core + your custom logic. > > On the gripping hand, if the point is to use a single FPGA for the > whole design, you might want to consider either the soft cores from > Altera, Xilinx and Lattice, or you may use one of the QuickLogic > devices that have a hard PCI core that talks to a bunch of FPGA gates. > In these cases, someone's done the hard work of designing the PCI > stuff; you get a local bus that you interface to your custom logic. > It's worth noting that none of the soft cores are inexpensive. > > In all cases, you will find that a PCI bus analyzer (a non-trivial > expense indeed) will be necessary when you're trying to figure out > just what the hell is going on when your design fails for bizarre > reasons. > > --aArticle: 67895
Hello, I am using a XC95144XL on a 5V board. I need to supply 3.3V to the XC95144XL. Do I need a 5V/3.3V DC-DC converter, or a zener with some resistors and capacitors? I heard that XC consumes wide range of current so I guess the zener might not do the job. Is there any reference about this issue? Thank you. vax, 3900Article: 67896
A contractor to a company where I used to work designed a board for us with an XCV50 on it. Eventually we dropped him because it became obvious he didn't know what he was doing. I took over the project and found that he had 3.3V hooked up directly to VCCINT and designed the board with no 2.5V regulator on it. The FPGA had some problems booting up occasionally but otherwise it had been working fine for months. $60k down the drain because some shmuck at NASA insisted we use his friend as a contractor.Article: 67897
Kevin, That only applies to Virtex and Virtex E. Delay is not necessary for the V2 and V2P. Austin Kevin Neilson wrote: > Nivek, > you should actually delay the lock to use as the reset for the second; see > Fig. 13 in XAPP132. > -Kevin > > "Niv" <niv.nospam.goaway@ntlworld.com> wrote in message > news:5po7c.47$Kn2.16@newsfe1-win... > >>I do have a reset delay circuit, but it does the same for both DCMs. >> >>I'll try & use DCM 1 lock as the reset for the 2nd, is that the sort of >>thing? >> >>Niv, (Also a Kevin really, backwards & truncated, in fact). >> >>"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message >>news:Kio7c.54744$1p.903420@attbi_s54... >> >>>Do you have a delayed reset on the second DCM? You can't let the second >> >>DCM >> >>>come out of reset until the first is locked. There is some appnote that >>>explains this. >>>-Kevin >> >> > >Article: 67898
All, Although gate oxides and junctions seem to occasionally take really painful punishment, and survive, we are not hearing fom all of those who are too embarrassed to admit they blew it. Please observe the abs max ratings: they are there for a reason. Read the qual reports that are posted online if you want to see what punishment we subject our devices to, and expect them to live. http://www.xilinx.com/bvdocs/userguides/ug116_reliability_report.pdf Austin Xilinx, APD, ICDES chris wrote: > A contractor to a company where I used to work designed a board for us > with an XCV50 on it. Eventually we dropped him because it became obvious > he didn't know what he was doing. I took over the project and found that > he had 3.3V hooked up directly to VCCINT and designed the board with no > 2.5V regulator on it. The FPGA had some problems booting up occasionally > but otherwise it had been working fine for months. > > $60k down the drain because some shmuck at NASA insisted we use his > friend as a contractor. >Article: 67899
cdufourfour@yahoo.ca (john) wrote in message news:<79cc958c.0403220115.79f493c7@posting.google.com>... > Wolfgang <wp@it-effektiv.de> wrote in message news:<c3kmro$uq2$00$1@news.t-online.com>... > > Ulrich programmed a cpu on a Xilinx and you can download the VHDL code. > > http://www.it-effektiv.de/Download2/downloads2.php > > > > GNU License! > > Hi, > > Interresting, but is any one know another 64-bits CPU core in > GNULicense to be able to compare it ??? This is more comparible to an 8-bit CPU in terms of functionality than a real 64-bit processor. I don't know of many 64-bit processors that can only access 16k-words of RAM. Cheers, JonB
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