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Hi, NG: Senario 1: I have a 40MHz primary clock, through a clock buffer. I now have two DCMs to convert the 40MHz into 36MHz & 12MHz. Both using CLKFX...Each DCM has its own feedback clock buffer. Assume I floorplan the DCMs and clock buffers symmetrically (almost), how much confidence can I rely on the synchronization of my 36MHz & 12MHz? Will ISE6 automatically fix the timing related issues if only set the constraints on the DCM with following? NET "clk_40m_w" TNM_NET = "clk_40m_w"; TIMESPEC "TS_clk_40m_w" = PERIOD "clk_40m_w" 25 ns HIGH 50 %; INST "DCM0" CLKIN_PERIOD = 25 ; INST "DCM1" CLKIN_PERIOD = 25 ; Senario 2: I have a 40MHz primary clock, through a clock buffer. I use one DCM to convert them into, say 12MHz(CLKFX) & 4MHz(CLKDV). How much confidence can I rely on the synchronization of my 4MHz & 12MHz? Best Regards, KelvinArticle: 67301
Hi, I am wondering if anyone out there has experienced random spurious reconfiguration issues with Cyclone devices? We have an issue where the FPGA in our design configures correctly but then a short time later for apparently no reason goes int a reconfig cycle and stays there (as its not loaded). I suspect that there might be an issue with our power supply design but still have not isolated the problem ... and on the off-chance this is a larger issue, it seems like a good idea to see whether other people have experienced similar problems. Thanks, ChrisArticle: 67302
You can do that by having the terminal state assert a synchronous reset to the entire
state machine with considerably less logic.
Jim Granville wrote:
> Ray Andraka wrote:
>
> > Peter,
> >
> > Consider the case where you have 1 input high to one of your luts, and 2 inputs
> > high to another lut. It is clearly an illegal state, as it has two extra '1' bits,
> > but it will be detected as OK by your circuit because exactly one LUT is indicating
> > one input on. Each group of four requires two outputs to distinguish 0,1 or more
> > than 1 input on.
>
> I think Peter was partly correct. You can protect/correct a 16 stage
> One-Hot engine against illegal states with 5 LUTs, but it will not
> recover in a single clock cycle.
> Simplest topology is to have 15 shifters, and #16 loads a HI ONLY if
> all Prev15 are 000000000000000, if not, it simply waits until
> the bogus ones ripple out.
>
> -jg
>
> >
> > Peter Alfke wrote:
> >
> >
> >>Eh, what? Unfortunately anonymos...
> >>
> >>Each first level LUTs detects (output High) that exactly one of its inputs
> >>is High.
> >>The second tier LUT detects that exactly one of the first-tier LUT outputs
> >>is high, which mans that there is exactly one High input.
> >>Agreed ?
> >>Peter Alfke
> >>
> >>
> >>>From: user@domain.invalid
> >>>Newsgroups: comp.arch.fpga
> >>>Date: Tue, 09 Mar 2004 05:24:26 GMT
> >>>Subject: Re: Release asynchrounous resets synchronously
> >>>
> >>>Peter Alfke wrote:
> >>>
> >>>>LUTs are very efficient "illegal state" detectors.
> >>>>Let's say you have a 16-state one-hot machine. Four LUTs can each detect
> >>>>"exactly one of my inputs is High", and a fifth LUT does the same with the
> >>>>four LUT outputs. So 5 LUTs can detect any illegitimate 16-bit code. Take it
> >>>>from there...
> >>>
> >>>Eh, what? So the first tier LUT compute f, where
> >>>f(a,b,c,d) = 1 iff a+b+c+d = 1, else 0.
> >>>For the 5th LUT we have the same property that a legal 16-state would
> >>>map exactly one of the four first tier LUTs to 1, thus it sounds like
> >>>what you have in mind is something like this:
> >>>
> >>>f({f(s[3:0]), f(s[7:4]), f(s[11:8]), f(s[15:12])})
> >>>
> >>>but this could accept states like 16'b1111_1110_1100_0001.
> >>>
> >>>I don't see how you can detect legal states with only five four-input LUTs.
> >>>
> >>>
> >>>Peter, the FPGA reset question has come many times. What does Xilinx
> >>>recommend in general? Async-reset+Sync-release, all-sync, or all-async?
> >>>Which uses fewest resources?
> >>>
> >>>Thanks,
> >>>
> >>>Tommy
> >>>
> >
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 67303I have been going nuts with a Spartan 2 and 18v04 during configuration with a JTAG cable (III) and impact 6.1. 1. The mode pins are set for boundary scan. 2. If I run the cable with a 5v reference: a. Chain initialization will succeed 99% of the time. b. EPROM programming/verify will succeed 95% of the time. c. FPGA programming/verify will fail verify 100% of the time and the FPGA is left with what appears to be wrong IOB configuration; starts drawing a great deal of power. d. If I run IDCODE looping, it will fail before my defined 1000 loops are completed. 3. If I run the cable with 3.3v reference (which it should be anyway), I cannot get through the Chain initialization ever. I get up to 10 unknown devices reported. I have pulled out a previously designed board and reprogrammed it without any problems, to verify the software/drivers/cables. I have checked for noise on the power and JTAG lines, didn't find anything alarming. If anyone has any suggestions, your input would be GREATLY appreciated. Thanks!Article: 67304
Do spartan-2 and JTAG support readback and verify? Kelvin warren <topfuel1015@comcast.net> wrote in message news:86732d3d.0403092000.656c2ac3@posting.google.com... > I have been going nuts with a Spartan 2 and 18v04 during configuration > with a JTAG cable (III) and impact 6.1. > > 1. The mode pins are set for boundary scan. > 2. If I run the cable with a 5v reference: > a. Chain initialization will succeed 99% of the time. > b. EPROM programming/verify will succeed 95% of the time. > c. FPGA programming/verify will fail verify 100% of the time and > the FPGA is left with what appears to be wrong IOB configuration; > starts drawing a great deal of power. > d. If I run IDCODE looping, it will fail before my defined 1000 > loops are completed. > 3. If I run the cable with 3.3v reference (which it should be anyway), > I cannot get through the Chain initialization ever. I get > up to 10 unknown devices reported. > > I have pulled out a previously designed board and reprogrammed it > without any problems, to verify the software/drivers/cables. > > I have checked for noise on the power and JTAG lines, didn't find > anything alarming. > > If anyone has any suggestions, your input would be GREATLY > appreciated. > > > Thanks!Article: 67305
hi,
tried so many ways. I am getting same error. individual
blocks are getting synthesized. Please if anybody have the idea help
me.
thanking you all.
Article: 67306Dear Sir, As suggested by you I have downloaded the webpack from the Xilinx website but how to set the options for the device XC4010E and FPGA3142. Forgive me for my ignorance. kindly help me. regards and thanks "B. Joshua Rosen" <bjrosen@polybus.com> wrote in message news:<pan.2004.03.07.15.46.31.684698@polybus.com>... > On Sun, 07 Mar 2004 06:38:15 -0800, manmohan singh wrote: > > > Hi All, > > Greetings, > > > > I am a student. I found Xilinx 2.1i version software but I think > > Licence is expired. Can anybody give me the information from where I > > can get the licence (preferably free because as student I don't have > > much funds) > > > > regards and thnaks > > You don't want to use 2.1 for anything it's an antique. Xilinx offers > webpack which is a free version of their tools. Webpack is a subset but > it's probably sufficient for your needs. If you want to use the full set > of tools you should have your EE department contact the local Xilinx sales > office, I suspect that they would be happy to provide a free or > discounted version of their tools to you University.Article: 67307
Hi, I have written a very small design to control some LEDs in order to check out the XC2V6000-4ff1517 FPGA on a board that I am bringing up. The code has only 92 signals that are to be routed. The Synthesis, Translation and mapping steps take just 25 seconds. However, the PAR takes about 20 minutes. I would like to know what the ISE6.1 (SP3) is doing in all that time? Any suggestion to improve this will be very welcome. Thanks, HunterArticle: 67308
"Subroto Datta" <sdatta@altera.com> wrote in message news:<41a3c.22164$cY5.21375@newssvr31.news.prodigy.com>... > Hi Sneakernet, > > You cannot implement their desired output frequency of 12.5 Mhz using the > Cyclone PLL without going out of spec. > > The Cyclone PLL does have a minimum output frequency limit, which is a > function of the PLL's minimum VCO frequency. The minimum VCO frequency is > 491Mhz, and the maximum output divider counter size is 32, which results in > a minimum output frequency of approximately 15.3 Mhz (i.e.491/32). > > Page 4-31 of the device handbook gives the PLL frequency specs. The input > frequency has to be between 15.625 MHz and 464 MHz for the > fastest (-6) speed grade, and between 15.625 MHz and 387 MHz for the slowest > (-8) speed grade. See > http://www.altera.com/literature/hb/cyc/cyc_c51004.pdf for details. > > - Subroto Datta > Altera Corp. > Dear Mr Datta, is that right? In the spec. it is said that the minimum VCO frequency is 300 and not 491MHz. Could you please clarify? I also want to create an internal 12MHz-clock (PLL input 30MHz) Rgds Andrés VázquezArticle: 67309
Hi Allan, In comp.arch.fpga, Allan Herriman said... > I suggest you look at Ethernet PHYs. They are cheap, readily > available, simple to interface to your FPGA, and will work reliably at > 100Mb/s over 100m of cat5. They also take care of scrambling and > coding such that you effectively have a 100Mb/s clear channel > end-to-end. > > E.g. LXT972A > http://www.intel.com/design/network/products/ethernet/linecard_ept.htm Thanks for the hint. We have to transmit very low amounts of data (17 Bit adress, 16 Bit Data). Our idea was to create our own protocol, which has just a little overhead to secure the data. I have not yet understood what the scrambler/descrambler does. It does not produce the whole ethernet protocol, does it? Isn't it possible to use just the cat5 cable and the Ethernet coils? Can I connect the coil directly to the FPGA? How much is the PHY you proposed? What else do I need to have it working? Sorry for these maybe silly questions, but I never designed an Ethernet connection before. Thanks for your help. Greetz, Thomas -- No matter if you are going on-piste or off-piste, just hit the slope and stay healthy! For mail reply replace "nospam" with "kurth" and "net" with "de". The above mentioned adress is valid, but ignored.Article: 67310
Hi has anyone have had any luck with Quartus II ver 4? Internal Error: Sub-system: FYGR, File: fygr_global_utility.cpp, Line: 5797 number_of_res == 0 || number_of_res == 1 (Fitter pre-processing) Quartus II Version 4.0 Build 190 1/28/2004 SJ Web Edition the desing is one input routed to one output. all other projects fail as well including the tutorials from QII V4 Altera: what is that? Measuring customers? How much bullshit can they take? If you cant make a software to work, DO NOT RELEASE IT! Hire people that can make it work, and TEST IT! v3 is now uninstalled and v4 completly fails!!! and I am really really really tired to submit service requests! Antti Lukats P.S. For Altera: for a short period of time I might be available for hiring, as my current contract ends 31.03.2004, I will be still busy in April preparing a OTG core ASIC tapeout, but after that I would be available. However the situation may change any day. P.P.S. the OTG core is AHB bus connected but instead of using Altera and NIOS (and NIOS avalon 2 AHB wrapper) we are using Microblaze with OPB to AHB wrappers. Those neverending problems with Altera tools have been one reason why we did not make the FPGA verification on NIOS board what also was available. I could change that (people abonding use of Altera products), if I get the chance!Article: 67311
hi Kelvin, Yup, I come from The Chinese University of Hong Kong. I don't think my professor is fooling me. May be I should state clearly what I have to do. The poject do not require us to make a real chip. We just use magic to draw the layout and use irsim to simulate. And, it is a group poject. Could you shed a light on my project? Regards, Tong "Kelvin @ SG" <kelvin8157@hotmail.com> ¼¶¼g©ó¶l¥ó·s»D :404e7739@news.starhub.net.sg... > it seems your professor is fooling you...i guess designing a decent FPGA > chip will require a big team of > engineers and top of the line Cadence & Mentor softwares...be prepared to > pay hundreds of thousands US$ > for the licenses alone...besides, it seems u r from a Chinese university... > > > > Tong <nospam@cuhk.edu.hk> wrote in message > news:c2km7a$ko9$1@justice.itsc.cuhk.edu.hk... > > hi all, > > > > I am a undergraduate studying VLSI and Magic manul layout. My professor > have > > asked us to design an FPGA chip using Magic. > > I am confused in how to build the switch box and look up table. Could > anyone > > kindly recommend some website or books that gives detail explanation on > > these stuff. > > > > Thanks a lot. > > > > Regards, > > Tong > > > > > >Article: 67312
>You can take the 50 mhz clock into a 2 bit counter and take the output >of the MSB for 12.5 MHz. This can drive a global clock tree within the >device to minimize skew between all registers driven by the 12.5 MHz. >The only drawback is that you will have some skew between the 50 mhz >and 12.5 mhz domains, so you need to be careful with data transfers >across the domains. Suppose I make a 100 MHz clock, feed it to a 3 bit counter, and use the bottom and top bits as 50 and 12.5 MHz clocks. If I'm careful, what sort of skew can I get between those two clocks? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 67313
Hi Klaus, In comp.arch.fpga, Klaus Falser said... > We are using LVDS together with a low capacitance cable of 10 m > at 50 MHz clock, and my impression is that it is on it's limit. It is sensitive > to disturbances and signal quality depends strongly on quality of the cable. > > If you really want to do it, do not forget to feed the GND signal too through > the cable, since the common mode range of the differential receivers is not > large enough for dealing with differences between the ground levels of > transmitter and receiver. > > I seem to remember that somewhere on the National Semiconductor web pages there is > a graph about data rates and covered distances. > > Convince your boss to use an optical link, you will have only advantages! They are not > so complicated as it seems. Thanks for your help. I have already found the graph before and so I am a little confused about your experience. On http://www.maxim-ic.com/appnotes.cfm/appnote_number/1856/ln/en there is table3 and figure7 which show the relation between cable lengths and transmission rates. I found a reliable transmission over 60 ft (20 m) at data rates of about 528 MBit. So your 10 m @ 50 MBit seem to be very low... Factor 10 should be possible? Concerning the optical solution. What do we need for such a thing and what will it cost? Do you have any experience on this topic? Thanks for your help, Thomas -- No matter if you are going on-piste or off-piste, just hit the slope and stay healthy! For mail reply replace "nospam" with "kurth" and "net" with "de". The above mentioned adress is valid, but ignored.Article: 67314
We have had lots of success so far ... been using it for a while. Got any optimisation flags ticked? We do a lot of minimise area with chains stuff and logic locking (which is tonnes better than 3) but there used to be issues with some flags in 3. Are you using an AMD based platform - had some issues running version 4 on AMD we think. "Antti Lukats" <antti@case2000.com> wrote in message news:80a3aea5.0403100111.5b08404c@posting.google.com... > Hi > > has anyone have had any luck with Quartus II ver 4? > > Internal Error: Sub-system: FYGR, File: fygr_global_utility.cpp, Line: 5797 > number_of_res == 0 || number_of_res == 1 > (Fitter pre-processing) > Quartus II Version 4.0 Build 190 1/28/2004 SJ Web Edition > > the desing is one input routed to one output. > all other projects fail as well including the > tutorials from QII V4 > > Altera: what is that? Measuring customers? > How much bullshit can they take? > If you cant make a software to work, DO NOT RELEASE IT! > Hire people that can make it work, and TEST IT! > > v3 is now uninstalled and v4 completly fails!!! > and I am really really really tired to submit service requests! > > Antti Lukats > > P.S. > For Altera: for a short period of time I might be available > for hiring, as my current contract ends 31.03.2004, I will > be still busy in April preparing a OTG core ASIC tapeout, > but after that I would be available. However the situation > may change any day. > > P.P.S. the OTG core is AHB bus connected but instead of using > Altera and NIOS (and NIOS avalon 2 AHB wrapper) we are > using Microblaze with OPB to AHB wrappers. Those neverending > problems with Altera tools have been one reason why we did > not make the FPGA verification on NIOS board what also was > available. > I could change that (people abonding use of Altera products), > if I get the chance!Article: 67315
Hi everybody, I'm rather new to the whole VHDL business but I'm surrounded by good helpfull people. Yesterday I wrote a short block which has caused us al headaches. The error I get after "Syntax check" is: Started process "Check Syntax". ========================================================================= HDL Compilation * ========================================================================= Compiling vhdl file c:/bruno/tb/test.vhd in Library work. ERROR:HDLParsers:3214 - HdpStrSafeCatPX: Str2 is NULL ERROR: XST failed Process "Check Syntax" did not complete. anybody who can help us out? thx in advance BrunoArticle: 67316
Dear all I am looking for FPGA benchmark circuits. Could someone inform me of - where can I obtain the benchmark (HDL or schematic or any format), if available. Are there any working group such as MCNC, in fpga? - second thing is about Virtex . Are the configuration memory and block select RAM different or same term? If different, where is configuration memory located (outside of FPGA chip or inside)? There are registers in FPGA (for example, frame data input register). Question is how it look like (flip flop chain?) and where is it located (outside of FPGA or inside) Thankyou alwaysArticle: 67317
Thomas Kurth <thomas.nospam@gmx.net> writes: > we are planning a high speed data transmission between several devices. > We now found the LVDS standard. I found some pages in the WWW which told We (Dolphin) transmit 18-bits in parallel (including clock), source syncronous, LVDS, over 5-meter (longer if the cable has low skew) copper cables running at 166 MHz sampling at both edges resulting in 333 Mbit/pin or 667 MByte/second. See: http://www.dolphinics.no/products/ Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 67318
greg, Thanks for theses notes about Stratix PLL but I own a Cyclone development board , so I can't use the features of the Stratix PLL ... About the operating limits of the cyclone PLL, the values given in the hand-book don't interrest me : theses ones are fixed by altera in order to achieve the performances written in the handbooks. That's why the VCO frequency range of the VCO is between 500MHz and 1000Mhz (acording to the handboook) but I am able to run the VCO at 200 MHz and even 50 MHz with a 50 MHz clock input. So, that I would like to know is the behaviour of the PLL when I use it out of the frequency range specified in the hand book. In particular: -what is the bandwith of the loop filter of the PLL ? -what is the attenuation in the IOs when I use a clock input of 10MHz or 5Mhz or 100kHz I'm not sure to be very clear, so in other terms : how can I use the PLL out of the specified ranges in order to have a miximum jitter ? Thanks a lot.Article: 67319
>I have been going nuts with a Spartan 2 and 18v04 during configuration >with a JTAG cable (III) and impact 6.1. Have you put a scope on the clocks? Can you shorten the chain by lifting some pins and bypassing a chip or two? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 67320
>Oh, and I alwasy make sure I have at least a million clock cycles, and >take repeated samples of a million cycles to be sure that I have the >peak values captured. How did you decide that a million was enough? How many times do you have to repeat that? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 67321
>The only reason I could see to do a Forth machine in an FPGA is that you >might have valuable Forth code that needs to run 100x faster than the >microprocessor curretly hosting it. So, you do a 6502 (or whatever) on >steroids or a true Forth machine in a fast FPGA and solve your problem. Suppose I had some Forth code that I wanted to run. How would a special system in an FPGA compare to an emulator/inteperator on a normal CPU (take your pick)? I guess I'm curious about $/instruction or $/MIPS as well as absolute speed. I'd expect a resonably vanilla X86 or embedded system would do quite well in the $/instruction department. I'd expect a modern PC to go pretty fast, depends upon the skill of the guys writing the compiler/interpreter/emulator. Can I actually build a system in a FPGA that runs faster? The FPGA system might be a great idea if you already need the FPGA for something else, especially if your program/system is small enough so that you won't have to add a lot of memory chips. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 67322
Hi, I have been using Quartus 11 release 4 build 190 already for about 4 weeks and had only problems in the beginning with a project using signaltap. Al my Q3 project work fine with Q4, i am only using cyclones at the moment. ron proveniers "Antti Lukats" <antti@case2000.com> schreef in bericht news:80a3aea5.0403100111.5b08404c@posting.google.com... > Hi > > has anyone have had any luck with Quartus II ver 4? > > Internal Error: Sub-system: FYGR, File: fygr_global_utility.cpp, Line: 5797 > number_of_res == 0 || number_of_res == 1 > (Fitter pre-processing) > Quartus II Version 4.0 Build 190 1/28/2004 SJ Web Edition > > the desing is one input routed to one output. > all other projects fail as well including the > tutorials from QII V4 > > Altera: what is that? Measuring customers? > How much bullshit can they take? > If you cant make a software to work, DO NOT RELEASE IT! > Hire people that can make it work, and TEST IT! > > v3 is now uninstalled and v4 completly fails!!! > and I am really really really tired to submit service requests! > > Antti Lukats > > P.S. > For Altera: for a short period of time I might be available > for hiring, as my current contract ends 31.03.2004, I will > be still busy in April preparing a OTG core ASIC tapeout, > but after that I would be available. However the situation > may change any day. > > P.P.S. the OTG core is AHB bus connected but instead of using > Altera and NIOS (and NIOS avalon 2 AHB wrapper) we are > using Microblaze with OPB to AHB wrappers. Those neverending > problems with Altera tools have been one reason why we did > not make the FPGA verification on NIOS board what also was > available. > I could change that (people abonding use of Altera products), > if I get the chance!Article: 67323
have you tried expanding the "Generate Programming file" option in the processes for source pane of ISE. The option to generate PROM, ACE or JTAG file is there, try running that? Mike emanuel stiebler wrote: > Hi all, > > Where is the strange checkmark hiding in ISE 6.1 > to create the .mcs files for programming the proms ? > > Thanks >Article: 67324
I just tried this, it should launch the iMPACT program which then gives you the option of selecting your target type device i.e. PROM, ACE, JTAG etc. it's pretty intuitive from then on. Mike Mike Nicklas wrote: > have you tried expanding the "Generate Programming file" option in the > processes for source pane of ISE. > > The option to generate PROM, ACE or JTAG file is there, try running that? > > Mike > > emanuel stiebler wrote: > >> Hi all, >> >> Where is the strange checkmark hiding in ISE 6.1 >> to create the .mcs files for programming the proms ? >> >> Thanks >> >
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