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groups.google.com had a sponsored link from http://www.4starelectronics.com/ for Altera parts. I clicked for a quick check on this "Obsolete Semiconductors" website and found Spartan-3s! Small quantities of ES and non-ES parts. I didn't see any pricing because it seems they hide that info. Request a quote and verify their stock numbers are real! Qty 25 XC3S400-4PQ208CES are showing. "Brad Eckert" <nospaambrad1@tinyboot.com> wrote in message news:7d4cc56.0403170952.6724372d@posting.google.com... > I know this subject has been kicked around a lot here, but here we go > again. > > Where can one get a small quantity of XC3S400s? I already have some on > indefinite back order at Avnet. Maybe there is another source? > > Reminds me of John Cleese in the cheese shop: > "Do you in fact have _any_ Spartan IIIs?" > "Yes." > "Really?" > "No."Article: 67826
>How do you upload the program to the FPGA? As far as I know FPGA's doesn't >haave support for EEPROM so another deivce would have to upload it (I would >be very glad if you could prove me wrong on this one!). The general idea is that it gets loaded automatically at the end of power-on reset (from the PCI connector). I suggest you read the section in the data sheets on configuration. It may take a few readings. It's not a big deal after you see it. You can get special serial ROMs that directly interface to the FPGA. The FPGA wiggles a clock. The ROM gives back bits. It's probably cheaper to add a tiny CPLD or uP to give you more flexibility in your choice of (flash) ROMs. That turns the problem into how do you get your program into the (flash) serial ROM. The simple answer is with a cable going into the back of the card. You can also do it with signals coming out of the back side of the FPGA. That assumes you have a working design, and you probably want another copy for backup so maybe you need a switch. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 67827
If you read the datasheet correctly, you find that this extra delay is between 100 ps and 300 ps. It is longest for large devices and slow speed grades. The purpose of this extra delay is to avoid input pad hold-time issues. The extra delay compensates for potential clock routing delay uncertainties. Peter Alfke >From: thangkho <> >Organization: (none) >Newsgroups: comp.arch.fpga >Date: Fri, 19 Mar 2004 15:03:59 -0800 >Subject: Virtex-E IOB programmable delay > > >Hi guys, > >This is what I get from Xilinx datasheet, please confirm me if I am wrong: >The IOB programmable delay has only two modes delay/nodelay. When delay is >implemented, it add just 100ps to data path.Article: 67828
Hi, For that board, specifically, the smaller chip is a Xilinx ISP PROM that contains the bitstream. There are also some jumpers to which you may attach a download cable, which can send the bitstream to the device directly. That is only useful for prototyping and debug. > Also, What kind of PCI cards have you developed with the > help of this card? I've done a number of designs with it; one was a RAMDisk that used the SDRAM as storage, another was a video peripheral to drive a VGA monitor. I haven't had any problems with this card. All the designs I did used the v3.0 PCI LogiCORE from Xilinx, and I didn't have any problems with that, either. :) EricArticle: 67829
Kurt Müller wrote: > I still can run the synthesis using the UI, so the error is not related to > the hld code. Try running the script one line at a time. > Any sugestion what i have messed up in my setup, and what the cure is to > bring my design back on track. Talk to whoever wrote the script. Or just use the GUI. Or learn the leo commands yourself. -- Mike TreselerArticle: 67830
>Nonsense. I'll grant that it's harder to do a static timing analysis on a >latch based design but it's perfectly doable. In an ASIC a latch design >has a lot of advantages, Thanks for the long explaination. I think I've worked with people who built latched based CPUs back in the TTL/ECL days but I've never worked on that sort of beast. (I know what a 373 is, but my junk box only has 374s.) My half-wiseass response would have been because the hardware prefers FFs and the software (basically) doesn't support latches. Has anybody done a classic latched based two-phase clock design in a FPGA? How do you distribute the clock? What sort of speed did it run at, relative to a similar design using FFs. Can you trick the software into doing a sensible timing report? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 67831
> > I don't really use the GUI for Tcl-ing, but I have never seen a case
> > where you need to close the project and re-open it to avoid an
> > Internal Error.
>
> That's the only solution I found. If I don't close & open the project,
> when the script reaches the "initialize_logiclock" command it crashes
> with:
>
> Internal Error: Sub-system: XRU, File: xru_hdb.cpp, Line: 1560
> m_got_esf_writelock > 0
> Exiting...
>
> The problem has to do with the virtual pin assignments and the logiclock
> initialization, since each of them works fine on its own...
>
Looks like a bug :-(
Your best bet may be to upgrade to V4.0.
>
> > In terms of where to get help, I recommend that you use "quartus_sh
> > --qhelp" from the command-line. --qhelp will execute a Tk based GUI
> > that allows you to browse through the help (both for Tcl commands and
> > for the command-line executables).
> >
> > You can also do:
> >
> > quartus_cdb --tcl_eval help -cmd <command>
> >
> > or using the Tcl shell:
> >
> > quartus_cdb -s
> > tcl> help -cmd <command>
> > tcl> <command> -long_help
> > tcl> <command> -h
>
> Yes, but the problem is that there are no help files for some commands,
> so neither of these options works for them (see the other subthread, in
> answer to Przemek), e.g. the set_logiclock command.
>
I was trying to reproduce it on the PC (and I am sure Przemek too), so
it seems like the Linux installation may be missing some files.
Again, if you can do it, try V4.0
> > >
> > > catch {puts [exec printf ",s/FLOATING/LOCKED/g\nwq\n" | ed top.esf]} dummy
> > >
> >
> > This is clever. You can also use the ::quartus::project package to
> > change the assignments.
>
> This will be interesting. How exactly? Using a set_global_assignment? This
> information is stored hierarchically into the .esf file, so somehow I will
> need to specify the LOGICLOCK_REGION for each assignment...
>
Yes, you can use set_global_assignment. You can use "-entity
<esf_file_name>" and "-section_id <logiclock_region_name>". At least
-section_id may be hidden in V3.0, but it will work fine.
-David Karchmer
Altera Corp.
Article: 67832Yeah, source code is there... It's a good example to study a microprocessor design. However, do you have any simulation files and do you have a behavior model of the cpu instead of the instantiated LUT4s which are hard to read... Lack of a multiplier seems to be a flaw in the instruction set... If it is on FPGA, then a debugger can be easily integrated...can JTAG pins be used for normal IOs after the FPGA programming? How to lower pin count? If want more instructions, then it may need to a wider instruction bus... Can add in some peripherals like UART/I2C/PWM etc... Without PROM/Flash on board also... Willing see your progress... Best Regards, Kelvin "Sumit Gupta" <do_not_reply_to_this_addr@yahoo.com> wrote in message news:ae680d56.0403191133.44cf13f7@posting.google.com... > "Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:<405a9fdf$1@news.starhub.net.sg>... > > Gupta, > > > > Are you willing to release the source code for sasm.exe? > > Its already there. Click on downloads in the sidebar. > > Sumit > > > > > Best Regards, > > Kelvin > > > > > > Sumit Gupta <do_not_reply_to_this_addr@yahoo.com> wrote in message > > news:4ru6c.26051$nH2.4810@newssvr29.news.prodigy.com... > > > I wrote a sample VC++ program to download Xilinx FPGAs via slave serial > > mode > > > using JTAG cable (parallel cable III). I have posted it to my website. Its > > > compiled as a windows console application. I used inpout32.dll library to > > > talk to parallel port of the PC. The program works on my win2K laptop. > > > > > > Sumit > > > ----- > > > http://www.c-nit.net > > > > > >Article: 67833
> For timing simulation with Xilinx FPGAs, a global set/reset (GSR) is
> automatically asserted at the begining of simulation.
> this is to mimic what happens after configuration of the FPGA. One of
> the final stages of conifguration is the assertion of the GSR net (a
> dedicated wire connected to the set or reset of every FF in the FPGA) to
> bring the design into a known state after the completion of
> configuration.
If I understand corretly, FPGAs have about 100ns internal reset. This means
that we do not need for any explicit RESET in test bench at all; we just
need to wait for 100ns for reset to complete. However, my observation shows
that test bech must provide at least 100 ns reset for registers to
initialize.
As you see, one of the outputs depend on state of registers. Both register
and the output are (strong?) low during 100 ns reset; meantime they should
be initially high. Low value may mistrigger the logic reading that output
telling that FPGA has some data to send; meantime, FPGA itself is reseting.
How can we ensure, that the output goes directly into correct high state
right after power-up without being pulled down for a while?
> As for the simple code snip you posted previously, I am not sure if that
> would do anything in a timing simulation or the chip itself for that
> matter. I would need to see the rest to be sure but based on what I
> saw, most likely what would happen if the circuit was not optimized to a
> 'logic 1' on that output would be that the GSR would drive that inferred
> FF to a 'logic 1' so that at 100 ns when you should start driving your
> stimulus, that register will already be a 'logic 1'. I think your test
> is a little too simple to try to figure out FPGA functionality or
> timing. You might want to try a little more substantial test where the
> FF is at least clocking in data to better understand how this would be
> inplemented. My guess at what your issue ther is that this example is
> so simple it is being optimized to the point that you are not seeing
> what you might expect.
If the example would be optimized into '1', the output would not depend on
reset, but 100 ns reset is required to let output (and register) go high. I
think XST infers a latch in that example. But result is the same (output is
low during 100 ns after timing simulation start) for the more complex FF
example as well:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TEST_RESET is
port (
DBG_X : out std_logic;
CLK : in std_logic; -- system clock signal
RESET : in std_logic -- Reset input
);
end TEST_RESET;
architecture RTL of TEST_RESET is
signal X: boolean;
begin
DBG_X <= '1' when X else '0';
REG: process (CLK, RESET)
begin
if RESET = '1' then
X <= True;
elsif Rising_Edge(Clk) then
X <= not X;
end if;
end process;
end RTL;
... and test bench for it
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
entity TB is
end TB;
architecture BEH of TB is
component TEST_RESET port (
DBG_X: out std_logic;
CLK : in std_logic; -- system clock signal
RESET : in std_logic -- Reset input
);
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested
entity
signal CLK : std_logic;
signal RESET : std_logic;
-- Observed signals - signals mapped to the output ports of tested entity
signal DBG_X : std_logic;
constant PERIOD: TIME := 1 ns;
begin
UUT : component TEST_RESET
port map (
DBG_X => DBG_X,
CLK => CLK,
RESET => RESET
);
RUN: process
begin
RESET <= '1';
-- wait for 40 ns;
-- wait for 100 ns;
wait for 1 ns;
RESET <= '0';
wait for 1 ms;
wait;
end process;
CLOCK : process
begin
CLK <= '0'; wait for PERIOD/2;
CLK <= '1'; wait for PERIOD/2;
end process;
end BEH;
Article: 67834In article <slrnc5mm2o.7e0.ldoolitt@recycle.lbl.gov>, Larry Doolittle <ldoolitt@recycle.lbl.gov> writes: |> Infer flip-flops instead. In Verilog: |> |> reg foo; |> always @(posedge clk) foo <= some_expression; |> |> or the more verbose and not necessarily more useful: |> |> reg foo; |> always @(posedge clk or posedge rst) if (rst) begin |> foo <= 0; |> end else begin |> foo <= some_expression; |> end |> |> I'll leave the VHDL versions to someone else. |> My fingers get tired too quickly. ;-) As if if rst='0' then foo<='0'; elsif clk'event and clk='1' then foo<=some_expression; end if; would be any more typing than your Verilog example... (Just for curiosity: Any reason for triggering on the reset's rising edge instead of its level?) And you don't even need to explicitly define foo to be a register :) RainerArticle: 67835
STD resets immediately to '1'. At the same time, it takes 100ns for BOOL to go from False to True. REG: process (CLK, RESET) begin DBG_BOOL <= '1' when BOOL else '0'; DBG_STD <= STD; REG: process (CLK, RESET) begin if RESET = '1' then BOOL <= True; STD <= '1'; elsif Rising_Edge(Clk) then BOOL <= not BOOL; STD <= not STD; end if; end process; end RTL;Article: 67836
Hi I am compling a design in Xilinx ISE 6.1 SP3. When a timing analysis is done using error report, it reports few setup errors. But when I run the same with verbose report, it doesn't repert. In the former case, how can I find where the errors are happening as the tool doesn't give any clue. Any help is appreciated. AnjanArticle: 67837
"Eric Crabill" <eric.crabill@xilinx.com> skrev i meddelandet news:405B96DC.6E48295A@xilinx.com... > > Hi, > > For that board, specifically, the smaller chip is a Xilinx > ISP PROM that contains the bitstream. There are also some > jumpers to which you may attach a download cable, which can > send the bitstream to the device directly. That is only > useful for prototyping and debug. > > > Also, What kind of PCI cards have you developed with the > > help of this card? > > I've done a number of designs with it; one was a RAMDisk that > used the SDRAM as storage, another was a video peripheral to > drive a VGA monitor. I haven't had any problems with this > card. All the designs I did used the v3.0 PCI LogiCORE from > Xilinx, and I didn't have any problems with that, either. :) > > Eric But the LogicCORE component isn't integrated on your card (correct me if I'm wrong but I can't see it on the schematics)? did you simply add it to the schematics when you had tested your projects, assuming it would work? Did you ever simulate your projects in a SPICE enviroment? Where did you find the models for it? //SPikeArticle: 67838
Hi Spike,
See my comments below.
Spike wrote:
>
>
> I looked at the "Included" list and didn't find any IDE or similiar for
> development of VHDL programs. Do I have to buy that separate?
You sound like a hardware novice who has some software
experience.
As far as I know, hardware engineers don't use the word "program" when
describing hardware designs done in HDL.
Anyway, Insight Electronics sells a version of Spartan-II 200 PCI card
with the free version of the design software (ISE WebPACK) and a
parallel port JTAG card for $275 (Look for DS-KIT-2S200-PAK or
DS-KIT-2S200-PAK-EURO mentioned in the PDF file.).
Or, you can download Xilinx ISE WebPACK from Xilinx for free which
contains a synthesis tool that can synthesize a Verilog or VHDL design.
http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack
Xilinx also lets you use an HDL simulator called ModelSim
XE-Starter for free, however, because it is free, the simulation slows
down if the design is larger than 500 HDL statements, but it won't
prevent the user from simulating the design (Gives you a warning, but
you can ignore it.).
I myself use the same simulator, and it should be good enough for a
hobbyist.
>
>
> While I'm waiting for the card I will try to read some books on FPGA's, VHDL
> and so on. Once I get it I will try to
> test a couple of test - examples that I hope are included just to see how
> the machine really works.
>
> After a while I will try to build a valid PCI Configuration Space (what
> Vendor/Device ID's did you use? are there any reserved for hobby purpose?)
> to test if my PCI design works. As soon as the design works I will try to
> read the PCI spec(s). more carefully to learn how the mechanical &
> electrical parameters should be implemented.
>
As a guy who is trying to make money from licensing a PCI IP
core I developed, I don't recommend FPGA beginners to suddenly start a
doing a PCI interface (Obviously, I am biased.) because you will likely
go through a steep learning curve in the process.
Instead, I recommend using a PCI IP core, so that you won't have to deal
with various nasty aspects of PCI like timing closure or certain valid
protocol variations among different chipset implementations.
Also, setting up the simulation environment is also important, and I had
to spend much more time than I wanted on that.
Most PCI IP cores I know of, you can set the Vendor ID or Device
ID to whatever value you please to, so for non-commercial purposes, the
lack of an official Vendor ID should not be a problem (It costs $3,000
if I am correct to become a PCI-SIG member, and obtain a Vendor ID.).
In your case, I will say that use a Vendor ID no one is currently using.
You shouldn't have to worry with the electrical or mechanical
aspects if you bought a PCI prototype card, but if you are going to
design your own PCI interface, you will have to worry about timing
constraints (Especially, setup time.) if you want to play it safe.
Again, if you license my PCI IP core, you will get a constraint file for
the Insight Electronics Spartan-II 200 PCI card (Or for the Avnet
Spartan-3 PCI card if someone is willing to provide me the PCI pin out
of the Spartan-3.), which will ensure easy timing compliance.
Basically, using a PCI IP core can potentially save you somewhere from
two to six months off your design time, so that you can concentrate on
the user logic (The part you should be worried about.)
> But the real purpose of building a PCI card will be (in the beginning) just
> for fun. After a while I might try to build a I/O controller and maybe add
> something more advanced.
>
> If you know of any good books on VHDL, FPGA with PCI in mind or similar I
> would be glad if you could tell me.
>
> How did you start?
>
> Thanks for your help!
>
> //SPike
>
One document that should be helpful is PCI Local Bus
Specification Revision 2.2 or 2.3's Appendix B, which gives you two
state machine examples, and it was very helpful when I developed my PCI
IP core, however, the state machine examples have various details
omitted for clarity, so you will have to figure out the details
yourself.
I am reluctant on giving recommendation on HDL books because what I
found out was that, most books about HDL typically plunge into too much
details beginners have no clues about, or lack interesting enough
examples to keep the reader interested.
Instead, what I recommend is to license my PCI IP core because it will
come with a simple 16 byte I/O mapped reference design (The backend
design just doesn't get any easier than this.), and that design should
be simple enough for a beginner to understand how to build and simulate
a simple PCI device.
After you get comfortable with it, you should be able to develop your
own PCI device using HDL.
Kevin Brace
P.S. Remove the weird numbers from my E-mail address when contacting me.
Article: 67839arvindstomar@india.com (arvind) wrote in message news:<56147fd4.0403190344.796d99e9@posting.google.com>... > Hi all, > So many Books and articles on Web told me to Avoid Infer > latches in design, But Thay did't give the Proper reason behind this > and i did't convince. So can anybody give me the Short and Sweet > answer about my Question "why it is recommended to avoid latches in > Digital Designs?" > > Thanks for any Reply. > > Best Regards > Arvind Singh Tomar. If you do serious cpu design and have really good tools and design sense, its ok to use latches with out master slave, provided all paths have similar delays. This was common in ECL days and still is in some high perf CMOS cpus. Using an edge FF for the pipeline makes most peoples lives easier, but there is a very small penalty that is noticable only at extreme perf levels. I have used latches in a mixed signal chip, 1 master latch can serve an array of slave latches, makes the whole array look syncronous to the ck edge and halves the memory size, but it was also hand layed out. None of the above applies to FPGA, you will have no control over anything and your timing will be horrible so forget it. FPGA design is not ASIC design. regards johnjakson_usa_comArticle: 67840
Hi Thomas, 15 month ago, I designed an LVDS communication interface using a Xilinx Spartan-II-5 and some simple external LVDS transceivers from TI - 2 US$ devices. Running at 100 MHz is of no problem conecering the FPGA. Clock and Data - serialized - is being xmitted and received through a customised RJ45 cat-5 cable. I did not chk the maximal length, since it has not been an issue ... The experience I made so far is, that is MANDATORY to add a low impendance ground path within the cable. The device - all LVDS devices - are very sensitive to common mode differences in between the xmitter and the receiver ... ~ 1 Volt or 2 is enough to completely disturb the differential transmisstion. Some more volts and the device has gone ... forever. Markus Thomas Kurth <thomas.nospam@gmx.net> wrote in message news:<MPG.1ab797b9709e1ba99896ef@127.0.0.1>... > Hello NG, > > we are planning a high speed data transmission between several devices. > We now found the LVDS standard. I found some pages in the WWW which told > me some things about cable lengths. But it might be not enough... We > would need a transmission rate of 100 MBit and a transmission length of > some ten meters (ok, my boss wants a km, but I think that this is > impossible if we want to use an electrical standard... This should be an > optical solution). Does anyone now how far we can use LVDS using > 100MBit? Has anyone already designed such a transmission line? > > Any help is appreciated. Thanks. > > Greetz, > > Thomas KurthArticle: 67841
Anjan wrote:
> Hi
> I am compling a design in Xilinx ISE 6.1 SP3. When a timing analysis
> is done using error report, it reports few setup errors. But when I
> run the same with verbose report, it doesn't repert. In the former
> case, how can I find where the errors are happening as the tool
> doesn't give any clue. Any help is appreciated.
> Anjan
Howdy Anjan,
I've seen this too (and it seems, almost every other Xilinx bug) on rare
occasions. My only guess is that the files that Timing Analyzer is
using aren't up-to-date, because as I recall, I got it to go away by
selecting Timing Analyzer and force it to re-run.
Good luck,
Marc
Article: 67842Hi, > But the LogicCORE component isn't integrated on your card > (correct me if I'm wrong but I can't see it on the schematics)? > did you simply add it to the schematics when you had tested your > projects, assuming it would work? The schematics of the physical board have no relation to the hardware design for the internal operation of the FPGA device on the physical board. You would use the LogiCORE in your Verilog or VHDL design description of the FPGA behavior, and you ultimately turn that description into a bitstream to program the FPGA. > Did you ever simulate your projects in a SPICE enviroment? No. EricArticle: 67843
> If I understand corretly, FPGAs have about 100ns internal reset. This means > that we do not need for any explicit RESET in test bench at all; we just > need to wait for 100ns for reset to complete. However, my observation shows > that test bech must provide at least 100 ns reset for registers to > initialize. > > As you see, one of the outputs depend on state of registers. Both register > and the output are (strong?) low during 100 ns reset; meantime they should > be initially high. Low value may mistrigger the logic reading that output > telling that FPGA has some data to send; meantime, FPGA itself is reseting. > How can we ensure, that the output goes directly into correct high state > right after power-up without being pulled down for a while? All storage elements have the attributes SRHIGH,SRLOW, INIT0 and INIT1. INIT0/1 determine the state the ffs go into after configuration/global reset. INIT0 forces '0' while INIT1 forces '1'. SRHIGH/LOW is determined by the user set/reset value. Hence if you were setting your ff to '1' the SRHIGH attribute is set and '0' sets SRLOW. By default setting SRHIGH sets INIT1 and SRHIGH sets INIT1. Now the INIT0/1 attributes can be set in your VHDL code by defining the INIT atrribute. Example: If your code has a registered signal X then signal X : std_logic; attribute INIT : string; attribute INIT of X : signal is "1"; -- if you want to set INIT1 if "1" is changed to "0" then INIT0 will be set. In your case X is defined as a boolean. For some reason, which I don't know but something to do with boolean (maybe some one on this news group would be able to explain), your ff's INIT0 is set even though you have SRHIGH set. This is why your output is LOW for 100 ns. You can see the attributes in FPGA editor. A simple fix is to change your boolean declaration to std_logic. SudhirArticle: 67844
Because latch is level sensitive, instead of edge sensitive. So, as long as the enable of your latch is asserted, whatever coming in from the input will show up at the output. That is dangerous because usually the input to your latch is a combinational logic. And combinational logic is subject to glitches. So, if you are going to use a latch, you have to make sure that during the entire time when the enable of your latch is asserted, the output from your combinational logic will never have any glitches. The case is different if you use a flip flop. The input to your flip flop only need to be stable shortly before the rising edge of the clock and shortly after the rising edge of the clock. That will live much easier because you just need to make the period of your clock long enough to make sure that by the time of the rising edge of the clock, the output from your combinational logic is already stable. Thanks! Hendra ----- Original Message ----- From: "arvind" <arvindstomar@india.com> Newsgroups: comp.arch.fpga Sent: Friday, March 19, 2004 3:44 AM Subject: Why It Is not Recommended to Infer latches in VLSI Design... > Hi all, > So many Books and articles on Web told me to Avoid Infer > latches in design, But Thay did't give the Proper reason behind this > and i did't convince. So can anybody give me the Short and Sweet > answer about my Question "why it is recommended to avoid latches in > Digital Designs?" > > Thanks for any Reply. > > Best Regards > Arvind Singh Tomar.Article: 67845
I am sorry to interrupt but if you already have your own non-PCI development board, such as D2E board from digilent, is it possible that you can just use an adapter to connect your board to the PCI slot? Thanks! HendraArticle: 67846
> And combinational logic is subject to >glitches. So, if you are going to use a latch, you have to make sure that >during the entire time when the enable of your latch is asserted, the output >from your combinational logic will never have any glitches. That's not obvious to me. Am I missing something? You do have to make sure that glitches don't get connected to clock inputs or any other place where they might cause troubles. But they don't cause any trouble going into the data input of the latch. They will flow through the latch so you have to check the other side of the latch. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 67847
Hi. How can I run Xilinx map with -timing option through the ise gui ? Currently I am using command line, but I wish to use the ise gui. ThankX, NAHUMArticle: 67848
Kelvin wrote: > Yeah, source code is there... > It's a good example to study a microprocessor design. If you want to do that, have a look to this SPARC V8 processor under GPL license : http://www.gaisler.com/leonmain.html Marc -- Réponse par email http://cerbermail.com/?C9OVeUlzPc Answer by email http://cerbermail.com/?C9OVeUlzPcArticle: 67849
Thanks for looking. What I got is some .src files with only input/output pin declarations (pin number and variable name) and then logic equations for the output pins VS input states. This file is representing a 16L8 PAL supposedly. What I need is to go from here to a PAL JEDEC file suitable for programming, by what method(s) please? I'm new at this and would dearly like to know if anyone can recognize this simple .src format and name any software that can use it.
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