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Dave, I'd estimate at least $700K/yr for Atlanta, and about 20% more for San Jose -- especially since this person will need to do technical documentation/marketing material. Bob "Dave" <no@spam.com> wrote in message news:d3oo69$1ft$00$1@news.t-online.com... > Hi to all, > > Just wondering if you could give me an idea of a current salary ballpark for > the following details/person: > > Person: > PhD in DSP on FPGA (3.5 years of RTL VHDL mainly for Xilinx and C++ > development) > 1st class honours degree in Software Development/Electronic & Electrical > Engineering > 1 years industry experience (+ some during PhD) > sales training/experience > extensive presentation writing/giving experience > > Job description: > DSP on FPGA design in RTL VHDL on Xilinx/Altera/Lattice/Actel etc. > C++ development > Customer visits/application support > Technical documentation/marketing material > Presentations to customers/conferences/seminars > > Job Location: > Please give an idea for Atlanta and San Jose > > Thanks very much in advance for your time > >Article: 82676
On 13 Apr 2005 06:21:03 -0700, "Mohammed A Khader" <am.imak@gmail.com> wrote: >Hi all, > > I am new to FPGA architecture. Welcome. >To know the what does LUT means I came >across few good articles posted in this group. >But still not completely clear about it. > >A 4-bit input LUT in spartan 2 can be implemented as Function >Generator or as 16-bit ROM ... accepted . You need to accept it more fully :-) Think of a ROM the following way: 16 flipflops (storage) each one either set or clear, and no clock to the flipflops. Take the output of the 16 FFs, and connect them to a 16 to 1 mux. The mux will need 4 control lines. When the control lines are 0000, the output of the mux is the value in FF_0 , when it is 1111, the mux output is the value in FF_15. So really, there is no difference between calling it a LUT or a ROM. It holds 16 bits, and via the mux, you can select to look at any 1 bit. >But I can't imagine it as a 16-bit RAM or a shift Register. Let me help your imagination, in stages. First, lets take the 16 FFs I described above (without clocks, but somehow preset to either 0 or 1), and lets add an async set and clear line to each FF. We can now force the value of each FF via these new signals. This is equivalent (but not actually) the way the FPGA uses the configuration data to initialize the FFs that make up the ROM/LUT. Now, lets add a common D and common clock input to each FF, and also a clock enable to each FF (16 of them). Add a 4 line to 16 line decoder and connect it to the 16 clock enable lines. The 4 inputs to the decoder are connected to the 4 control lines of the output selection mux. So when these 4 lines are 0000, the output mux shows us the content of FF_0, and if we put a 0 or 1 on the D input line (that goes to all FFs), and apply a rising clock edge (that goes to all FFs), then only FF_0 will be loaded with the data on D, because the decoder is only enabling the clock on FF_0. What we now have is a RAM. >If it is a 16-bit Ram / Shift Register then where is the input port. There are 3 extra inputs, Clock, Write Enable (WE), and Data (D) To turn the 16 FFs into a shiftregister, we need to add some additional logic so that rather than only clocking 1 FF at a time (RAM mode), we enable clocking of all 16 FFs, and rather that the 16 D inputs all comming from a common D signal, the D signal only connects to FF_0. The D of FF_n connects to the output of the prior FF, Q_n-1. Thus we have a shiftregister. >I think input port to LUT is only available during configuration of >FPGA but not to the designer. This is true of the early Xilinx FPGA products, the XC2000 and XC3000 families. All Xilinx FPGA products since the XC4000 family (1990) have had the RAM capability, and the SRL capability became available in the Virtex-II product line (2001). > Also please suggest me some good books to know the architecture of >FPGA. The US patent office makes available all patents on-line, for free. You "just" need to search for the appropriate patent. start here: http://patft.uspto.gov/netahtml/search-bool.html Try search terms like "RAM" and "XILINX". Here let me help you. try 5566123 , it includes complete detailed schematics, including something you didn't ask about, Dual-Port. > Thanks . >-- Mohammed A Khader. Unfortunately the folling has several errors. On Wed, 13 Apr 2005 16:19:28 +0200, Laurent Gauch <laurent.gauch@DELETEALLCAPSamontec.com> wrote: >DO NOT CONFUSE LUT and CLB Mohammed never mentioned CLBs >Sorry but a LUT is : Logic Unit Table -> a LUT can only do combinatory works (AND OR >XOR ...). No. It is Look Up Table. >CLB is: Configurated Logic Block -> a CLB include one LUT followed by >one Flip-Flop in minimum. True enough, but irrelevant to the question. >For some Xilinx FPGA the CLB can be use as RAM or as SRL (not the LUT >itself ;-) ) No. The LUT IS what is used to implement the RAM or SRL. >After that advice, please open a FPGA datasheet for understanding it >specific architecture ! Sure. Happy learning, Philip =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 82677
this Simon.. is a professional :-) but thoughts and ideas expressed by Simon may not be the same as all Simons. "Simon" <news@gornall.net> wrote in message news:rrOdnXY7xaVu9P3fRVn-qg@comcast.com... > JJ wrote: > > I'd imagine most people here are employed, consultants, small business, > > occasional blue chip EEs etc beside the FPGA vendor reps. The traffic > > reflects the niggling details that make simple things harder than 1st > > seems and a little ragging on the vendors to boot. Not sure if open > > source is of that much interest here except to the entry level or for > > educational purposes. > > > > The free semi free tools are a great way for vendors to rope in new > > paying customers perhaps a future woz or 2 will give them larger order, > > no OSS agenda here. > > > > Since FPGAs are heading up into low end ASIC territory, not sure if > > hobbyists will become a major deal here, mostly serious hobyists are > > perhaps buddying engineers. It may seem as if FPGAs are a little > > reminiscant of the 70s computer clubs but I don't expect to see > > homebrew clubs popping up. > > Well, I'm a hobbyist. It makes a change from coding software for a > living, at least when I can fit it in :-) > > The problems for hobbyists aren't really the vendors, or the tools, or > even the large quantities of relatively domain-specific knowledge > required. It's getting to grips with the teeny-weeny-pin soldering > issues (at least it is for me). That's when you can get the parts in > home-solderable form at all, eg: largest S3 is a PQ208. Whoosh. By the > time you've added memory and a few peripherals, you're seriously out of > pins :-( *And* it's a bitch to solder... > > Yes, I know there are good reasons (trust me - this is me being > understanding :-) You really don't want to hear me whining about > something :-)) Question though - would pin-grid array have the same > signal integrity issues as BGA ? Or is it a function of lead-length > rather than pin geography ? At least PGAs are solderable... > > I don't really expect A,X,whoever to produce parts that help the > hobbyist, but it's immensely frustrating to get a quote of $350/board > (inc. assembly/x-ray testing) when the part is "under 10$", well ok, $50 > in my quantities... > > It's actually cheaper to buy a development board for deployment (eg: > AVNET virtex-4 FX-12 board) as well as development, which is a bit weird > really! > > Simon.Article: 82678
Can anyone provide a recommendation on which journal or transaction series one ought to subscribe to in the IEEE family which provides the most coverage on FPGAs? Computer Aided Design of Integrated Circuits and Systems, IEEE (TCAD) Very Large Scale Integration Systems (TVLSI) Solid-State Circuits (J-SSC) Thanks in advance ....Article: 82679
depends... Do you normally add "Would you like fries with that?" Simon "Dave" <no@spam.com> wrote in message news:d3oo69$1ft$00$1@news.t-online.com... > Hi to all, > > Just wondering if you could give me an idea of a current salary ballpark for > the following details/person: > > Person: > PhD in DSP on FPGA (3.5 years of RTL VHDL mainly for Xilinx and C++ > development) > 1st class honours degree in Software Development/Electronic & Electrical > Engineering > 1 years industry experience (+ some during PhD) > sales training/experience > extensive presentation writing/giving experience > > Job description: > DSP on FPGA design in RTL VHDL on Xilinx/Altera/Lattice/Actel etc. > C++ development > Customer visits/application support > Technical documentation/marketing material > Presentations to customers/conferences/seminars > > Job Location: > Please give an idea for Atlanta and San Jose > > Thanks very much in advance for your time > >Article: 82680
On Fri, 15 Apr 2005 18:27:10 -0700, Simon wrote: > JJ wrote: >> I'd imagine most people here are employed, consultants, small business, >> occasional blue chip EEs etc beside the FPGA vendor reps. The traffic >> reflects the niggling details that make simple things harder than 1st >> seems and a little ragging on the vendors to boot. Not sure if open >> source is of that much interest here except to the entry level or for >> educational purposes. >> >> The free semi free tools are a great way for vendors to rope in new >> paying customers perhaps a future woz or 2 will give them larger order, >> no OSS agenda here. >> >> Since FPGAs are heading up into low end ASIC territory, not sure if >> hobbyists will become a major deal here, mostly serious hobyists are >> perhaps buddying engineers. It may seem as if FPGAs are a little >> reminiscant of the 70s computer clubs but I don't expect to see >> homebrew clubs popping up. > > Well, I'm a hobbyist. It makes a change from coding software for a > living, at least when I can fit it in :-) > > The problems for hobbyists aren't really the vendors, or the tools, or > even the large quantities of relatively domain-specific knowledge > required. It's getting to grips with the teeny-weeny-pin soldering > issues (at least it is for me). That's when you can get the parts in > home-solderable form at all, eg: largest S3 is a PQ208. Whoosh. By the > time you've added memory and a few peripherals, you're seriously out of > pins :-( *And* it's a bitch to solder... > > Yes, I know there are good reasons (trust me - this is me being > understanding :-) You really don't want to hear me whining about > something :-)) Question though - would pin-grid array have the same > signal integrity issues as BGA ? Or is it a function of lead-length > rather than pin geography ? At least PGAs are solderable... > > I don't really expect A,X,whoever to produce parts that help the > hobbyist, but it's immensely frustrating to get a quote of $350/board > (inc. assembly/x-ray testing) when the part is "under 10$", well ok, $50 > in my quantities... > > It's actually cheaper to buy a development board for deployment (eg: > AVNET virtex-4 FX-12 board) as well as development, which is a bit weird > really! > > Simon. Nowadays people are soldering surface mount parts themselves in toaster ovens. I think you can even do BGA's this way. Have you checked out the PCBexpress website? If not, have a look. www.pcbexpress.com. They make circuit boards, but they also have a lot of information about hobbyist / low-volume production techniques. Mind you, I haven't done any of this stuff myself, yet, but I would much rather cook a board in the oven than try to solder it, even if it doesn't have any BGA's on it. Of course, with BGA's, hand-soldering is not an option. --MacArticle: 82681
On Sat, 16 Apr 2005 04:55:42 +0000, Bob wrote: > Dave, > > I'd estimate at least $700K/yr for Atlanta, and about 20% more for San > Jose -- especially since this person will need to do technical > documentation/marketing material. > > Bob > Do normal people really make 700k a year purely in salary? My first reaction is that you are making a joke. I would have guessed 150-200k for a PhD with only a little relevant experience, but that would have been nothing but a guess. That is, I don't know any PhD's (in EE). How long does it take to get a PhD? If it's only five or six years, it may actually be worth it! ;-) --Mac > > "Dave" <no@spam.com> wrote in message > news:d3oo69$1ft$00$1@news.t-online.com... >> Hi to all, >> >> Just wondering if you could give me an idea of a current salary ballpark > for >> the following details/person: >> >> Person: >> PhD in DSP on FPGA (3.5 years of RTL VHDL mainly for Xilinx and C++ >> development) >> 1st class honours degree in Software Development/Electronic & Electrical >> Engineering >> 1 years industry experience (+ some during PhD) >> sales training/experience >> extensive presentation writing/giving experience >> >> Job description: >> DSP on FPGA design in RTL VHDL on Xilinx/Altera/Lattice/Actel etc. >> C++ development >> Customer visits/application support >> Technical documentation/marketing material >> Presentations to customers/conferences/seminars >> >> Job Location: >> Please give an idea for Atlanta and San Jose >> >> Thanks very much in advance for your time >> >>Article: 82682
In article <d3pr78127f2@enews2.newsguy.com>, Phil Tomson <ptkwt@aracnet.com> wrote: > Well, much cheaper tools anyway ;-) I can't afford ModelSim, but I can > download and compile Icarus or GHDL (both open source) for all of my HDL > simulation needs. Are they as slick as ModelSim? No, but they're > actually pretty capable and I get things done with them. Eh. I just log into work over the VPN link, and use Modelsim for my own projects. And Synplicity. And the full Xilinx tools. All from my laptop wirelessly from my couch. :) Yes, you may throw things at me now. Bosees don't mind as long as its after hours and the Suns are just sitting there counting out time.Article: 82683
has anyone figured out how to do a cvs operation using HDL Designer? i use cvsroot as :extssh:name@domain:/cvsroot_path and get the error "Error: cvs.exe add: unknown method in CVSroot: ..... cvs.exe [add aborted]: Bad CVSROOT.Article: 82684
There are ISE Foundation and ISE Webpack versions for Red Hat Enterprise Linux 3.0 How strict is this port? Has anybody managed to run these tools on Fedora or Mandrake Linux (now Mandriva), or any other Linux variant? If so, how well did it work?Article: 82685
In article <iV08e.7071$yq6.1107@newsread3.news.pas.earthlink.net>, Bob <nimby1_notspamm_@earthlink.net> wrote: >Dave, > >I'd estimate at least $700K/yr for Atlanta, and about 20% more for San >Jose -- especially since this person will need to do technical >documentation/marketing material. > $700K/yr! Wow, where do I sign up?! PhilArticle: 82686
Just downloaded, thanks very much! Dani "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:d3ml4e$9da$05$1@news.t-online.com... > ok I wasnt lazy the freelib1 is now downloadable > http://gforge.openchip.org/projects/wwwfreeipcom/ > > antti > > "Daniel Florin" <florin@primelec.ch> schrieb im Newsbeitrag > news:d3ma49$pm4$1@news.hispeed.ch... >> Over the last couple of weeks I have tried accessing the web site >> www.free-ip.com and gotten an error message. Is it mirrored someplace >> else >> on the web? >> >> I am looking for Free-LIB1, a library of NCO, DAC and PWM parameterized >> cores in VHDL, which was available at www.free-ip.com. >> >> Any information is very appreciated. >> >> > >Article: 82687
Hello, I am searching how to specify a relative timing constraint (and not a placement constraint) that would be enforced either by the VHDL synthesis tool or the place and route tool in the following case (decoding of a serial link data/strobe like the one depicted in figure 5 of http://products.sel.sony.com/semi/PDF/wpIEEE1394.pdf ) : * the serial link is made of one data line D and one strobe line S * the clock CLK at half bit rate is regenerated by an XOR between D and S * the data signal D is sampled on both the rising edge and the falling edge of CLK. The problem is that when the clock edge is caused by a change on the D line, the setup time is very dependant on the routing of D, S and CLK. Manual placement constraints allow to solve the problem, but it is rather tricky. I would prefer to find a way to specify a relative timing contraint between D and CLK. MarcArticle: 82688
Mac wrote: > On Sat, 16 Apr 2005 04:55:42 +0000, Bob wrote: > > >>Dave, >> >>I'd estimate at least $700K/yr for Atlanta, and about 20% more for San >>Jose -- especially since this person will need to do technical >>documentation/marketing material. >> >>Bob >> > > > Do normal people really make 700k a year purely in salary? My first > reaction is that you are making a joke. > > I would have guessed 150-200k for a PhD with only a little relevant > experience, but that would have been nothing but a guess. That is, I don't > know any PhD's (in EE). > > How long does it take to get a PhD? If it's only five or six years, it may > actually be worth it! ;-) Well, to join two threads together, if a 'professional' in this industry makes $700k/year, I'm about to become a professional! And I already have a PhD :-) [it takes 3 years in the UK, on average btw] I'm sure that was just a reaction post to an open-ended question though. Please tell me I'm right, or I'll have wasted the last 10 years (!) ATB, Simon (the unprofessional one. Oh, wait!)Article: 82689
Mac wrote: > > Nowadays people are soldering surface mount parts themselves in toaster > ovens. I think you can even do BGA's this way. > > Have you checked out the PCBexpress website? If not, have a look. > www.pcbexpress.com. They make circuit boards, but they also have a lot of > information about hobbyist / low-volume production techniques. Yep, and pad2pad (who are cheaper, in general). PCBExpress (or rather, screaming circuits, their partner) want ~$650 for 1 board I was thinking of (10 IC's, 1 BGA, a few through-hole components). Pad2pad were $350 for the same. It makes 'hobbyist' a bit expensive... > Mind you, I haven't done any of this stuff myself, yet, but I would much > rather cook a board in the oven than try to solder it, even if it doesn't > have any BGA's on it. Of course, with BGA's, hand-soldering is not an > option. Like you, I've heard of it, but not actually done it. I intend to though. I've read some of the articles and I'll be purchasing one of these 'toaster' ovens (a strange term!) RSN(tm). I'm off to Vegas for a week (trade show) so it'll have to wait a bit longer... The PQ208's aren't actually that bad - it takes a bit of practice, which is itself expensive! But once you've the knack, you can knock out a board in a few hours - and that includes the inspection with a magnifying glass to find the solder joins... I have heard of people using vias to mate with the balls of the chip and soldering from below, filling the vias like little ink-wells. Sounds like a good way to destroy a chip to me :-) ATB, SimonArticle: 82690
>> Just wondering if you could give me an idea of a current salary ballpark > for >> the following details/person: >> >> Person: >> PhD in DSP on FPGA (3.5 years of RTL VHDL mainly for Xilinx and C++ >> development) >> 1st class honours degree in Software Development/Electronic & Electrical >> Engineering >> 1 years industry experience (+ some during PhD) >> sales training/experience >> extensive presentation writing/giving experience >> >> Job description: >> DSP on FPGA design in RTL VHDL on Xilinx/Altera/Lattice/Actel etc. >> C++ development >> Customer visits/application support >> Technical documentation/marketing material >> Presentations to customers/conferences/seminars >> >> Job Location: >> Please give an idea for Atlanta and San Jose > I'd estimate at least $700K/yr for Atlanta, and about 20% more for San > Jose -- especially since this person will need to do technical > documentation/marketing material. I think, there is a '0' too much (if it was not a joke alltogether ;-), otherwise I'll buy a ticket to the Bay Area... (I am from Europe) ThomasArticle: 82691
Hi I wonder if I could find online a good introduction to start with FPGA and hardware design. So the document should say something about the trade of between performance and size, how the critical path determines the system performance and so on. Does anybody know a good online ressourse for this basis stuff? thanksArticle: 82692
In article <zG28e.2191$J12.2162@newssvr14.news.prodigy.com>, David <dmsbox2000-news1@yahoo.com> writes: |> There are ISE Foundation and ISE Webpack versions for Red Hat Enterprise |> Linux 3.0 How strict is this port? Has anybody managed to run these |> tools on Fedora or Mandrake Linux (now Mandriva), or any other Linux |> variant? If so, how well did it work? Debian and SuSE work nicely. Just the usual environment variable hassles. RainerArticle: 82693
On 15 Apr 2005 06:41:48 -0700, Puneetsingh81@gmail.com (CODE_IS_BUG) wrote: >if i am having a set of modules which reference some common control >registers and each of these modules can read or write to these >registers then there is a severe problem of 'bus' first of all and >secondaly the 'mode' of the control registers(INOUT??). Is there any >design reference or document that may be of help to me? The first thing I would do is re-think the design approach. Having multiple writers of a resource is usually just a bad idea. If the situation is that different modules write to mutually exclusive bits of the registers, then you just need to break these registers up into separate registers. If the writers are trully writing to the same bits, and this is really what you want (see the start of my reply), then you could do something like have multiple registers, and then mix their outputs (OR, AND, priority, ...). The problem really comes down to what happens if 2 or more writers both try to write at the same time. How is this resolved. A complex solution to this might be something like a separate module for these annoying registers, that takes in a bus and a write request from each of the writers. Inside this module is where you decide what to do with simultaneous writes. On the third had, re-think, and change your design approach. Philip Freidin Philip Freidin FliptronicsArticle: 82694
In article <4260ca75$0$32388$91cee783@newsreader02.highway.telekom.at>, "Thomas Entner" <aon.912710880@aon.at> writes: |> I think, there is a '0' too much (if it was not a joke alltogether ;-), |> otherwise I'll buy a ticket to the Bay Area... (I am from Europe) Consultant job in the NYC metro area as a freshly graduated PhD, ~100K/yr A Friend of mine is working at LLNL (after a Postdoc year at Cornell), ~120K/yr Thomas: In Europe they don't pay their PhD nearly as well. They just wonder why everyone who has the chance to work in the US does it... RainerArticle: 82695
On Sat, 16 Apr 2005 06:56:31 +0000, David wrote: > > > There are ISE Foundation and ISE Webpack versions for Red Hat Enterprise > Linux 3.0 How strict is this port? Has anybody managed to run these > tools on Fedora or Mandrake Linux (now Mandriva), or any other Linux > variant? If so, how well did it work? They run fine on Fedora Core 3 once you have them installed. The only problem is the installer which is looking for an older version of the libcurl library. You can do a soft link between the version in FC3 and the required version. ln -s /usr/lib/libcurl.so.3.0.0 /usr/local/lib/libcurl.so.2 If that doesn't work for you then the other alternative is to use RHEL3 or a clone, I used Whitebox Linux, to do the install and then you can rsync the directories to your other machines.Article: 82696
> Dave, > > I'd estimate at least $700K/yr for Atlanta, and about 20% more for San > Jose -- especially since this person will need to do technical > documentation/marketing material. $70k right!?Article: 82697
> How long does it take to get a PhD? If it's only five or six years, it may > actually be worth it! ;-) In the UK it is usually 3/4 years. More like 5/6 in Europe though I think....Article: 82698
> Well, to join two threads together, if a 'professional' in this industry > makes $700k/year, I'm about to become a professional! And I already have a > PhD :-) [it takes 3 years in the UK, on average btw] Any salary insights then based on your experience? Cheers DaveArticle: 82699
> Consultant job in the NYC metro area as a freshly graduated PhD, ~100K/yr > > A Friend of mine is working at LLNL (after a Postdoc year at Cornell), > ~120K/yr > > Thomas: In Europe they don't pay their PhD nearly as well. They just > wonder > why everyone who has the chance to work in the US does it... I expect living costs in the NYC metro area are higher than Atlanta for example? Pretty good salaries - does put Europe in the shade a little....
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