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"Jerry Avins" <jya@ieee.org> wrote in message news:81CBD918DDBAFD53DD190E0D384E5075@in.webx.sUN8CHnE... > What is the clock source? Is id overloaded or short on settling time? > > Jerry Using LA's internal clock, I could see the external clock's posedge is at least 10ns ahead of data. When I change the sampling clock to this external clock, LA complained that the clock is too weak. I need it to sample 10 data lines, and the clock & data pin's drive strength are both 12mA in Virtex 2. Any idea on how to proceed?Article: 83126
"nashafi" <nashafi@gmail.com> wrote in message news:1114299707.678274.84510@z14g2000cwz.googlegroups.com... > I wrote a synthesizeable 4 tap FIR code in vhdl and synthesized it > using Xilinx. I have an Xess XSV board with Virtex 800 fpga on it. > I am new to FPGA programming. Can some one guide me what steps i have > to take to implement my FIR on this board . > > I believe steps will be > synthesize > Implement > generate bit file > > using xilinx ISE software > > But I used an example to implement a & segment LCD counter and i am > confused about the functionality of ucf file and how to make one for my > design i.e how i can configure inputs and outputs of my design so that > i can send an input and see what is the response as an out put on the > LCD > Take a look at the Constraint Guide ($XILINX\doc\usenglish\books\docs\cgd\cgd.pdf) installed with your ISE software. The constraint for placing pins is "LOC". HTH, Jim jimwu88NOOOSPAM@yahoo.com (remove capital letters) http://www.geocities.com/jimwu88/chips > > Thanks, > > -Nauman >Article: 83127
In Virtex2Pro, the OCM data must return in a fixed number of clock cycles. This obviously isn't a good match to external DRAM memory especially since refresh can take lots of cycles. I checked in the Virtex4 PowerPC docs and only the DSOCM has added "Optional support for variable latency for read or write data transfer" specifically to support "wide range of new applications utilizing memory-mapped I/O" (page 140: http://xilinx.com/ise/embedded/ppc405block_ref_guide.pdf) In addition, the EDK memory controllers already have plb or opb interfaces on them so you'd have to develop an OCM-interfaced memory controller. Not super difficult but using the provided controllers should get you up and running very quickly. Then you can determine what additional system-level architectural changes are appropriate for your application. Don't forget to enable the PowerPC405 caches--they make a large difference and do note that OCM accesses bypass the PowerPC405 caches. Paul Joey wrote: > > Hi BCD, > > I didn't really understand what you meant with what parts I am using. > > I am trying to implement a C program which is a little big. I tried it with > the local BRAMs and now I want to know whether I can really route the > signals out of the FPGA chip and to the peripherals on the board. I just > wanted to make the onboard SDRAM as the place for my program !! So the plan > is, to fetch the program from the SDRAM interface. Somehow I cannot increase > the Bus frequency more than 100MHz. But the SDRAM might work faster and > thats why I am trying to do this. > > Thank you > Joey > > <pilot172@gmail.com> schrieb im Newsbeitrag > news:1114181921.329786.190300@g14g2000cwa.googlegroups.com... > > > > Probably not. What parts are you using? > > > > BCD > > > > Joey wrote: > > > Hello all, > > > > > > I would like to know whether an interface like an OCM interface is > > possible > > > at all for the SDRAM !!! > > > > > > Thank you > >Article: 83128
Hi Dave, Yes. these are very different. To the best of my knowledge, Simulink supports only multi-rate systems that are in some manner synchronous. That is, you really can not model 2 (or more) asynchrounous clock domains in Simulink. As we derive implementations from the Simulink model, Synplify DSP does not, from a single model, allow for asynchronous clock domains during implementation. If the model had 2 seperate sample rate specifications for 2 completely unrelated datapaths, I think it should be OK. Synplify DSP would create 2 clock ports, that you could define as unrelated in Synplify Pro thru the timing constraints file. However, if the domains at all communicated in the same model, Synplify DSP would not try to synchronize the logic (as it assumed they were synchronously related). Seperate models could also be put thru Synplify DSP seperately, and hooked up in Synplify Pro with RTL created outside of Simulink/SynplifyDSP. If you know of any common or good ways to model asynchronous systems in Simulink, please let me know. We'd love to infer that from the Simulink model during Synplify DSP synthesis. Thanks AndrewArticle: 83129
I agree, and eventually I will be doing just that on my old Spartan II. However, right now im just looking for some quick estimates from anyone that's already done these implementations. If no one responds I guess I will have to spend a week or so implementing all those. But thanks for the reponse. -AKiriwasArticle: 83130
Hi,
I wonder why this results in undefined values for some time:
----------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity trigger_level is
Port ( clk : in std_logic;
prescale : in std_logic;
din : in std_logic_vector(7 downto 0);
level : in std_logic_vector(7 downto 0);
rf : in std_logic;
hold : in std_logic;
trig : out std_logic);
end trigger_level;
architecture Behavioral of trigger_level is
type samples_buffer is array(9 downto 0) of
std_logic_vector(7 downto 0);
signal samples : samples_buffer;
begin
process(clk)
begin
if rising_edge(clk) and prescale = '1' and hold = '0' then
-- no reset circuit (not needed) for reducing the number of
slices to 1 instead of 5
for i in 9 downto 1 loop
samples(i) <= samples(i-1);
end loop;
samples(0) <= din;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if (rf = '1') then --- falling edge
if (samples(0) < level and samples(9) > level) then
trig <= '1';
else
trig <= '0';
end if;
elsif (rf = '0') then --- rising edge
if (samples(0) > level and samples(9) < level) then
trig <= '1';
else
trig <= '0';
end if;
else
trig <= '0';
end if;
end if;
end process;
end Behavioral;
----------------------------------
The design should be a trigger for an oscilloscope, and I think I have
an error in my design here! The trouble is that I get triggers where I
shouldn't! (or my presampler probably doesn't work, but I think this
simulation told me where the error was!)
The simulation "error" is viewable on my website:
http://www.interrupt.dk/sim.jpg
The trigger is a level/edge trigger that should activate on rising and
falling edges!
And like allways: Thanks for helping
Preben Holm
Article: 83131Hi, I am using a KS0066UP LCD Controller, which requires some delays in the ms area. However my FPGA runs at 100 MHz. Therefore I am using a DCM to generate a 8 MHz clock and a clk_div vhdl makro do generate a 250 KHz clock out of that. This 250 KHz clock goes into my LCD_CNTL module. My Problem is, that modelsim does only 1 ms per Minute (when I set clk period to 20 ns), so simulating everything is not possible. Are there any tricks? regards, BenjaminArticle: 83132
John wrote: > Hi, > > I am write and read from a text file using vhdl. I am using quartus > 4.0 to compile and simulate. when I compile the code below, it said > that the writeline, write functions are not synthesis, which is > correct. Then when I simulate using simulator tools, it does not work, > and nothing get written to the "test_1.txt". > > Did anyone try to do this in Quartus before? and what is the problems > in my code? Quartus has absolutely nothing to do with this. Do not try to synthesize a test bench, since it would mean you want your FPGA to write into a file ;-) You must use a VHDL simulator like ModelSim (AE or other) for this to work. To make it simple : Quartus is for synthesis, ModelSim is for simulation. Otherwise, the code has the principle of text io, so it should _almost_ work. I'm suspicious here because you didn't say the simulator rejected your code, which it should have, since "a" is ambiguous ! I suspect you didn't simulate, opr compile, or instanciate test_1_wrrd, or s is not '1' while a changes, etc... etc.... In case of doubt, load your test bench, make sure you can get into the test_1_wrrd instance, and place a breakpoint. Oh, about ambiguity : try Ht & "a" instead :-) And if you wanted to record the value of the a input, then you should have written write (l,a); .... but that wouldn't have worked either since you missed : use ieee.std_logic_textio.all; Keep faith... Bert Cuzeau > > Thank you in advance for ur time and effort, > John. > > > Library IEEE; > use ieee.std_logic_1164.all; > > use std.textio.all; > > entity test_1_wrrd is > > generic( > Input_File : string := "test_1.txt" > ); > > port ( a : in std_logic; > -- clk : in std_logic; > b : out std_logic; > s : in std_logic > ); > > end entity test_1_wrrd; > > architecture beh of test_1_wrrd is > > begin > > Process(a, s) > > file p_file : text open write_mode is Input_File ; > Variable l : Line; > > > Begin > > > if s = '1' then > > b <= '1'; > > > Write ( l, "a"); > Writeline ( p_file, l ); > > > > else > > b <= '0'; > > end if; > > > > End Process; > End beh;Article: 83133
Benjamin Menküc wrote: > Hi, > > I am using a KS0066UP LCD Controller, which requires some delays in the > ms area. However my FPGA runs at 100 MHz. Therefore I am using a DCM to > generate a 8 MHz clock and a clk_div vhdl makro do generate a 250 KHz > clock out of that. This 250 KHz clock goes into my LCD_CNTL module. > > My Problem is, that modelsim does only 1 ms per Minute (when I set clk > period to 20 ns), so simulating everything is not possible. Are there > any tricks? > > regards, > Benjamin Why don't you get my free LCD controller and take a look ? http://www.alse-fr.com/English/ips.htmlArticle: 83134
Hi Info, I am using it already. However displaying a character doesnt work, I can only reset the display. Whats are the clk und the tick input for? Should both be clocked at 250 KHz? I have removed the tick thing, now I just have a 250khz_clk on clk. regards, BenjaminArticle: 83135
Thanks. I also posted this question elsewhere and got some good info. I now have a rough idea.Article: 83136
A new product from Digiliant...
All i can say is oooo!
* Virtex-2 Pro XC2VP30 FPGA with 30,816 Logic Cells, 136 18-bit
multipliers, 2,448Kb of block RAM, and two PowerPC Processors
* DDR SDRAM DIMM that can accept up to 2Gbytes of RAM
* 10/100 Ethernet port
* USB2 port
* Compact Flash card slot
* XSGA Video port
* Audio Codec
* SATA, and PS/2, RS-232 ports
* High and Low Speed expansion connectors with a large collection
of available expansion boards
http://www.digilentinc.com/info/XUPV2P.cfm
300$ student price.... Now if i can convince them to give that price out
to us lowly hobbiests too...
Article: 83137Hi, indeed very nice and I am even a student :o regards, BenjaminArticle: 83138
Benjamin Menküc wrote:
> Hi Info,
>
> I am using it already. However displaying a character doesnt work, I can
> only reset the display.
>
> Whats are the clk und the tick input for?
> Should both be clocked at 250 KHz?
>
> I have removed the tick thing, now I just have a 250khz_clk on clk.
>
> regards,
> Benjamin
I thought it was clear in the IP :
-- ------------------------------
Entity LCD_DRV is
-- ------------------------------
port( Clk : in std_logic; -- System Clock
Rst : in std_logic; -- asynchronous Reset, active high
Tick : in std_logic; -- Tick at 250 kHz (one clock cycle long)
It is a synchronous design, with only one clock domain.
* Clk is your one and only global Clock, any Frequency (above 1 Mhz) is fine.
* Tick is a one clock cycle long pulse repeated every 4 microseconds.
A simple clock division does it.
Since you have all the commented code, you shouldn't have any
trouble understanding how it works if you're curious.
Just feed the inputs with what is needed, but don't change
any line in the code unless you fully understand how it works.
Below a test bench which should help you understand how it works.
(I didn't verify that it was up-to-date with the version you have, but
it should be pretty obvious to run this simulation)
-- tb_lcd.vhd
-- -----------------------------------
-- VHDL test bench for lcd_drv
-- -----------------------------------
-- (c) Bertrand Cuzeau
-- http://www.alse-fr.com
-- very simple simulation (no fancy command sent
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
entity TB_LCD is
end;
Architecture TEST of TB_LCD is
signal Clk : STD_LOGIC := '0';
signal Tick : STD_LOGIC := '0';
signal Dav : STD_LOGIC;
signal Din : STD_LOGIC_VECTOR (7 downto 0);
signal Rst : STD_LOGIC;
signal Dout : STD_LOGIC_VECTOR (7 downto 0);
signal Busy : STD_LOGIC;
signal Lcd_En : STD_LOGIC;
signal Lcd_Rw : STD_LOGIC;
signal Lcd_Sel : STD_LOGIC;
-- 10 MHz clock for simulation
constant Period : time := 100 ns;
-- 10 times faster than reality to speed up simulation
constant TickPeriod : time := 400 ns;
begin
process begin
Tick <= '0';
wait for TickPeriod-Period;
Tick <= '1';
wait for Period;
end process;
Clk <= not Clk after (Period / 2);
Rst <= '1', '0' after Period;
UUT : entity work.LCD_DRV
Port Map ( Busy=>Busy, Clk=>Clk, Dav=>Dav, Din=>Din,
Dout=>Dout, Lcd_En=>Lcd_En, Lcd_Rw=>Lcd_Rw,
Lcd_Sel=>Lcd_Sel, Rst=>Rst, Tick=>Tick );
process
variable Data : std_logic_vector (7 downto 0) := x"5A";
begin
Din <= (others=>'0');
Dav <= '0';
wait for 10 * Period;
wait until Busy ='0';
for i in 1 to 3 loop
Din <= Data;
Data := std_logic_vector (unsigned(Data) + 1);
Dav <= '1'; wait for Period; Dav <= '0';
wait for TickPeriod;
if Busy='1' then wait until Busy='0'; end if;
end loop;
report "End of Simulation." severity failure;
wait;
end process;
end TEST;
Article: 83139Hi guys, hope you can help! I'm trying to create Space Invaders using video ROMs. I'm creating a hardware schematic to be used on the XESS XS40 development board that contains an embedded 8031 microcontroller and a Xilinx 4010 series deivce. Im downloading it onto that board and running it using a C program. If anyone can provide any tips/hints or web resources on schmatic design or operation it will be greatly appreicated. RegardsArticle: 83140
ZioPino wrote: > Duane Clark ha scritto: > > >>They will need to share the same physical clock, so you need to modify >>it in the core. If you don't, you will get error messages, I think >>during place and route. > > > Hi Duane, > thank you very much again for all the infos, you've been very kind, and > now I understood how I can proceed! I'll start to prepare the design > and as soon I'll be back in the lab I'll try it on the board, and let > you know if it all works. > Ehh... what the heck. I can't post the files directly, since the originals are copyrighted by Xilinx. But if you know how to use diff files, then here it is: http://www.leewardfpga.com/fpga/plb_dimm.diff You are free to use that in any way you want, without restriction. But of course, use at your own risk! Note that this design has one extra thing. The DIMM not only has a PLB interface, but it also has an external interface. The related signals are pretty easy to see, since they almost all start with EXT_ or EXT2IP_ or IP2EXT_. If you don't want to bother stripping these signals out, just tie the extra inputs to '0'. The purpose of these signals is to allow a high bandwidth interface to the DIMM without bogging down the PLB bus. I use this to allow RocketIO access (using the Aurora core) to the DIMM. Writing via the EXT interface has had lots of testing, and while writing, the PLB bus can simultaneously read/write the DIMM. Using this interface, I can fill a 1GB DIMM from the RocketIO in about 5 seconds. Verifying the entire block of acquired data with the PPC takes considerably longer ;) Reading of the EXT interface is a recent addition. It is somewhat more complicated, and has not been thoroughly tested yet. But it seems to work. I have not verified simultaneous PPC access while reading via the EXT interface.Article: 83141
Duane Clark wrote: > > Ehh... what the heck. I can't post the files directly, since the > originals are copyrighted by Xilinx. But if you know how to use diff > files, then here it is: > http://www.leewardfpga.com/fpga/plb_dimm.diff > Oh, and while at it, I included a simple testbench in the same directory. The files bd_test.vhd and bd_test_siml.vhd are separate tests that do slightly different things. You compile one or the other into the testbench. The top level testbench file is bd_top.vhd.Article: 83142
Ziggy wrote: > A new product from Digiliant... > > All i can say is oooo! > > > > * Virtex-2 Pro XC2VP30 FPGA with 30,816 Logic Cells, 136 18-bit > multipliers, 2,448Kb of block RAM, and two PowerPC Processors > * DDR SDRAM DIMM that can accept up to 2Gbytes of RAM > * 10/100 Ethernet port > * USB2 port > * Compact Flash card slot > * XSGA Video port > * Audio Codec > * SATA, and PS/2, RS-232 ports > * High and Low Speed expansion connectors with a large collection of > available expansion boards > > > http://www.digilentinc.com/info/XUPV2P.cfm > > 300$ student price.... Now if i can convince them to give that price out > to us lowly hobbiests too... Good luck :-) A quick glance at the NuHorizons website shows they're selling just the FPGA for $619 (Quantity 1 price), or $487 (quantity 100+ price). If you do manage it, let me know! At *last* a development board with a DIMM socket on it. Oh frabjous day. Callooh! Callay! He chortled in his joy :-)) Why it's such a rare item is beyond me - it takes 123 signals to put a generic 184-pin DIMM socket on-board... With the BGA parts having upwards of 300 (566 in this case) signals available, and RAM being so ridiculously cheap (in DIMMs!), and with the EDK becoming more popular you'd have thought a DIMM socket would be commonplace... Horses for courses I suppose :-( ATB, Simon.Article: 83143
Hi, I'm using the ML 401 development board configured with the "reference design" provided by Xilinx. I need to download a rather large c++ program but unfortunately it cannot fit into the bram of the design. I know that I should place the program data in the 64 mb external memory. Is there an "easy" way to do this? thanksArticle: 83144
*snip* > > Why it's such a rare item is beyond me - it takes 123 signals to put a > generic 184-pin DIMM socket on-board... With the BGA parts having > upwards of 300 (566 in this case) signals available, and RAM being so > ridiculously cheap (in DIMMs!), and with the EDK becoming more popular > you'd have thought a DIMM socket would be commonplace... Horses for > courses I suppose :-( > > ATB, > Simon. While not a full size DIMM, http://www.cmosexod.com/fnd.htm supports a laptop sized DIMM..Article: 83145
Austin Lesea wrote: > See the subject line. > > And, I have been posting, just not on your last thread, as I had nothing > more to say. > > Austin I did not expect to see any more posts from Xilinx after your last comments: "Abuse is not going to make me likely to post further. As of this moment, the case is closed. We have done what we can with what you are willing to do (look under the streetlamp)."Article: 83146
Johnsons. Joe wrote: > Hello > > I am using a Virtex2Pro board and lately I was trying to use the PowerPC at > the highest speed (300MHz) on my board. I have a function which uses a lot > of floating point instructions for calculating the log, sine, cosine and > such stuff. When I ran this program on the PowerPC it took almost 2 minutes > to perform 1000 iterations at 100MHz. Then we wanted the code to run a > little more faster and so we implemented the same design at 300MHz. Even if > we didn't expect a three fold increase in speed, there was only an > improvement of a couple of seconds. Can somebody tell me the reason. > > Well about the memory that I was using, I used a OCM interface with 32kB for > Instruction and 8kB for data. Cache memory was given to the PLB RAM(16kB). > There was infact no speed difference with and without the cache memories !! > Can somebody please help. > > When I selected 300MHz for the processor, the maximum bus freq that I could > select was only 100MHz. But this is only for the PLB or is it also for the > OCM interface. (I always uses the wizard to build a new system, as I am > quite new to tis stuff) > > Thank you very much > Joey > > Hi, If you executing from OCM then you would not see the speed up since OCM accesses is BEFORE the caches. If you have high cache rates, place the memory on PLB instead since this would make PPC to execute from the caches which scales with the CPU frequency. GöranArticle: 83147
Ziggy, For this board, can buyer specify a Spartan 3 1000K FPGA? On this page, it mentioned the board can accomodate three types of FPGA, http://www.digilentinc.com/Products/Programmable.cfm but on the actual page, this information is missing. http://www.digilentinc.com/info/S3Board.cfm Thank you for your attention. "Ziggy" <Ziggy@TheCentre.com> wrote in message news:ReUae.17355$NU4.6274@attbi_s22... > A new product from Digiliant... > > All i can say is oooo! > > > > * Virtex-2 Pro XC2VP30 FPGA with 30,816 Logic Cells, 136 18-bit > multipliers, 2,448Kb of block RAM, and two PowerPC Processors > * DDR SDRAM DIMM that can accept up to 2Gbytes of RAM > * 10/100 Ethernet port > * USB2 port > * Compact Flash card slot > * XSGA Video port > * Audio Codec > * SATA, and PS/2, RS-232 ports > * High and Low Speed expansion connectors with a large collection > of available expansion boards > > > http://www.digilentinc.com/info/XUPV2P.cfm > > 300$ student price.... Now if i can convince them to give that price out > to us lowly hobbiests too...Article: 83148
Here you go, some wild guesses, assuming mostly parallel
implementations.
On 23 Apr 2005 22:36:32 -0700, akiriwas@gmail.com wrote:
>Hi Group,
>
> I am looking for some rough estimate kind of numbers. The numbers
>don't really need to be precise, just guesses and estimates.
>
> Okay, here's what I need. What would the relative number of CLBs
>needed be for the following types of synthesized circuits (assuming the
>FPGA they were implemented on did NOT have any special components that
>would lessen the number of CLBs needed)
>
>1. 32 bit integer adder
1 single cycle
>2. 32 bit integer multiplier
32 single cycle or pipelined
>3. 32 bit integer divider
25 32 cycle sequential
>4. Double precision floating point adder (I know this one is
>expensive)
40 single cycle or pipelined
>5. Double precision floating point multiplier
200 single cycle or pipelined
>6. Double precision floating point divider
200 multi cycle (64?) sequential
>7. Double precision floating point square root
210 multi cycle (64?) sequential
>I know there are different algorithms for some of these operations,
>some are parallel some are serial, just whichever you know would help.
>Rough guesses are all I need. If you want, just take whichever would
>be the lease, use that as a baseline of 1.0 for the relative sizes.
>Thanks everyone.
>
>-AKiriwas
I bet some of these are off by 50%
Philip
Philip Freidin
Fliptronics
Article: 83149Preben Holm <64bitNOnoNOSPAM@mailme.dk> wrote: > I wonder why this results in undefined values for some time: The simulation shows that your getting unknown values, not uninitialised The code seems Ok for me. A simulation of the code itself should show no error. > The design should be a trigger for an oscilloscope, and I think I have > an error in my design here! The trouble is that I get triggers where I > shouldn't! (or my presampler probably doesn't work, but I think this > simulation told me where the error was!) > > The simulation "error" is viewable on my website: > http://www.interrupt.dk/sim.jpg The simulation shows a timing violation. It is likely that the timing violation leads to an X. You should check the timing of your design, maybe you didnt reach the used clock frequency or you have trouble with asynchronous inputs. bye Thomas
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