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Messages from 82275

Article: 82275
Subject: Re: Reverse engineering masked ROMs, PLAs
From: Robert Baer <robertbaer@earthlink.net>
Date: Sun, 10 Apr 2005 09:14:23 GMT
Links: << >>  << T >>  << A >>
Eric Smith wrote:

> I wrote:
> 
>>Before everyone jumps on me about piracy, I'll explain that the ROM
>>and PLA code in question is NOT copyrighted.
> 
> 
> Robert Baer wrote:
> 
>>...and, pray tell, how do you get to that conclusion?
> 
> 
> By knowing some of the details of US Copyright Law (Title 17 of the
> United States Code).
> 
> 
>>   Every time one generates a document or a pattern (in this case the
>>codes, masks, etc), such items *by FEDERAL law* are copyrighted!
> 
> 
> In the US, that wasn't the case before the Berne Copyright Convention took
> effect, March 1, 1989.  See 17 U.S.C. 405(a):
> 
>    Sec. 405. Notice of copyright: Omission of notice on certain copies
>    and phonorecords
> 
>    (a) Effect of Omission Copyright on With respect to copies and
>    phonorecords publicly distributed by authority of the copyright owner
>    before the effective date of the Berne Convention Implementation Act
>    of 1988, the omission of the copyright notice described in sections
>    401 through 403 from copies or phonorecords publicly distributed by
>    authority of the copyright owner does not invalidate the copyright in
>    a if work
> 
>     * (1) the notice has been omitted from no more than a relatively
>           small number of copies or phonorecords distributed to the
>           public; or
> 
>     * (2) registration for the work has been made before or is made
>           within five years after the publication without notice, and a
>           reasonable effort is made to add notice to all copies or
>           phonorecords that are distributed to the public in the United
>           States after the omission has been discovered; or
> 
>     * (3) the notice has been omitted in violation of an express
>           requirement in writing that, as a condition of the copyright
>           owner's authorization of the public distribution of copies or
>           phonorecords, they bear the prescribed notice. 
> 
> In the case of the ROMs and PLAs I want to extract, none of the
> conditions for preservation of a copyright without notice have been
> met.
> 
> Also, these parts were sold before the Semiconductor Chip Protection Act
> of 1984 (17 USC 901 et seq.) was enacted, so they are not elgible for
> protection as mask works.
> 
> 
>>   In fact, your missive to this NG, and my answer here is copyrighted!
> 
> 
> True, because the Berne Convention is in effect.  I'm including quotes
> from your message here as a matter of fair use.
> 
> 
>>   Now, if anyone wanted to make some lawyers rich and go to court
>>over mis-use of copyrighted material, then copyright *registration*
>>would be considered as the ultimate proof that judges cannot go
>>against.
> 
> 
> Technically registration is still a legal requirement, even though
> a copyright notice is not.
> 
> However, the main practical effect of registration is that it allows you
> to collect actual damages for infringement.  Without registration, you
> can only collect statutory damages, though they can be fairly substantial.
> 
> Eric
   The Semiconductor Chip Protection Act is not relevant; the masks 
could be covered as works of art.
   As far as age goes, you are correct - if an item is old enough, then 
notice would be needed.
   Without registration, collection of statutory damages would be rather 
difficult as one would have to prove ownership and priority.
   Registration is equivalent to "overkill" proof.

Article: 82276
Subject: Re: A PCI FPGA card I found on ebay
From: "randomdude@gmail.com" <randomdude@gmail.com>
Date: 10 Apr 2005 03:47:03 -0700
Links: << >>  << T >>  << A >>
Ah, fair enough. Ta for the tips, and the link.. I've been looking for
a cheap (decent) PCI fpga board for a while now, I hadn't found
anything that cheap before. :) Thanks :)


Article: 82277
Subject: Re: A PCI FPGA card I found on ebay
From: "Antti Lukats" <antti@openchip.org>
Date: Sun, 10 Apr 2005 13:03:39 +0200
Links: << >>  << T >>  << A >>

<randomdude@gmail.com> schrieb im Newsbeitrag
news:1113130023.925340.152230@o13g2000cwo.googlegroups.com...
> Ah, fair enough. Ta for the tips, and the link.. I've been looking for
> a cheap (decent) PCI fpga board for a while now, I hadn't found
> anything that cheap before. :) Thanks :)
>

there are hardly any other PCI-FPGA boards in that price range

http://www.fpga4fun.com/board_dragon.html
but that board costs $249/$299 what is way too much for that board
and
Memec still has low cost PCI boards but those are 'phasing out' from the
offering

both of those are based on S2 what is also old FPGA

Avnet has nice S3-PCI boards but they are a bit more expensive

so for the $150 you get MAX2 what very latest of family,
you get PCI, FT245, SRAM and LCD
so its really a nice package

I have special project page for MAX2 starterkit support

http://gforge.openchip.org/projects/maxkitutils/

it isnt much there at the moment, only example
how to wire connect the FT245 so the starterkit can be used as plain FT245
test board
and simple USB-JTAG interface compatible NUSB (nahitafu USB) specs

I also have partially working clone of Altera USB Blaster, but that isnt
finished
(eg not working properly)

Antti














Article: 82278
Subject: clk_div illigal connection
From: =?ISO-8859-15?Q?Benjamin_Menk=FCc?= <benjamin@menkuec.de>
Date: Sun, 10 Apr 2005 14:16:25 +0200
Links: << >>  << T >>  << A >>
Hi,

this is my code

	dcm1_1 : dcm1 port map (
		CLKIN_IN => CLK,
		RST_IN => RESET,
		CLKFX_OUT => clk_20M,
		CLKIN_IBUFG_OUT => open,
		CLK0_OUT => clk_int,
		LOCKED_OUT => locked);

	clk_div_1 : clk_div_262k
		port map (
			CLK => CLK_20M,
			DIV_262144 => clk_led2);

I get this error there during synthesis:
ERROR:Xst:2035 - Port <clk> has illegal connection. Port is connected to 
input buffer and following ports:
    Port C of instance cnt1_1/BU20 in unit cnt1_1 with type FDE

I have no idea where the problem is.

Is it generally a good idea to use the dcm and a clk_divider if a very 
slow frequency is needed? Or should I use only clk_dividers?

regards,
Benjamin

Article: 82279
Subject: Re: Neural Networks in FPGA
From: "Symon" <symon_brewer@hotmail.com>
Date: Sun, 10 Apr 2005 07:52:33 -0700
Links: << >>  << T >>  << A >>
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message 
news:iudh5191obt8jj1g9rd44j8h4e1kd8jq3a@4ax.com...
> On Sat, 9 Apr 2005 18:17:18 -0700, "Symon" <symon_brewer@hotmail.com>
> wrote:
>
>>No, no-one has. That's why when you put 'neural nets fpga' into Google, 
>>you
>>get no hits whatsoever. Apart from the first 10000, that is.
>>Syms.
>
>
> More importantly, has anybody found a use for neural nets?
>
> John
>
>
I use mine daily.... 



Article: 82280
Subject: Question about Xilinx OPB/PCI bridge
From: "Riz" <RizwanRasheed205@gmail.com>
Date: 10 Apr 2005 08:02:36 -0700
Links: << >>  << T >>  << A >>
Hi,

I am new using Xilinx EDK. The version I'm using is 6.3.

I'd like to access OPB bus from PCI side. I'm Xilinx OPB/PCI bridge v3
in a project where I'm using custom board. Linux and Windows are able
to recognize the PCI bridge and does allocate resources but unable to
access to the device on the OPB bus.

Please have a look at my mhs file, and advise me if I have done
something wrong!

Thank you in advance.
Riz/

Here is my mhs file;
-------------------

PARAMETER VERSION = 2.1.0

PORT sys_rst = sys_rst, DIR = IN
PORT clk_40mhz = clk_40mhz, DIR = I, SIGIS = CLK
PORT SDRAM_WEn = opb_sdram_0_SDRAM_WEn, DIR = OUT
PORT SDRAM_RASn = opb_sdram_0_SDRAM_RASn, DIR = OUT
PORT SDRAM_DQM = opb_sdram_0_SDRAM_DQM, VEC = [0:3], DIR = OUT
PORT SDRAM_DQ = opb_sdram_0_SDRAM_DQ, VEC = [0:31], DIR = INOUT
PORT SDRAM_Clk = opb_sdram_0_SDRAM_Clk, DIR = OUT, SIGIS = CLK
PORT SDRAM_CSn = opb_sdram_0_SDRAM_CSn, DIR = OUT
PORT SDRAM_CKE = opb_sdram_0_SDRAM_CKE, DIR = OUT
PORT SDRAM_CASn = opb_sdram_0_SDRAM_CASn, DIR = OUT
PORT SDRAM_BankAddr = opb_sdram_0_SDRAM_BankAddr, VEC = [0:1], DIR =
OUT
PORT SDRAM_Addr = opb_sdram_0_SDRAM_Addr, VEC = [0:11], DIR = OUT
PORT RS232_RX = RS232_RX, DIR = I
PORT RS232_TX = RS232_TX, DIR = O
PORT TRDY_N = TRDY_N, DIR = INOUT
PORT CBE = CBE, VEC = [3:0], DIR = INOUT
PORT DEVSEL_N = DEVSEL_N, DIR = INOUT
PORT FRAME_N = FRAME_N, DIR = INOUT
PORT AD = AD, VEC = [31:0 ], DIR = INOUT
PORT SERR_N = SERR_N, DIR = INOUT
PORT INTR_A = INTR_A, DIR = OUT
PORT IRDY_N = IRDY_N, DIR = INOUT
PORT PAR = PAR, DIR = INOUT
PORT GNT_N = GNT_N, DIR = IN
PORT STOP_N = STOP_N, DIR = INOUT
PORT RST_N = RST_N, DIR = IN
PORT REQ_N = REQ_N, DIR = OUT
PORT PERR_N = PERR_N, DIR = INOUT
PORT PCLK = PCLK, DIR = IN, SIGIS = CLK
PORT IDSEL = IDSEL, DIR = IN

BEGIN microblaze
PARAMETER INSTANCE = mblaze
PARAMETER HW_VER = 3.00.a
BUS_INTERFACE DLMB = d_lmb
BUS_INTERFACE ILMB = i_lmb
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb
PORT CLK = clk_40mhz
PORT INTERRUPT = net_gnd
END

BEGIN lmb_v10
PARAMETER INSTANCE = i_lmb
PARAMETER HW_VER = 1.00.a
PORT SYS_Rst = sys_rst
PORT LMB_Clk = clk_40mhz
END

BEGIN lmb_v10
PARAMETER INSTANCE = d_lmb
PARAMETER HW_VER = 1.00.a
PORT SYS_Rst = sys_rst
PORT LMB_Clk = clk_40mhz
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = i_bram_cntrl
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00007fff
BUS_INTERFACE SLMB = i_lmb
BUS_INTERFACE BRAM_PORT = ilmb_port
PORT LMB_Clk = clk_40mhz
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = d_bram_cntrl
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00007fff
BUS_INTERFACE SLMB = d_lmb
BUS_INTERFACE BRAM_PORT = dlmb_port
PORT LMB_Clk = clk_40mhz
END

BEGIN bram_block
PARAMETER INSTANCE = bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTB = dlmb_port
BUS_INTERFACE PORTA = ilmb_port
END

BEGIN opb_pci
PARAMETER INSTANCE = pci
PARAMETER HW_VER = 1.00.c
BUS_INTERFACE MSOPB = mb_opb
PARAMETER C_PCI_ABUS_WIDTH = 32
PARAMETER C_PCI_DBUS_WIDTH = 32
PARAMETER C_DEVICE_ID = 0x0300
PARAMETER C_VENDOR_ID = 0x10ee
PARAMETER C_REV_ID = 0x00
PARAMETER C_CLASS_CODE = 0x0b4000
PARAMETER C_BASEADDR = 0x08bb9000
PARAMETER C_HIGHADDR = 0x08bb9fff
PARAMETER C_INCLUDE_PCI_CONFIG = 0
PARAMETER C_IPIFBAR_NUM = 2
PARAMETER C_IPIFBAR_0 = 0x08d90000
PARAMETER C_IPIF_HIGHADDR_0 = 0x08d9ffff
PARAMETER C_IPIFBAR2PCI_0 = 0x0
PARAMETER C_IPIFBAR_1 = 0x08990000
PARAMETER C_IPIF_HIGHADDR_1 = 0x0899ffff
PARAMETER C_IPIFBAR2PCI_1 = 0x0
PARAMETER C_PCIBAR_NUM = 1
PARAMETER C_PCIBAR_0 = 0xff600000
PARAMETER C_PCIBAR2IPIF_0 = 0x08000000
PARAMETER C_PCIBAR_LEN_0 = 23
PARAMETER C_PCI_PREFETCH_0 = 1
PARAMETER C_PCI_SPACETYPE_0 = 1
PARAMETER C_PCIBAR_ENDIAN_TRANSLATE_EN_0 = 1
PORT TRDY_N = TRDY_N
PORT CBE = CBE
PORT DEVSEL_N = DEVSEL_N
PORT FRAME_N = FRAME_N
PORT AD = AD
PORT SERR_N = SERR_N
PORT INTR_A = INTR_A
PORT IRDY_N = IRDY_N
PORT PAR = PAR
PORT GNT_N = GNT_N
PORT STOP_N = STOP_N
PORT RST_N = RST_N
PORT REQ_N = REQ_N
PORT PERR_N = PERR_N
PORT PCLK = PCLK
PORT OPB_Clk = clk_40mhz
PORT IDSEL = IDSEL
END

BEGIN opb_uartlite
PARAMETER INSTANCE = uart
PARAMETER HW_VER = 1.00.b
PARAMETER C_DATA_BITS = 8
PARAMETER C_CLK_FREQ = 40000000
PARAMETER C_BAUDRATE = 9600
PARAMETER C_USE_PARITY = 0
PARAMETER C_ODD_PARITY = 0
PARAMETER C_BASEADDR = 0x08e38000
PARAMETER C_HIGHADDR = 0x08e380ff
BUS_INTERFACE SOPB = mb_opb
PORT RX = RS232_RX
PORT TX = RS232_TX
PORT OPB_Clk = clk_40mhz
PORT Interrupt = net_gnd
END

BEGIN opb_sdram
PARAMETER INSTANCE = opb_sdram_0
PARAMETER HW_VER = 1.00.e
PARAMETER C_SDRAM_TRAS = 60000
PARAMETER C_SDRAM_TRC = 90000
PARAMETER C_SDRAM_TRFC = 85000
PARAMETER C_SDRAM_TRRD = 25000
PARAMETER C_SDRAM_DWIDTH = 32
PARAMETER C_SDRAM_AWIDTH = 12
PARAMETER C_SDRAM_COL_AWIDTH = 9
PARAMETER C_SDRAM_BANK_AWIDTH = 2
PARAMETER C_OPB_CLK_PERIOD_PS = 19240
PARAMETER C_BASEADDR = 0x08000000
PARAMETER C_HIGHADDR = 0x087fffff
BUS_INTERFACE SOPB = mb_opb
PORT SDRAM_Addr = opb_sdram_0_SDRAM_Addr
PORT SDRAM_RASn = opb_sdram_0_SDRAM_RASn
PORT SDRAM_Clk = opb_sdram_0_SDRAM_Clk
PORT SDRAM_Clk_in = clk_40mhz
PORT SDRAM_CKE = opb_sdram_0_SDRAM_CKE
PORT SDRAM_CSn = opb_sdram_0_SDRAM_CSn
PORT SDRAM_CASn = opb_sdram_0_SDRAM_CASn
PORT SDRAM_WEn = opb_sdram_0_SDRAM_WEn
PORT SDRAM_DQM = opb_sdram_0_SDRAM_DQM
PORT SDRAM_BankAddr = opb_sdram_0_SDRAM_BankAddr
PORT SDRAM_DQ = opb_sdram_0_SDRAM_DQ
PORT OPB_Clk = clk_40mhz
END

BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_BASEADDR = 0xfffffe00
PARAMETER C_HIGHADDR = 0xffffffff
PARAMETER C_REG_GRANTS = 0
PARAMETER C_PROC_INTRFCE = 1
PORT OPB_Clk = clk_40mhz
PORT SYS_Rst = sys_rst
END

BEGIN opb_bram_if_cntlr
PARAMETER INSTANCE = opb_bram_if_cntlr_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x08b10000
PARAMETER C_HIGHADDR = 0x08b11fff
BUS_INTERFACE SOPB = mb_opb
BUS_INTERFACE PORTA = bram_block_0_port
PORT OPB_CLK = clk_40mHz
END

BEGIN bram_block
PARAMETER INSTANCE = bram_block_0
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = bram_block_0_port
END


Article: 82281
Subject: Re: clk_div illigal connection
From: austin <austin@xilinx.com>
Date: Sun, 10 Apr 2005 08:36:20 -0700
Links: << >>  << T >>  << A >>
Benjamin,

If you wish to use the CLKDV output, that uses the DLL part of the DCM, 
and it requires CLK0 to CLKFB (for phase alignment feedback -- required 
by using any of the CLK0, 90, 189, 270, 2X, or DV outputs), and a CLKIN 
less than 24 MHz.

Since you are also using the CLKFX output at the same time, the M and D 
values have to be such that with the CLKIN (which must be greater than 
24 MHz since you used the CLKDV output), places the CLKFX output 
frequency in an allowed range for either low, or high frequency modes.

If you have clock less than 24 MHz, and want a 20 MHz clock out, you 
can't do that (even if you don't use CLKDV):  20 MHz is too slow an 
output for the DFS part of the DCM (output must be greater than 24 MHz). 
  I would instead go to a higher freqeuncy (in range), and divide it 
down externally in the fabric.  There will be timing skews, etc. (since 
you can't use the DCM for division, and are uising local routing for 
clock signals) but at least you can make it work that way.

Austin

Article: 82282
Subject: vhdl and clock-pin
From: =?ISO-8859-15?Q?Benjamin_Menk=FCc?= <benjamin@menkuec.de>
Date: Sun, 10 Apr 2005 17:36:54 +0200
Links: << >>  << T >>  << A >>
Hi,

when I use a CLK input-pin in vhdl in my top-level file, is this 
automatically the clk signal of my device? Or do I have to constrain it 
to the correct PIN?

regards,
Benjamin

Article: 82283
Subject: Re: ISE 7.1 for 64 bit Linux ???
From: "Jim Wu" <nospam@nospam.com>
Date: Sun, 10 Apr 2005 11:46:26 -0400
Links: << >>  << T >>  << A >>

"mk" <kal*@dspia.*comdelete> wrote in message
news:6cuf51t2hdkg81fnpahjoqms4lihatpd43@4ax.com...
> On Sat, 9 Apr 2005 11:18:30 -0400, "Jim Wu" <nospam@nospam.com> wrote:
>
> >FWIW, I didn't have a problem installing it on a Dell machine w/ 2 AMD
> >Opteron 64-bit running RH Enterprise 3.
>
> I think you're confused. Are you sure it's a Dell machine with AMD
> Opterons ? Or do you mean a Dell machine with two cpus supporting
> AMD64 extensions from Intel ?

Sorry my mistake. It's been a while since I got the machine. It's a Sun Fire
V20Z machine.

Jim



Article: 82284
Subject: Re: vhdl and clock-pin
From: =?ISO-8859-15?Q?Benjamin_Menk=FCc?= <benjamin@menkuec.de>
Date: Sun, 10 Apr 2005 17:58:00 +0200
Links: << >>  << T >>  << A >>
Hi,

I figured out that I have to do it. It works now. Thanks anyway :)

regards,
Benjamin

Article: 82285
Subject: Re: Neural Networks in FPGA
From: "JJ" <johnjakson@yahoo.com>
Date: 10 Apr 2005 09:11:02 -0700
Links: << >>  << T >>  << A >>
Tryin to avoid some gardening work I had to check that out.

I only see upto p76 so 760 of 9880 refs.

Even after turning off a redundancy warning it goes to 980 out of 11600
so I guess the other 9-10k can't be reached or can they?

Is it possible to random access out there in the 9880 boonies, I don't
usually go further than 1st few pages. And google says it won't go past
1000. Hint directly type in over "num=300" to jump but 1000 gate still
there.

Anyway to save the whole thing to file in 1 go?
(after change settings to 100 items per page)


johnjakson at usa dot com


Article: 82286
Subject: edk annual renewal cost?
From: "starfire" <starfire151@cableone.net>
Date: Sun, 10 Apr 2005 10:17:22 -0600
Links: << >>  << T >>  << A >>
I am fairly new to the FPGA world.  I've been using Actel parts (Axcelerator 
family) at work but I would like to migrate to the Xilinx family for the 
next generation design for an existing project.  I would like to take 
advantage of the in-cricuit reprogrammablility and the high speed parts 
(either Virtex II or Virtex 4).  I've downloaded the free WebPack from 
Xilinx and have purchased the Spartan 3 Starter kit.  I've done a little 
checking into the costs of development tools for home use for embedded 
processors.

According to the Xilinx home page advertising the EDK, the package cost is 
about $495.  This is for a one-year license.  Does this mean I would have to 
pay $495 every year I wanted to use this package?  Is this the only way to 
get support for embedded processors like Microblaze and PowerPC?  Are there 
any alternatives (less expensive) for home use?  I would like to develop 
code for FPGAs (fairly high speed devices... > 300MHz) at home then employ 
the designs at work (where a separate license with annual renewal) would be 
established.

Is the EDK to only way to get generation support for Macro models?

Is there a better route to development that anyone could suggest?

Thanks.

Dave



Article: 82287
Subject: Re: edk annual renewal cost?
From: "Antti Lukats" <antti@openchip.org>
Date: Sun, 10 Apr 2005 18:21:21 +0200
Links: << >>  << T >>  << A >>
"starfire" <starfire151@cableone.net> schrieb im Newsbeitrag
news:115ikci5cm72pe8@corp.supernews.com...
> I am fairly new to the FPGA world.  I've been using Actel parts
(Axcelerator
> family) at work but I would like to migrate to the Xilinx family for the
> next generation design for an existing project.  I would like to take
> advantage of the in-cricuit reprogrammablility and the high speed parts
> (either Virtex II or Virtex 4).  I've downloaded the free WebPack from
> Xilinx and have purchased the Spartan 3 Starter kit.  I've done a little
> checking into the costs of development tools for home use for embedded
> processors.
>
> According to the Xilinx home page advertising the EDK, the package cost is
> about $495.  This is for a one-year license.  Does this mean I would have
to
> pay $495 every year I wanted to use this package?  Is this the only way to
> get support for embedded processors like Microblaze and PowerPC?  Are
there
> any alternatives (less expensive) for home use?  I would like to develop
> code for FPGAs (fairly high speed devices... > 300MHz) at home then employ
> the designs at work (where a separate license with annual renewal) would
be
> established.
>
> Is the EDK to only way to get generation support for Macro models?
>
> Is there a better route to development that anyone could suggest?
>
> Thanks.
>
> Dave
>

well first of all you dont have to use EDK if you are looking for
alternatives
www.gaisler.com there is free open-source GRLIB SoC and toolchain including
uclinux support for LEON3 (SPARC) softcore, thats completly free, inlcuded
free PCI
and wrapper around ethernet and can from the opencores

the LEON/GRLIB is SoC is slightly larger than small MicroBlaze based system
a very small GRLIB SoC fits into S3-400 but barely, anyway in any larger
FPGA the LEON3 SoC is an alternative

of course if at work there is EDK then you must use EDK
Antti



Article: 82288
Subject: Re: A PCI FPGA card I found on ebay
From: "randomdude@gmail.com" <randomdude@gmail.com>
Date: 10 Apr 2005 09:32:40 -0700
Links: << >>  << T >>  << A >>
Nice, thanks for the info and site :)

I have my eyes on a www.mesanet.com Anything IO card (
http://www.mesanet.com/pdf/parallel/5i20ds.pdf ) mainly because it has
a nice big FPGA on it. Its $200US. Seems a fair price to me. Has anyone
dealt with that company before?


Article: 82289
Subject: Re: implement the JTAG MASTER --ACT8990 by using FPGA
From: "Antti Lukats" <antti@openchip.org>
Date: Sun, 10 Apr 2005 18:50:00 +0200
Links: << >>  << T >>  << A >>
"strayblue" <strayblue2003@yahoo.com-dot-cn.no-spam.invalid> schrieb im
Newsbeitrag news:Y5-dncZSwMbpxMTfRVn_vg@giganews.com...
> I want to implement the JTAG MASTER --ACT8990 by using FPGA,Does who
> have do the same thing? Could someone give me a hand please?
>

heavens sake why do you want todo this ??!

the 8990 is a very old biest, why duplicate it?
just make your own JTAG master and be happy

antti



Article: 82290
Subject: Re: edk annual renewal cost?
From: Ziggy <Ziggy@TheCentre.com>
Date: Sun, 10 Apr 2005 16:54:34 GMT
Links: << >>  << T >>  << A >>
Antti Lukats wrote:
> "starfire" <starfire151@cableone.net> schrieb im Newsbeitrag
> news:115ikci5cm72pe8@corp.supernews.com...
> 
>>I am fairly new to the FPGA world.  I've been using Actel parts
> 
> (Axcelerator
> 
>>family) at work but I would like to migrate to the Xilinx family for the
>>next generation design for an existing project.  I would like to take
>>advantage of the in-cricuit reprogrammablility and the high speed parts
>>(either Virtex II or Virtex 4).  I've downloaded the free WebPack from
>>Xilinx and have purchased the Spartan 3 Starter kit.  I've done a little
>>checking into the costs of development tools for home use for embedded
>>processors.
>>
>>According to the Xilinx home page advertising the EDK, the package cost is
>>about $495.  This is for a one-year license.  Does this mean I would have
> 
> to
> 
>>pay $495 every year I wanted to use this package?  Is this the only way to
>>get support for embedded processors like Microblaze and PowerPC?  Are
> 
> there
> 
>>any alternatives (less expensive) for home use?  I would like to develop
>>code for FPGAs (fairly high speed devices... > 300MHz) at home then employ
>>the designs at work (where a separate license with annual renewal) would
> 
> be
> 
>>established.
>>
>>Is the EDK to only way to get generation support for Macro models?
>>
>>Is there a better route to development that anyone could suggest?
>>
>>Thanks.
>>
>>Dave
>>
> 
> 
> well first of all you dont have to use EDK if you are looking for
> alternatives
> www.gaisler.com there is free open-source GRLIB SoC and toolchain including
> uclinux support for LEON3 (SPARC) softcore, thats completly free, inlcuded
> free PCI
> and wrapper around ethernet and can from the opencores
> 
> the LEON/GRLIB is SoC is slightly larger than small MicroBlaze based system
> a very small GRLIB SoC fits into S3-400 but barely, anyway in any larger
> FPGA the LEON3 SoC is an alternative
> 
> of course if at work there is EDK then you must use EDK
> Antti
> 
> 

Not disagreeing with the Leon3 being really cool, but if he doesnt get 
the EDK how would one actually load the FPGA? Would there be free tools 
to do that?

I also think he wants to really do his own development as well.. Not 
just grab a pre-done core.

I know for some of us, $500/year would be steep for a hobby.. ( yes i 
realize that the hobby business isnt what supports these companies, so 
they really dont care much about us. So free tools are nice. )

Article: 82291
Subject: vhdl code for the 2-line lcd on xilinx boards
From: =?ISO-8859-15?Q?Benjamin_Menk=FCc?= <benjamin@menkuec.de>
Date: Sun, 10 Apr 2005 19:06:58 +0200
Links: << >>  << T >>  << A >>
Hi,

does anybody know where to find code for the 2-line lcd? For now I want 
to talk to the lcd without any processor (no EDK).

regards,
Benjamin

Article: 82292
Subject: Re: edk annual renewal cost?
From: "Antti Lukats" <antti@openchip.org>
Date: Sun, 10 Apr 2005 19:23:14 +0200
Links: << >>  << T >>  << A >>
"Ziggy" <Ziggy@TheCentre.com> schrieb im Newsbeitrag
news:eTc6e.3688$GJ.1717@attbi_s71...
> Antti Lukats wrote:
> > "starfire" <starfire151@cableone.net> schrieb im Newsbeitrag
> > news:115ikci5cm72pe8@corp.supernews.com...
> >
> >>I am fairly new to the FPGA world.  I've been using Actel parts
> >
> > (Axcelerator
> >
> >>family) at work but I would like to migrate to the Xilinx family for the
> >>next generation design for an existing project.  I would like to take
> >>advantage of the in-cricuit reprogrammablility and the high speed parts
> >>(either Virtex II or Virtex 4).  I've downloaded the free WebPack from
> >>Xilinx and have purchased the Spartan 3 Starter kit.  I've done a little
> >>checking into the costs of development tools for home use for embedded
> >>processors.
> >>
> >>According to the Xilinx home page advertising the EDK, the package cost
is
> >>about $495.  This is for a one-year license.  Does this mean I would
have
> >
> > to
> >
> >>pay $495 every year I wanted to use this package?  Is this the only way
to
> >>get support for embedded processors like Microblaze and PowerPC?  Are
> >
> > there
> >
> >>any alternatives (less expensive) for home use?  I would like to develop
> >>code for FPGAs (fairly high speed devices... > 300MHz) at home then
employ
> >>the designs at work (where a separate license with annual renewal) would
> >
> > be
> >
> >>established.
> >>
> >>Is the EDK to only way to get generation support for Macro models?
> >>
> >>Is there a better route to development that anyone could suggest?
> >>
> >>Thanks.
> >>
> >>Dave
> >>
> >
> >
> > well first of all you dont have to use EDK if you are looking for
> > alternatives
> > www.gaisler.com there is free open-source GRLIB SoC and toolchain
including
> > uclinux support for LEON3 (SPARC) softcore, thats completly free,
inlcuded
> > free PCI
> > and wrapper around ethernet and can from the opencores
> >
> > the LEON/GRLIB is SoC is slightly larger than small MicroBlaze based
system
> > a very small GRLIB SoC fits into S3-400 but barely, anyway in any larger
> > FPGA the LEON3 SoC is an alternative
> >
> > of course if at work there is EDK then you must use EDK
> > Antti
> >
> >
>
> Not disagreeing with the Leon3 being really cool, but if he doesnt get
> the EDK how would one actually load the FPGA? Would there be free tools
> to do that?
>
> I also think he wants to really do his own development as well.. Not
> just grab a pre-done core.
>
> I know for some of us, $500/year would be steep for a hobby.. ( yes i
> realize that the hobby business isnt what supports these companies, so
> they really dont care much about us. So free tools are nice. )

I dont get you, all you need is some FPGA S3-400 is enough
then grab GRLIB build your SoC use 5 wires to LPT port cable
to configure the then Sparc SoC already is working in the FPGA
nothing else required.

there is lots todo with GRLIB too :)

antti



Article: 82293
Subject: Re: Reverse engineering masked ROMs, PLAs
From: Pi <hoebenNOSPAM@bigfoot.com>
Date: Sun, 10 Apr 2005 17:27:59 GMT
Links: << >>  << T >>  << A >>
On 08 Apr 2005 12:53:25 -0700, Eric Smith <eric@brouhaha.com> wrote:

>Ray Andraka wrote about reverse-engineering ASICs based on behavior vs.
<snip>
>Can anyone recommend a lab that will do this, and take photomicrographs, at
>a "reasonable" price?
>Before everyone jumps on me about piracy, I'll explain that the ROM
>and PLA code in question is NOT copyrighted.

So why not look at what they do, the functionality and re-create it
with new parts? That way you avoid legal problems.

Regards,
Pieter

Article: 82294
Subject: Re: rules to assign pins to FPGA?
From: "dfx" <mpillai@prodacc.com>
Date: 10 Apr 2005 11:00:34 -0700
Links: << >>  << T >>  << A >>
Vax,

DesignF/X(TM) - is specifically designed for this task and delivers
easy, rapid and accurate **Xilinx** FPGA pin assignment. DesignF/X
capabilites include:

1) Extensive DRCs that include all published rules related to pin
assignment.
2) Focus-filters that ensure only compatible pins can be assigned into
banks - for both single ended and differential signals.
3) Clock/data pin sync to enable rapid local and global clock driven
systems implementations.
4) Weighted Average SSO (WASSO) calculations that provide an essential
SSO check.
5) A comprehensive but easy-to-use GUI that supports rapid feedback,
problem resolution and task completion to make DesignF/X the easiest,
fastest and most accurate method of Xilinx FPGA pin assignment
available today.

We invite you to join several other FPGA designers and find out more
for yourself with our free trial download at http://www.prodacc.com

With best wishes,

Manu Pillai

vax, 9000 wrote:
> I am a newbie and I need rules to assign pins to FPGA. I would
imagine some,
>
> 1. Group signals that are natually related, and assign them to the
same I/O
> bank/side of the FPGA;
> 2. Let the software to assign pins, then fix some pins according to
the
> automatic assignment, then let the software run again. Do this
iteratively
> for several times.
> 
> What is your experience? Suggestions are welcomed.
> 
> vax, 9000


Article: 82295
Subject: Re: edk annual renewal cost?
From: Ziggy <Ziggy@TheCentre.com>
Date: Sun, 10 Apr 2005 18:07:46 GMT
Links: << >>  << T >>  << A >>
Antti Lukats wrote:
> "Ziggy" <Ziggy@TheCentre.com> schrieb im Newsbeitrag
> news:eTc6e.3688$GJ.1717@attbi_s71...
> 
>>Antti Lukats wrote:
>>
>>>"starfire" <starfire151@cableone.net> schrieb im Newsbeitrag
>>>news:115ikci5cm72pe8@corp.supernews.com...
>>>
>>>
>>>>I am fairly new to the FPGA world.  I've been using Actel parts
>>>
>>>(Axcelerator
>>>
>>>
>>>>family) at work but I would like to migrate to the Xilinx family for the
>>>>next generation design for an existing project.  I would like to take
>>>>advantage of the in-cricuit reprogrammablility and the high speed parts
>>>>(either Virtex II or Virtex 4).  I've downloaded the free WebPack from
>>>>Xilinx and have purchased the Spartan 3 Starter kit.  I've done a little
>>>>checking into the costs of development tools for home use for embedded
>>>>processors.
>>>>
>>>>According to the Xilinx home page advertising the EDK, the package cost
> 
> is
> 
>>>>about $495.  This is for a one-year license.  Does this mean I would
> 
> have
> 
>>>to
>>>
>>>
>>>>pay $495 every year I wanted to use this package?  Is this the only way
> 
> to
> 
>>>>get support for embedded processors like Microblaze and PowerPC?  Are
>>>
>>>there
>>>
>>>
>>>>any alternatives (less expensive) for home use?  I would like to develop
>>>>code for FPGAs (fairly high speed devices... > 300MHz) at home then
> 
> employ
> 
>>>>the designs at work (where a separate license with annual renewal) would
>>>
>>>be
>>>
>>>
>>>>established.
>>>>
>>>>Is the EDK to only way to get generation support for Macro models?
>>>>
>>>>Is there a better route to development that anyone could suggest?
>>>>
>>>>Thanks.
>>>>
>>>>Dave
>>>>
>>>
>>>
>>>well first of all you dont have to use EDK if you are looking for
>>>alternatives
>>>www.gaisler.com there is free open-source GRLIB SoC and toolchain
> 
> including
> 
>>>uclinux support for LEON3 (SPARC) softcore, thats completly free,
> 
> inlcuded
> 
>>>free PCI
>>>and wrapper around ethernet and can from the opencores
>>>
>>>the LEON/GRLIB is SoC is slightly larger than small MicroBlaze based
> 
> system
> 
>>>a very small GRLIB SoC fits into S3-400 but barely, anyway in any larger
>>>FPGA the LEON3 SoC is an alternative
>>>
>>>of course if at work there is EDK then you must use EDK
>>>Antti
>>>
>>>
>>
>>Not disagreeing with the Leon3 being really cool, but if he doesnt get
>>the EDK how would one actually load the FPGA? Would there be free tools
>>to do that?
>>
>>I also think he wants to really do his own development as well.. Not
>>just grab a pre-done core.
>>
>>I know for some of us, $500/year would be steep for a hobby.. ( yes i
>>realize that the hobby business isnt what supports these companies, so
>>they really dont care much about us. So free tools are nice. )
> 
> 
> I dont get you, all you need is some FPGA S3-400 is enough
> then grab GRLIB build your SoC use 5 wires to LPT port cable
> to configure the then Sparc SoC already is working in the FPGA
> nothing else required.
> 
> there is lots todo with GRLIB too :)
> 
> antti
> 
> 

Perhaps beacuse some of us want to do our OWN designs too?

Article: 82296
Subject: Re: edk annual renewal cost?
From: Duane Clark <dclark@junkmail.com>
Date: Sun, 10 Apr 2005 18:09:59 GMT
Links: << >>  << T >>  << A >>
starfire wrote:
> ...
> According to the Xilinx home page advertising the EDK, the package cost is 
> about $495.  This is for a one-year license.  Does this mean I would have to 
> pay $495 every year I wanted to use this package? 

Yes, there is an annual fee, which at least if paid directly through 
Xilinx, is $495 (having just paid it a few days ago).

> Is this the only way to 
> get support for embedded processors like Microblaze and PowerPC? 

Not strictly. What EDK provides is two main things that I find useful. 
First is a fairly painless, complete environment for developing the 
hardware and software. More significant, EDK includes (included for the 
$495 paid for EDK) a bunch of cores for performing lots of common 
functions. For example, cores for all kinds of different memories, both 
internal memory and a wide variety of external memory types. That alone 
is well worth the price to me. Almost all these cores include VHDL 
source too.

> Are there 
> any alternatives (less expensive) for home use?  I would like to develop 
> code for FPGAs (fairly high speed devices... > 300MHz) at home then employ 
> the designs at work (where a separate license with annual renewal) would be 
> established.
> 

Well, you might want to read the license carefully. While of course few 
will admit it here, I think it is fairly common for people to have 
copies of the software at home for this purpose, and frankly I think it 
is in the interest of Xilinx to ignore such uses. There is no hardware 
license enforcement (via flexlm or whatever) on EDK. Probably the bigger 
factor is whether your company allows such use; it is not worth getting 
fired over.

Since this apparently would benefit you at work, probably a good way to 
obtain EDK and also get familiar with it is to look into some of the 
"evaluation" boards offered by the various chip vendors and Xilinx. 
Several of these include EDK as part of the purchase price, and some 
also include more elaborate tool such as a complete Linux environment 
(not included with EDK). I consider that the learning hump on these 
tools is quite large, and having a complete working board and 
environment to start from was invaluable to me. Without that, it is 
clear to me after the fact that I would have spent substantially more 
time trying to figure out all the pieces.

Article: 82297
Subject: Re: Neural Networks in FPGA
From: Nick <no-email@published.nul>
Date: Sun, 10 Apr 2005 20:19:57 +0200
Links: << >>  << T >>  << A >>
On Sat, 09 Apr 2005 22:21:59 -0700, John  Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

>On Sat, 9 Apr 2005 18:17:18 -0700, "Symon" <symon_brewer@hotmail.com>
>wrote:
>
>>No, no-one has. That's why when you put 'neural nets fpga' into Google, you 
>>get no hits whatsoever. Apart from the first 10000, that is.
>>Syms.
>
>
>More importantly, has anybody found a use for neural nets?
>
>John
>

Yes,

I've very likely that the letter you receive are sorted by zip code
using a neural nets. That's only one example in a million others

Nick

Article: 82298
Subject: Re: edk annual renewal cost?
From: "Antti Lukats" <antti@openchip.org>
Date: Sun, 10 Apr 2005 20:24:49 +0200
Links: << >>  << T >>  << A >>
"Ziggy" <Ziggy@TheCentre.com> schrieb im Newsbeitrag
news:SXd6e.15934$g65.13221@attbi_s52...
> Antti Lukats wrote:
> > "Ziggy" <Ziggy@TheCentre.com> schrieb im Newsbeitrag
> > news:eTc6e.3688$GJ.1717@attbi_s71...
> >
> >>Antti Lukats wrote:
> >>
> >>>"starfire" <starfire151@cableone.net> schrieb im Newsbeitrag
> >>>news:115ikci5cm72pe8@corp.supernews.com...
> >>>
> >>>
> >>>>I am fairly new to the FPGA world.  I've been using Actel parts
> >>>
> >>>(Axcelerator
> >>>
> >>>
> >>>>family) at work but I would like to migrate to the Xilinx family for
the
> >>>>next generation design for an existing project.  I would like to take
> >>>>advantage of the in-cricuit reprogrammablility and the high speed
parts
> >>>>(either Virtex II or Virtex 4).  I've downloaded the free WebPack from
> >>>>Xilinx and have purchased the Spartan 3 Starter kit.  I've done a
little
> >>>>checking into the costs of development tools for home use for embedded
> >>>>processors.
> >>>>
> >>>>According to the Xilinx home page advertising the EDK, the package
cost
> >
> > is
> >
> >>>>about $495.  This is for a one-year license.  Does this mean I would
> >
> > have
> >
> >>>to
> >>>
> >>>
> >>>>pay $495 every year I wanted to use this package?  Is this the only
way
> >
> > to
> >
> >>>>get support for embedded processors like Microblaze and PowerPC?  Are
> >>>
> >>>there
> >>>
> >>>
> >>>>any alternatives (less expensive) for home use?  I would like to
develop
> >>>>code for FPGAs (fairly high speed devices... > 300MHz) at home then
> >
> > employ
> >
> >>>>the designs at work (where a separate license with annual renewal)
would
> >>>
> >>>be
> >>>
> >>>
> >>>>established.
> >>>>
> >>>>Is the EDK to only way to get generation support for Macro models?
> >>>>
> >>>>Is there a better route to development that anyone could suggest?
> >>>>
> >>>>Thanks.
> >>>>
> >>>>Dave
> >>>>
> >>>
> >>>
> >>>well first of all you dont have to use EDK if you are looking for
> >>>alternatives
> >>>www.gaisler.com there is free open-source GRLIB SoC and toolchain
> >
> > including
> >
> >>>uclinux support for LEON3 (SPARC) softcore, thats completly free,
> >
> > inlcuded
> >
> >>>free PCI
> >>>and wrapper around ethernet and can from the opencores
> >>>
> >>>the LEON/GRLIB is SoC is slightly larger than small MicroBlaze based
> >
> > system
> >
> >>>a very small GRLIB SoC fits into S3-400 but barely, anyway in any
larger
> >>>FPGA the LEON3 SoC is an alternative
> >>>
> >>>of course if at work there is EDK then you must use EDK
> >>>Antti
> >>>
> >>>
> >>
> >>Not disagreeing with the Leon3 being really cool, but if he doesnt get
> >>the EDK how would one actually load the FPGA? Would there be free tools
> >>to do that?
> >>
> >>I also think he wants to really do his own development as well.. Not
> >>just grab a pre-done core.
> >>
> >>I know for some of us, $500/year would be steep for a hobby.. ( yes i
> >>realize that the hobby business isnt what supports these companies, so
> >>they really dont care much about us. So free tools are nice. )
> >
> >
> > I dont get you, all you need is some FPGA S3-400 is enough
> > then grab GRLIB build your SoC use 5 wires to LPT port cable
> > to configure the then Sparc SoC already is working in the FPGA
> > nothing else required.
> >
> > there is lots todo with GRLIB too :)
> >
> > antti
> >
> >
>
> Perhaps beacuse some of us want to do our OWN designs too?

Hi Ziggy

what are you trying to say?
there is way more possibilities to your OWN designs with GRLIB then with EDK
!
simply because the EDK is partially closed and limited by GRLIB comes with
full sources, just instead making PLB/OPB peripherals you do AHB/APB
peripherals

antti








Article: 82299
Subject: Re: rules to assign pins to FPGA?
From: Mike Treseler <mike_treseler@comcast.net>
Date: Sun, 10 Apr 2005 11:36:25 -0700
Links: << >>  << T >>  << A >>
> "vax, 9000" <vax9000@gmail.com> wrote
>>2. Let the software to assign pins, then fix some pins according to the
>>automatic assignment, then let the software run again. Do this iteratively
>>for several times.

Jim Wu wrote:
> No, do not do this.

I agree about not iterating.

However, running a single unconstrained
place and route tells me
if the design fits at all, _before_
I manually enter lots of pin numbers.

It also gives me hints of router
preferences for pin assignments I don't
care about.


        -- Mike Treseler



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