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I have a design that is a one hot FSM.
Sometime the FSM was locked up invalid state after reset. But I had set
the default state.
Does anyone have any idea on how this could happen ?
Thanks
My design is as follows,
-------------------------------------------------
always @(posedge clk or negedge rst_n) begin
if (!rst_n)
cur_state <= IDLE;
else
cur_state <= next_state;
end
always @(*) beign
case (cur_state)
IDLE: next_state = ST1;
.
.
.
default: next_state = IDLE;
endcase
end
Article: 93726eehinjor wrote: > Hi,everybody. > I have some questions about pci interface on Cyclone.Would someone help > me? > First,Which pins of PCI should be pull-up or pull-down on the board? > Second,Do some resistors(33ohms or 50ohms) to be series between EP1C6 > and PCI? > > Thanks. Without having used the Cyclone, I can say that if the PCI interface is a standard one, the pull ups/downs required are in the PCI spec (which I strongly suggest you read). Available at: http://www.pcisig.com/specifications Whether you need series resistors depends ont he physical characteristics of the drivers and the board. Cheers PeteSArticle: 93727
Austin Lesea wrote: > Recently posted on our website: > > http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex4/resources/Virtex-4_Power_Case_Study.pdf > > Is a case study in which the latest claims of power savings by the > competitor's software are debunked. > > I had intended to post this as part of the earlier thread, but I > couldn't find the link to the above white paper. > > If you ignore the superiority of Virtex 4, and just concentrate on the > improvement in power from the tool, going from ~ 2.8 watts to ~ 2.6 > watts, or an improvement of 200 mW, is roughly an improvement of 7% less > power. > > So, routing and placement can really save some power. Or perhaps, one > should say poor routing and poor placement can increase power? > > Or should one say that Virtex 4 uses so much less power, that talking > about how much is 'saved' by the software tool is just a distraction to > fool the unwary? > > Austin It has long been known that appropriate placement and routing at the physical layer can save power (not by a huge amount, but certainly of the order of 5% or so depending on the circumstances). I've done a lot of high speed design work, and minimising power is always an issue. To find it can be done internally with the place and route tool is not particularly surprising - indeed it is to be expected. I wonder when the optimisation goal will be expanded to include 'power' (instead of just speed and space). Cheers PeteSArticle: 93728
> Alanwrote: There are a paper of Dynamic Partial Reconfiguration "A Module-Based > Dynamic Partial Reconfigration". > I also resurch of this subject.Good Luck! : ) > > Alan Chen Alan, thanx for the reply......well i would like to know wat actually r u doing in the dynamically reconfigurable FPGA topic.Article: 93729
wtxwtx@gmail.com wrote: > Hi, > I read patent 6,914,453 by IBM and trying to follow the paper's claim > pattern to write my claims. > > The next question is: > What is the difference between Method and Apparatus in a patent claim > area? > > The interesting thing happens with the claims: > The patent repeats all sentences in claims for Method with a few > changes to make up claims for Apparatus. > > I will follow their patterns, but I really don't realize why to do them > repeatedly? > > Any patent precedents that if not repeated, a very serious consequences > would follow? > > Thank you. > > Weng > Read at least a dozen different patents, pick those that "closely" relate to what you are doing. Note that there are two kinds of claims, independent and dependent. The first claim is the most important and is always an independent claim. Usually, but not always, the second claim is a dependent claim and will be worded like "...of claim 1" or such, some aspect being a little different than that described in claim one. Crafting claims is an art. You must describe the novel item so others "skilled in the art" can reproduce it. That does not mean that what they produce will work as well as what you invented, and/or that they *understand* or *believe* what you said. Also, if the device is completely novel (such as the transistor first patented in the US by Lillienfeld in the late 1920s), it is not required that a correct theory be described - a wild guess will do. And....even as a "small entity" it is expensive. If the claims are crafted properly, few if any will raise an objection (does not correctly fit the legal requirements) and a good patent lawyer can "argue" (ie: give good legal reasons) that the wording is OK as-is. Furthermore, the time in process will be "short" - less than 2 years. The claims should cover all possible aspects that can be legally covered; some claims being rather specific and others as general as possible, looking at the item upside-down, sideways, backwards, inside-out, and crazy-blue-sky if one can. If you invent the paper clip and describe only its holding capabilities, you lose the sales and profits of its use as a slingshot.Article: 93730
Some Synthesis programs just ignore what you write in the "default", if
you don't set the
attribute of the state machine as "safe".
If you go to the Synplify webpage you can find a good app notes talking
about this kind of problem.
A solution to your problem could be:
1) your FSM shoule be "safe"
2) instead of :
> always @(*) beign
> case (cur_state)
> IDLE: next_state = ST1;
> .
> .
> .
> default: next_state = IDLE;
> endcase
> end
write something like:
always @(*) beign
case (cur_state)
IDLE: next_state = ST1;
.
.
STn : next_state = IDLE; .
default: next_state = IDLE;
endcase
end
I hope this help.
Happy new year.
Francesco
akun wrote:
> I have a design that is a one hot FSM.
> Sometime the FSM was locked up invalid state after reset. But I had set
> the default state.
> Does anyone have any idea on how this could happen ?
>
> Thanks
>
> My design is as follows,
> -------------------------------------------------
> always @(posedge clk or negedge rst_n) begin
> if (!rst_n)
> cur_state <= IDLE;
> else
> cur_state <= next_state;
> end
>
> always @(*) beign
> case (cur_state)
> IDLE: next_state = ST1;
> .
> .
> .
> default: next_state = IDLE;
> endcase
> end
Article: 93731"Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1135825838.800221.321020@g47g2000cwa.googlegroups.com... > If you change the fundamental > frequency, the rise and fall times do not change, and neither does the > damage caused by these rise and fall times. > Hi Peter, Here's a time-domain counter-example to your premise. A fast rising edge arrives at a badly terminated node. The signals reflect back and forth causing (say) a ringing effect. Luckily, the amplitude of this ringing is not enough to change the state of the receiver input, so all works well. After a while the ringing dies down. After the ringing has died down the falling edge arrives and there's no problem. OK, now the same thing but with a faster fundamental:- A fast rising edge arrives at a badly terminated node. The signals reflect back and forth causing (say) a ringing effect. Luckily, the amplitude of this ringing is not enough to change the state of the receiver, so all works well, until the falling edge arrives while the line is still ringing. The combination of the falling edge and the ringing causes the receiver to see a rising edge. Not good. In this case, the fundamental frequency DOES affect the circuit. On a separate point, it's as well to remember that digital ICs inputs aren't a simple hi-impedance open circuit. They have some amount of capacitance. (See Symon vs. Austin vs. Brian in CAF passim!) This means that low frequencies see the input as an open, but very high frequencies see them as a short. For a Xilinx FPGA, the 50 ohm impedance point is at about 300MHz. Ish. I do know at least one bloke whose brain apparently has a hard-wired Smith chart in it. Mine doesn't have this feature so I simulate, or, if we're down the pub, ask my mate! Cheers, Syms.Article: 93732
This could be due to your reset signal not meeting setup and hold when it is released. A lot of designs don't see this because they are binary(only under certain conditions e.g. "000" -> "001"), grey or one-hot encoded and effectively only one flip-flop is affected directly after reset is released. There encoding is such that they stay in the state or go to the next legal state. Remedy - make your reset signal a synchronous exit from active state or make your encoding tolerant of not meeting setup and hold. The former can be done by creating a flip-flop that has a asynchronous input reset signal putting to active state and making exit dependent on a clock edge condition. John Adair Enterpoint Ltd. - Home of Raggedsone1. The Low Cost Spartan-3 Development Board. http://www.enterpoint.co.uk "akun" <akun.cheng@yahoo.com.tw> wrote in message news:1135846099.855537.192600@g47g2000cwa.googlegroups.com... >I have a design that is a one hot FSM. > Sometime the FSM was locked up invalid state after reset. But I had set > the default state. > Does anyone have any idea on how this could happen ? > > Thanks > > My design is as follows, > ------------------------------------------------- > always @(posedge clk or negedge rst_n) begin > if (!rst_n) > cur_state <= IDLE; > else > cur_state <= next_state; > end > > always @(*) beign > case (cur_state) > IDLE: next_state = ST1; > . > . > . > default: next_state = IDLE; > endcase > end >Article: 93733
I stumbled upon the System Monitor feature in the Virtex-4 handbook while looking for the DXN/DXP pins from Virtex-II for temperature supervision. Perfect, just what we need! Both temperature and power supply supervision, without the hazzle of external SMBus measuring devices, voltage comparators and the like. Only trouble is (gee wizz..) the feature is marked as "NOT supported" in Xilinx Answer Record 20102. Since that option seems to be out the window, are there still means to supervise chip temperature? Or do we need to glue a sense diod atop each package? Or maybe the System Monitor will be revived in later stepping levels of silicon? Anyone who knows? /LarsArticle: 93734
Hi Lars, I use a Maxim MAX6695 together with the DXN, DXP pins. Works lovely! Cheers, Syms.Article: 93735
Hi Robert, Thank you for your excellent advice. Here are you key points: 1. Read at least a dozen "closely" relate patents; 2. You must describe the novel items; 3. The claims should cover all possible aspects that can be legally covered. I think this is inventor's responsibility: looking at the item upside-down, sideways, backwards, inside-out, and crazy-blue-sky if one can. The example of paper clip doesn't exist for eletronical circuits. For eletronical circuit, the inventor must have to think a lot about any possible designs around patents that any lawyers couldn't do it. Block them or invent them together. I don't understand the following statement: even as a "small entity" it is expensive. Thank you. WengArticle: 93736
It seems these pins are renamed TDP/TDN in Virtex-4. Good, so we don't need to resort to glue... I wonder if these pins are as succeptable to switching noise as DXP/DXN in the Virtex/Virtex-E/Virtex-II? It seems the only way to aquire a reliable reading is to stop clocking the device (Answer Record 11558). In my experiance, Virtex readings where fairly stable, Virtex-E (at least the devices I have used) gave a +15 degrees Celsius higher reading than was the case, and Virtex-II again where fine in most situations but could start to fluctuate wildly under certain conditions. Maybe it was my board that was badly layed out... We used the MAX1617A and the ADM1021. I also wonder what became of System Monitor??? /LarsArticle: 93737
Hi Lars, Well my V2PRO stuff works great and the FPGA is thrashing away while the measurement is going on. As you say, I am very careful with my layout. And I read the Maxim datasheet very carefully indeed! Good luck, Syms.Article: 93738
> Recently posted on our website: > > http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex4/resources/Virtex-4_Power_Case_Study.pdf > > Is a case study in which the latest claims of power savings by the competitor's software are debunked. Why are the power values measured at 25C and than scaled, in a way that is not given in the paper, to 85C. Either provide the values at 25C for reference or measure at 85C. Another point: measurements are nice, but what about the worst case values? MartinArticle: 93739
"Martin Schoeberl" <mschoebe@mail.tuwien.ac.at> wrote in message news:43b3ef46$0$11094$3b214f66@tunews.univie.ac.at... > Why are the power values measured at 25C and than scaled, in a way > that is not given in the paper, to 85C. Martin, You did read this? "We collected power data at 25°C junction temperature from idle (0 MHz) up to 200 MHz, in 50Mhz steps. We then scaled the results to 85°C using static power data previously taken on Virtex-4 and Stratix II devices over temperature (see Xilinx White Paper WP223 for further information). Note that previous testing has shown that dynamic power does not vary significantly with temperature for either family of devices. " Cheers, Syms.Article: 93740
Hi I am really happy to see my Sample Pack board to boot again from on board flash - in my attempt to reprogram it I did manage to burn (with a small hole on top of the IC package) all the onboard power supply and to partially damage the strataflash on board. and when attempting to check the flash using universal scan my FPGA based PCI Cable III burned completly as well. so I ended up desoldering a TSOP56 flash from Avent Virtex4LX25 board and replacing the damaged flash on the sample pack board. and shortly after that the board did reboot again from the configuration programmed into the flash. the "standalone flash programmer for the sample pack board" will be available shortly. http://xilant.com/content/view/28/51/ if anyone needs it already now, please email me to my best efforts I did not manage to programm the flash using the 'approuch' suggested in the sample pack manual, maybe other are more lucky, but I have given up, or better waiting for EDK 8.1 or the webcase solution Antti PS I wonder that the free Spartan3e Sample Pack doesnt seem to be available in Europe? (only in north america and asia/pacific)Article: 93741
Symon, I also prefer to look at it as rise and fall times causing problems. Obviously, anything that happens in the time domain is also happening in the frequency domain, and the opposite as well. We are just observers trying to understand what happened. The clock pulse itself exists in both domains simultaneously. It is like the physics student who asked the professor "is light a particle or a wave?" The answer, of course, is 'yes.' Sometimes modeling it as a particle gives you insight into what happened, and sometimes modeling it as a wave tells you something useful. So it is with reflections. If the rising edge gets a kink in it due to a reflection, it is easier to explain it as fast rising edges hitting a discontinuity and reflecting in the time domain. Is it 'wrong' to say that the clock frequency is the cause of the problem (even though we both know that frequency and time are two ways of describing the physics of the system)? I think so, the frequency model is the wrong approach to understand what is happening (to a pulse on a wire). If I am trying to explain a clock pulse on a wire, I think the time domain is the best choice. Austin Symon wrote: > "Peter Alfke" <alfke@sbcglobal.net> wrote in message > news:1135825838.800221.321020@g47g2000cwa.googlegroups.com... > >> If you change the fundamental >>frequency, the rise and fall times do not change, and neither does the >>damage caused by these rise and fall times. >> > > Hi Peter, > Here's a time-domain counter-example to your premise. > A fast rising edge arrives at a badly terminated node. The signals reflect > back and forth causing (say) a ringing effect. Luckily, the amplitude of > this ringing is not enough to change the state of the receiver input, so all > works well. After a while the ringing dies down. After the ringing has died > down the falling edge arrives and there's no problem. > OK, now the same thing but with a faster fundamental:- > A fast rising edge arrives at a badly terminated node. The signals reflect > back and forth causing (say) a ringing effect. Luckily, the amplitude of > this ringing is not enough to change the state of the receiver, so all works > well, until the falling edge arrives while the line is still ringing. The > combination of the falling edge and the ringing causes the receiver to see a > rising edge. Not good. > In this case, the fundamental frequency DOES affect the circuit. > > On a separate point, it's as well to remember that digital ICs inputs aren't > a simple hi-impedance open circuit. They have some amount of capacitance. > (See Symon vs. Austin vs. Brian in CAF passim!) This means that low > frequencies see the input as an open, but very high frequencies see them as > a short. For a Xilinx FPGA, the 50 ohm impedance point is at about 300MHz. > Ish. I do know at least one bloke whose brain apparently has a hard-wired > Smith chart in it. Mine doesn't have this feature so I simulate, or, if > we're down the pub, ask my mate! > Cheers, Syms. > >Article: 93742
Lars, What happened to the System Monitor? Well, it is a long, and rough road, but we fixed it. Or at least, we fixed everything that was wrong with it, or know how to, or have bits and pieces of it working. I believe in the most recent stepping all parts have 'working' (yet untested) system monitors. What was left unfixed was gain error (the gain varies by more than we would like it to, but we know how to fix that, too - we just did not). The offset is automatically corrected, so that was never an issue. Linearity was broken, and now it is fixed. The Vccaux voltage sensor point also was measured at the wrong node (simple error, so we can do it right next time). What is left is the core voltage sensor (which works), the temp sensor (which works), and the external voltage inputs, multiplexers, alarm levels, scanners, etc. which all work (save for the variation in gain that is beyond what we would have liked). To re-introduce the feature this late in the game is just not possible, so we will chalk this experience up to experimental silicon prototyping that just happens to be in every part: and being on the "bleeding edge" of the technology, and learning just how difficult mixed signal IC design is (something we learn again and again, with each new technology it seems). If we did reintroduce it, we would have to specify it, and then test it, and then deal with the yield loss for ones where it doesn't work. So, we won't (do any of that above). But we did do the test program, and screened enough to make sure that when we do it (again) we will be ready for it. We are supporting the system monitor for anti-tamper methods security research, so it still has some (small) life in the real world. Austin Lars wrote: > It seems these pins are renamed TDP/TDN in Virtex-4. Good, so we don't > need to resort to glue... > > I wonder if these pins are as succeptable to switching noise as DXP/DXN > in the Virtex/Virtex-E/Virtex-II? It seems the only way to aquire a > reliable reading is to stop clocking the device (Answer Record 11558). > In my experiance, Virtex readings where fairly stable, Virtex-E (at > least the devices I have used) gave a +15 degrees Celsius higher > reading than was the case, and Virtex-II again where fine in most > situations but could start to fluctuate wildly under certain > conditions. Maybe it was my board that was badly layed out... We used > the MAX1617A and the ADM1021. > > I also wonder what became of System Monitor??? > > /Lars >Article: 93743
"Antti Lukats" <antti@openchip.org> wrote in message news:dp06mp$am3$00$1@news.t-online.com... > "Marco T." <marcotoschi@nospam.it> schrieb im Newsbeitrag > news:dp060n$s04$1@nnrp.ngi.it... >> Hallo, >> I'm developing a microcontroller based on Virtex-4FX. >> This system should send text to a USB printer. >> >> I think to use Cypress 67300 usb microcontroller. >> >> In what way could I send text to printer? >> >> I must use a RTOS like VxWorks to have usb driver support? >> >> Many Thanks >> Marco > Xilinx ML40x boards have a demo that does work with usb printer > v4 and 67300 are used on the board look there > > antti > I'll lookfor it. Many Thanks MarcoArticle: 93744
>> Why are the power values measured at 25C and than scaled, in a way >> that is not given in the paper, to 85C. > Martin, > You did read this? "We collected power data at 25°C junction temperature from idle (0 MHz) up to 200 MHz, in 50Mhz steps. We then > scaled the results to 85°C using static power data previously taken on Virtex-4 and Stratix II devices over temperature (see > Xilinx White Paper WP223 for further information). Note that previous testing has shown that dynamic power does not vary > significantly with temperature for either family of devices. " > Cheers, Syms. I did read this and that is exactly the point I want to criticize. I don't like measuring an aspect at one temperature point, not showing the results, but scaling it 'in some way' to a different temerature point for the final graph. However, it's not so important - just a little bit of marketing stuff ;-) MartinArticle: 93745
OK Austin, I sympathise. As a matter of fact, quite a few "bells and whistles" where scrapped in my recent projects, some of them would have been quite useful. Sometimes it is better to acknowledge the fact that it is just not worth the effort... It would have been nice though. Better luck next time! Me, I'll start looking for replacements for the MAX1617, that part has caused enough greif.Article: 93746
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:dp0vtb$8d9$03$1@news.t-online.com... > Hi > > I am really happy to see my Sample Pack board to boot again from on board > flash - comments to myself - it looks like nahitech is programming the flash on the sample pack board with their JTAG tools - http://nahitafu.cocolog-nifty.com/nahitafu/2005/12/xilinx_spartan3_3fdf.html on the above link the Actual DVD box is seen along with 25USD OFF splash, for the case the text on the picture is not readable: it is a discount offer for 25USD from Spartan 3e Starterkit price, valid til 31.01.2006 so do not order the Starterkit before getting the free Sample Pack :) Antti PS too bad nahi decided to discontinue their free JTAG stuff, now all his things are commercial with no demo no eval and whats even worse only in japaneseArticle: 93747
Anyone an idea about the availability and pricing of their starter kit. The new Fusion line looks very interesting. Almost all needed stuff on-chip - I'm only missing some larger SRAM for microprocessor applications. MartinArticle: 93748
Alex Gibson wrote: > According to the front page of xilinx's site but not yet in the web shop. > > http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-DK > > With double the amounts of ram and flash than origonally announced. > > Now if only xilinx sold digilentincs addon cards > so could get some decent shipping charges. > > Alex It's been front-(wb)page news for 2 days and it's *still* not at the online store. If it's available, what's the proper way to get hold of one? Do I need to contact my local sales guy for a development board? We're a big account but I don't want to bother with a PO in this "belt tightening" era so I'll just buy the darned thing myself and use it at work and home. Best way to do this is the online store. Where else *should* I go?Article: 93749
Martin Schoeberl wrote: > However, it's not so important - just a little bit of marketing > stuff ;-) No, Martin, it is not Marketing, it is Science. Dynamic power and static power (leakage) have different temperature dependencies: Dynamic power is independent of temperature (since the frequency and the capacitance do not change), while leakage current is very temperature dependent. The two can be added linearily. Therefore it is not necessary to measure dynamic power at temperature. And let this quibbling not obfuscate the basic fact: Xilinx power consumption is much lower than Altera's. We have to mention this because Altera makes so much noise about their (non-existent) power superiority. Their claims are just Marketing BS... Peter Alfke, Xilinx Applications
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z