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"Kevin Brace" <sa0les1@brac2ed3esi4gns5olut6ions.com> schrieb im Newsbeitrag news:Mntrf.36310$BZ5.11211@newssvr13.news.prodigy.com... > Hi bjzhangwn, > > Take a look at the reply I made to Tim Wescott. > My estimated cost of developing a PCI Express IP core is at least $90,000 > ($60,000 for bleeding-edge oscilloscope, $10,000 for four FET Hi Kevin, its not that bad the $$$ money needed. For the endpoint core development sufficent is to just get an PCIe FPGA board and those cost as low as 800 USD. using that one card and the supplied ipcore it is defenetly possible to develop own core. what makes it un-reasonable is the amount of time investment needed what I would expect to be around one man year (when verfiied). So in case you have that one year of your life to 'invest' into the project it makes no sense to start. "black" market PCIe cores with PHY are known to be offered for 50,000 USD - what is way below of the costs of developing it, as the PHY is way more complex as the endpoint logic. Anyway, if someone is really up to develop the PCIe endpoint core, I offer setting up the verification testbench for it, and maybe also do the FPGA testing for it. (I have done some preliminary work on the subject so I could re-use that experience) AnttiArticle: 93576
Wow, this thread had hit the 40 post mark already. First off, I want to thank all the people that have given me a great deal of help and insight in understanding verilog/synthesizers. It seems my biggest problem was that I though that HDL would give me the ability to write behavioral code and the software would be able to make it work - i.e. if I add a delay, it generates all the required counters/etc to implment the delay. But it seems to be a lot more primative than I had expected. However, I am a bit irked at the continued comments about this "digital design" class. I have no problems taking a course that's recommended, but when I try to map "digital design" to a real course and ask for help doing so, I get nothing but degrading comments. So, I will ask one last time in a more direct fasion: Rather than degrading my abilities, please find a "digital design" class from the Berkely course schedule. http://schedule.berkeley.edu . I also want to follow by saying that I am not an EE major nor have I taken any EE classes in my life. I'm a bioengineering major and the bulk of my courses have been dealt with mechanics, chemistry, physics, biology, etc. With that said, I have done a lot of electronics work - mostly with microcontrollers, and the work I've done has been well liked by the people I have worked for. I think of verilog/HDL as a tool to use, not a career destination. All I want is a rudementary understanding of it so I can later make informed decisions about what the right tool to use for a task is. And getting back to the notion of asking questions vs. doing my own "studying" -- I've learned more in the past 40 posts about verilog/synthesizers than I have in the dozens of hours I've spent reading books and web pages on the material. And in response to the RTFM, I actually followed someone else's suggestion of googling for "tristate verilog". I found some docs for altera, whch didn't seem to work for xilinx. After bit of playing, I figured it out. I appreciate that you answered my question, twice, but there was no need to be insultive about it. I really didn't know where to look about the tristate thing - you could have said "look in the xxxxx docs" or given me the answer and had that been the end of it. One other comment before I ask some real questions. I really want to thank the people that have posted brief and accurate answers to my questions as well as those that have provided me with pointers. Ok, Real questions in response : - Are there a standard set of templates that all synthesizers use? The problem was that the same synthesizer said it couldnt find a template for one target CPLD, but it found it for another. Why would this be? Does anyone know of a respository for standard templates? - There have been several replies indicating that the order of the statment has to do with priorities, and an async reset has a higher priority. Why is this? Is this just how flipflops are physically built? Andy gave an example about a high vs. low reset. Was the second example invalid? My code "if (!reset)..." failed, but what if it was an active low reset. Then shouldn't it have worked? Or was the reset implied in the <= 0, in which case the problem was not the (!reset), but rather the location of <=0? What exactly defines a reset? - about the rising & falling edge of a signal triggering a block - if two flipflops are required, so be it. is it bad form? Shouldn't the synthesizer be able to deal with it? thnx, reza p.s. people keep saying there are great resources on the net, but i'm having problems finding good information. If anyone knows of some good sites, I would love to know. google is not a valid answer to this question, but google search terms are if you've found good info using the phrase.Article: 93577
Hi Antti, I don't share your optimism regarding PCI Express. Yes, in theory, it is true that anyone can develop a PCI Express IP core using a sub $1,000 PCI Express FPGA development board. But in practice, one probably needs to have at least a PCI Express protocol analyzer to understand what is going on in PCI Express. And I don't think that is cheap. (I am guess it costs $20,000 to $30,000.) My fear (Maybe that's not an appropriate word.) from reading the PCI Express Base Specification Revision 1.0a is that the initialization sequence (link training) is far more complex than anything Conventional PCI had (RST# gets asserted 100ms after the computer is switched on. 64-bit PCI adds REQ64# assertion during RST# assertion to signal 64-bit environment.). So, because the protocol is far more complex, even someone like myself who has developed a Xilinx compatible PCI IP core does have hard time understanding the entire PCI Express protocol, especially the initialization sequence. (I guess that the part I am stuck right now.) Setting up the verification environment seems a lot more challenging than Conventional PCI due to the fact that the protocol is a lot more complex. I have looked into the PCI Express checklist, and it seems much longer and more detailed than Conventional PCI. I must say that knowing Conventional PCI doesn't gets to too far with PCI Express, perhaps, knowing how Ethernet works does. Kevin Brace Antti Lukats wrote: > "Kevin Brace" <sa0les1@brac2ed3esi4gns5olut6ions.com> schrieb im Newsbeitrag > news:Mntrf.36310$BZ5.11211@newssvr13.news.prodigy.com... > >>Hi bjzhangwn, >> >>Take a look at the reply I made to Tim Wescott. >>My estimated cost of developing a PCI Express IP core is at least $90,000 >>($60,000 for bleeding-edge oscilloscope, $10,000 for four FET > > > Hi Kevin, > > its not that bad the $$$ money needed. For the endpoint core development > sufficent is to just get an PCIe FPGA board and those cost as low as 800 > USD. > > using that one card and the supplied ipcore it is defenetly possible to > develop own core. > > what makes it un-reasonable is the amount of time investment needed what I > would > expect to be around one man year (when verfiied). So in case you have that > one year > of your life to 'invest' into the project it makes no sense to start. > > "black" market PCIe cores with PHY are known to be offered for 50,000 USD > - what is way below of the costs of developing it, as the PHY is way more > complex > as the endpoint logic. > > Anyway, if someone is really up to develop the PCIe endpoint core, I offer > setting > up the verification testbench for it, and maybe also do the FPGA testing for > it. > (I have done some preliminary work on the subject so I could re-use that > experience) > > Antti > > -- Brace Design Solutions Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available for as little as $100 for non-commercial, non-profit, personal use. http://www.bracedesignsolutions.com Xilinx and LogiCORE are registered trademarks of Xilinx, Inc.Article: 93578
"Kevin Brace" <sa0les1@brac2ed3esi4gns5olut6ions.com> schrieb im Newsbeitrag news:Fkurf.37333$dO2.28554@newssvr29.news.prodigy.net... > Hi Antti, > > I don't share your optimism regarding PCI Express. > Yes, in theory, it is true that anyone can develop a PCI Express IP core > using a sub $1,000 PCI Express FPGA development board. > But in practice, one probably needs to have at least a PCI Express > protocol analyzer to understand what is going on in PCI Express. > And I don't think that is cheap. (I am guess it costs $20,000 to $30,000.) > My fear (Maybe that's not an appropriate word.) from reading the PCI > Express Base Specification Revision 1.0a is that the initialization > sequence (link training) is far more complex than anything Conventional > PCI had (RST# gets asserted 100ms after the computer is switched on. > 64-bit PCI adds REQ64# assertion during RST# assertion to signal 64-bit > environment.). > So, because the protocol is far more complex, even someone like myself who > has developed a Xilinx compatible PCI IP core does have hard time > understanding the entire PCI Express protocol, especially the > initialization sequence. (I guess that the part I am stuck right now.) > Setting up the verification environment seems a lot more challenging than > Conventional PCI due to the fact that the protocol is a lot more complex. > I have looked into the PCI Express checklist, and it seems much longer and > more detailed than Conventional PCI. > I must say that knowing Conventional PCI doesn't gets to too far with PCI > Express, perhaps, knowing how Ethernet works does. > > > Kevin Brace > where did you see my optimism? :) I only stated that up-front 100,000 $ investment is not needed. and then that the project is un-reasonable as of the man-years required. PCIe is WAY more complex as PCI. Way more. it could still be done with one low cost PCIe board, and more work, meaning making your own protocol monitor-analyzer sw, etc, etc. AnttiArticle: 93579
I think you can find it in the altera website,also you can ask the sales for help.Article: 93580
Can xilinx or altera can provided the softcore freely?Article: 93581
"bjzhangwn" <bjzhangwn@126.com> schrieb im Newsbeitrag news:1135512647.330045.150020@z14g2000cwz.googlegroups.com... > Can xilinx or altera can provided the softcore freely? > there is is opensource free version from microblaze and nios I myself do have nios-2 verilog the cores from Xilnx/Altera are also free assuming you have purchased the EDK/SOPC tools the license is then included free of charge. but there Xilinx/Altera do not offer their SoC tools for free, they must be purchased AnttiArticle: 93582
Hi Reza! I will recommend two readings that will save you a lot of headache: The first one is an expensive, but invaluable book (sorry, don't know if it exists in a Verilog version): "VHDL for Logic Synthesis" And the second one is a free PDF downloadable from Actel homepage: "Actel HDL Coding" (I am sure the other players have their own HDL coding style guides too, but this one looks the best). They will show you how synthesizers work internally. good luck! (and happy new year) PS. for some reason some people one the newsgroups waste a lot of their own time and our time by giving non-answers. If you dont have an answer, dont post!!Article: 93583
i have a V2MB1000 developement board for Partial-Reconfig. but now i want to have a try on how to using ICAP of Virtex-II FPGA on the board. if anyone have such an experience on how to do this and ready to help me, please communicate with my via liou_payphone@yahoolcom.cn(My MSN ID) or Email me. Many thanks here! ^_^ My first problem is : there is only a JTAG port on the board for downloading and programming. but ICAP shoulb be used under SelectMAP mode. firstly, jumpers should be set for JTAG mode. but when i want to use ICAP for completing my partial reconfiguration, the mode is of JTAG not SelectMAP. It is said that jumpers must not be re-set for another mode when the system is running. eager for helpArticle: 93584
<lioupayphone@gmail.com> schrieb im Newsbeitrag news:1135518143.477956.220490@g47g2000cwa.googlegroups.com... >i have a V2MB1000 developement board for Partial-Reconfig. but now i > want to have a try on how to using ICAP of Virtex-II FPGA on the board. > if anyone have such an experience on how to do this and ready to help > me, please communicate with my via liou_payphone@yahoolcom.cn(My MSN > ID) or Email me. > Many thanks here! ^_^ > > My first problem is : > there is only a JTAG port on the board for downloading and programming. > but ICAP shoulb be used under SelectMAP mode. firstly, jumpers should > be set for JTAG mode. but when i want to use ICAP for completing my > partial reconfiguration, the mode is of JTAG not SelectMAP. It is said > that jumpers must not be re-set for another mode when the system is > running. > > eager for help > ICAP can be accessed from the FPGA fabric no matter what configuration mode is selected. AnttiArticle: 93585
On 25 Dec 2005 02:03:40 -0800, "Reza Naima" <google@reza.net> wrote: > stuff snipped >However, I am a bit irked at the continued comments about this "digital >design" class. I have no problems taking a course that's recommended, >but when I try to map "digital design" to a real course and ask for >help doing so, I get nothing but degrading comments. So, I will ask >one last time in a more direct fasion: Rather than degrading my >abilities, please find a "digital design" class from the Berkely course >schedule. http://schedule.berkeley.edu . EL ENG 42 Introduction to Digital Electronics EL ENG 141 Introduction to Digital Integrated Circuits You may also want to look at the online lecture notes for this course: http://ocw.mit.edu/OcwWeb/Electrical-Engineering-and-Computer-Science/6-111Spring2004/CourseHome/index.htm Bob Perlman Cambrian Design WorksArticle: 93586
There's one more course I should mention. Eric Crabill of Xilinx teaches a digital design course at SJSU. The class notes are online at: http://www.engr.sjsu.edu/crabill/ This is probably the best how-to-do-FPGA-design course for beginners that I've seen. Bob Perlman Cambrian Design WorksArticle: 93587
How much (I would like to know only the order of magnitude) static current
does a configured XC3S200-4TQ144C device need with clock disabled, all
IO tristated etc.? A microamp? ;-)
Best regards
Piotr Wyderski
--
"If you were plowing a field, which would you rather use?
Two strong oxen or 1024 chickens?" -- Seymour Cray
Article: 93588>How much (I would like to know only the order of magnitude) static current >does a configured XC3S200-4TQ144C device need with clock disabled, all >IO tristated etc.? A microamp? ;-) It's in the data sheet. It's not small. Thin oxides leak. Very think oxides leak like a sieve. Think milliamps rather than microamps. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 93589
Hal Murray wrote:
> It's in the data sheet.
Is it that "quiescent current" parameter?
> It's not small. Thin oxides leak. Very think oxides leak like a
> sieve.
If the above is correct, it means "Typical 10, Maximum 80 mA", holy Molly!
So there will be no battery sustaining of the RAM memory contents, not good.
:-(
Best regards
Piotr Wyderski
--
"If you were plowing a field, which would you rather use?
Two strong oxen or 1024 chickens?" -- Seymour Cray
Article: 93590Piotr Wyderski wrote: > How much (I would like to know only the order of magnitude) static current > does a configured XC3S200-4TQ144C device need with clock disabled, all > IO tristated etc.? A microamp? ;-) > The data sheet says 120 mA (Iccint + Iccaux + Iccio), and that is not a typo... If you need very low quiescent current, then pick a CoolRunner CPLD (very low current, but very limited complexity compared to XC3S200) or use older technology, previous generation devices. All 130 nm, and especially 90 nm devices have considerable quiescent current, even though Xilinx uses some circuit "tricks" to keep the current down. Part of the leakage is through the ultra-thin gate dielectric, part is through transistors that are not perfectly turned off (sub-threshold leakage). It's the price you pay for high performance and high density (small size, low cost). This is perhaps the most frustrating aspect of the newer technology... Peter Alfke, Xilinx (from home) Merry Christmas to all !Article: 93591
Peter Alfke wrote:
> If you need very low quiescent current, then pick a CoolRunner CPLD
> (very low current, but very limited complexity compared to XC3S200)
Yes, unfortunately my device is quite complex, so no CPLD
chip can be used instead of an ol' good FPGA technology.
I wanted to store some data inside the chip for several weeks
when the main power supply is off, but in this situation a separate
FRAM memory will be used. BTW, since I am very new to the
Xilinx world and its nomenclature, how should I interpret the
"CLB" term? The manual says that
"The Configurable Logic Blocks (CLBs) constitute the main
logic resource for implementing synchronous as well as
combinatorial circuits. Each CLB comprises four interconnected
slices"
and I presume that "slice" means something comparable to Altera's
"Logical Element" (assumption based on figure 6 in ds099.pdf). So
why there is a separate name for a group of slices, i.e. where should
I count used CLBs instead of slices?
> It's the price you pay for high performance and high density
> (small size, low cost).
The performance is really very impressive and the price is very low
(~25 USD per chip including taxes @ 1 chip quantity), which makes
that Spartan a perfect chip for my hobbyist purposes. Unfortunately,
nothing above 3S200-144 is easily available, but the same is with
Cyclones. Playing with FPGAs is a rare hobby. :-(
> This is perhaps the most frustrating aspect of the newer technology...
Eh... :-(
> Merry Christmas to all !
Thank you, Merry Christmas to you too! :-)
Best regards
Piotr Wyderski
--
"If you were plowing a field, which would you rather use?
Two strong oxen or 1024 chickens?" -- Seymour Cray
Article: 93592
Reza Naima wrote:
> Wow, this thread had hit the 40 post mark already. First off, I want
> to thank all the people that have given me a great deal of help and
> insight in understanding verilog/synthesizers. It seems my biggest
> problem was that I though that HDL would give me the ability to write
> behavioral code and the software would be able to make it work - i.e.
> if I add a delay, it generates all the required counters/etc to
> implment the delay. But it seems to be a lot more primative than I had
> expected.
Yes. You'll have to scale down such expectations about synthesis
drastically.
> I think of verilog/HDL as a tool to use, not a career destination.
That may explain your communication problems with many of the people
here.
On a personal note, the meta-goal of my current work is to show that
your approach is meaningful and productive. You may want to
explore the link in the signature section.
> - Are there a standard set of templates that all synthesizers use?
There is an IEEE synthesis standard that all reasonable synthesis tools
will adhere to - but I agree that it doesn't seem that easy to get that
info for free.
My advice: for implementation-oriented modeling, you only need 2
templates: the synchronous always block (sensitive to a clock
edge and possibly a reset edge), and the combinatorial always
block (sensitive to the input signal levels).
Out of these, use the synchronous template for the bulk of your
work. The big advantage is that you can then raise your expectations
again. To a large extent, you can concentrate on getting the behavior
right (hard enough), and rely on the synthesis tool to give you a good
implementation. In contrast to what many people will tell you (and
sometimes shout at you), there's no need to try to visualize the exact
hardware that will come out. Believe me, they can't either.
I'll go further. Once you follow the advice above, relying on
"hardware thinking" too much will hamper productivity. Die-hard
hardware thinkers may miss the opportunity to find an elegant coding
solution without giving up efficiency in the synthesized result. So
here's a chance to do better than the experts.
> - There have been several replies indicating that the order of the
> statment has to do with priorities, and an async reset has a higher
> priority. Why is this? Is this just how flipflops are physically
> built?
I think they just implement what "asynchronous" means. Priority
seems an inherent property.
> - about the rising & falling edge of a signal triggering a block - if
> two flipflops are required, so be it. is it bad form? Shouldn't the
> synthesizer be able to deal with it?
To me, it's not obvious they should. A particular case is not
a general solution yet.
For now, just code the behavior you want using two
synchronous blocks, sensitive to different edges.
Jan
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com
Article: 93593Piotr Wyderski wrote: > how should I interpret the > "CLB" term? The manual says that > >> and I presume that "slice" means something comparable to Altera's > "Logical Element" (assumption based on figure 6 in ds099.pdf). So > why there is a separate name for a group of slices, i.e. where should > I count used CLBs instead of slices? > Hello, Piotr (nice name, if I may say so) Xilinx and Altera implement logic mainly in 4-input look-up tables with an associated flip-flop. We call that a Logic Cell. Two of the neighboring Logic Cells share some connections, so we call that a Slice, and either 2 or 4 Slices are grouped together in a CLB. For estimating purposes, stay with the LUT = Logic Cell = the number of flip-flops. Slices and CLBs are not very meaningful for estimates, although some people like them. Sorry to disappoint you about the leakage current... Peter AlfkeArticle: 93594
Hi I am looking for verilog code for a 64 bit wide datapath. I used the function generated by EASICS but did not get the correct results. If someone could post the code on how to use the EASICS function or give me the psedo code or just the steps I need to perform to make it work, I would really appreciate it. I would also appreciate a sample good packet with the correct CRC appended to it for verifying the code. thanks VikramArticle: 93595
On Sun, 25 Dec 2005 08:55:17 GMT, Kevin Brace <sa0les1@brac2ed3esi4gns5olut6ions.com> wrote: > From what I understand, PCI Express requires a bleeding-edge >oscilloscope which normally cost around $60,000, plus around $10,000 for >four FET probes. I think some clarification is in order. This is only necessary if you're developing a PCI-E PHY or physical layer interface. There is a specification called PIPE (physical interface for pci express) which defines a parallel clock, data recovered interface between a pci-e phy and the higher levels of the system. The equivalent to your PCI IP would be a block which sits above PIPE at which level you don't the scope and the probes if you assume that the PIPE block works.Article: 93596
> Marco ToschiMarco wrote: > Hallo, > I would to try this core. Where I could find the documentation for 8051 > interface? > > Has anyone ever used it? Yes, I used it for my PhD project - it works very well, I didn't find any bugs in the latest version. It is directly based on the Philips SJA1000, so all the registers and operation are the same - best to download the datasheet. I think I clocked this core at 25MHz. As for the interface options, I have only used the Wishbone, but for the 8051 spec, won't this do? http://www.intel.com/design/mcs51/datashts/27041908.pdf Various other datasheets are here: http://www.intel.com/design/mcs51/docs_mcs51.htm#Datasheets TomArticle: 93597
hey bijoy i am trying to implement a DDC with the xilinx virtex II-pro XUPV2P board. since you have started on an FPGA project, and are in the process of optimizing, i was wondering if you could help me in figuring out how to interface LVDS/CMOS i/o - data to be demodulated - with system generator or edk. i greatly appreciate your help. AshwinArticle: 93598
There are a paper of Dynamic Partial Reconfiguration "A Module-Based Dynamic Partial Reconfigration". I also resurch of this subject.Good Luck! : ) Alan ChenArticle: 93599
Hi, I have implemented a I2C bus core by myself. When reading, a multiple source 'error' would happen if your code assertes the acknowledge bit slightly earlier than the target deasserts the bus from the last read data bit or when writing, if your code deasserts the acknowledge bit slightly later than the target asserts the acknowledge bit on the bus. You may ignore them totally without any problem. Weng
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