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On a sunny day (Tue, 13 Dec 2005 10:03:38 +0100) it happened "Antti Lukats" <antti@openchip.org> wrote in <dnm2pa$a0$00$1@news.t-online.com>: >they talked about this producte for more than 3 years ago, now its finally >laucnhed > >* ADC 12bit 600KS/S >* MOSFET drivers >* user Flash rom >* onchip 1% accurate 100MHz oscillator >* oscillator for 32KHz watch crhrystal >* single 3.3V power supply > >http://xilant.com/content/view/22/2/ > >pretty nice features! > >Well PA3 is just about shipping so we may have to wait to get hands on onto >Fusion silicon, but it really looks like cool true single chip. > >hm,. if I think about it, this the silicon I have been waiting for, for the >last 10 years or so > >Antti > > http://www.actel.com/products/fusion/ AFS600 has 30 analog inputs, amazing. it is the Microchip philosophy, integrate everything.Article: 93076
On a sunny day (Tue, 13 Dec 2005 23:24:41 +1300) it happened Jim Granville <no.spam@designtools.co.nz> wrote in <439ea16a$1@clear.net.nz>: >Antti Lukats wrote: >> they talked about this producte for more than 3 years ago, now its finally >> laucnhed >> >> * ADC 12bit 600KS/S >> * MOSFET drivers >> * user Flash rom >> * onchip 1% accurate 100MHz oscillator >> * oscillator for 32KHz watch crhrystal >> * single 3.3V power supply >> >> http://xilant.com/content/view/22/2/ >> >> pretty nice features! >> >> Well PA3 is just about shipping so we may have to wait to get hands on onto >> Fusion silicon, but it really looks like cool true single chip. >> >> hm,. if I think about it, this the silicon I have been waiting for, for the >> last 10 years or so >> >> Antti > >- and large amounts of code flash, so much that the SRAM looks a bit >light..... > >Key determinant will be the price, as you can get >ARM+FLASH+ADC+32KHz+Ethernet, for rather less than the same bundle will >be in the Fusion. That means the FPGA aspect has to be very important, >to the design, and the single chip more important than a much cheaper >CPLD/Small FPGA alongside the ARM+FLASH+ADC+32KHz+Ethernet.... > >Devices from the uC segment to compare this with, would be the >ADuC7xx series : 12 Bit ADC, 12 Bit DAC, ARM CPU, FLASH, in 40-80 pins, >and the 'comming' uPSD ARMs from ST, which have 32MC CPLDs, and >Ethernet/CAN/USB, 96K Bytes SRAM and 2MBytes FLASH. > >Seems to me a smaller Fusion device, _and_ a "Well stacked" ARM Flash >Microcontroller, will be better value, than trying to roll it all >yourself in a bigger Fusion device. Time will tell, I guess. ADC is 600k samples per second. Not bad.Article: 93077
"Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag news:WaAnf.17576$Mi5.17212@dukeread07... > Antti Lukats wrote: > >> all 1-wire products *must* have unique number, it is IMPOSSIBLE to >> something else >> >> Antti > Well, not impossible. The codes are customized to the customer. IIRC, it > is a 48 bit code, and part of that number is a unique number assigned to > the customer, and part is a range of numbers assigned to that customer. > You can (or at least you used to be able to) get duplicate numbers within > your range. The codes, as I understand it, are added after the silicon is > manufactured. > > The problem with using these in attempt to secure a bitstream is that the > code is not secure...anyone with a data sheet and an oscilloscope or logic > analyzer can extract the serial number easily. Once you have the serial > number, it is nearly trivial to create a circuit that will mimic the > dallas part using what ever serial number you want to use. These parts > are intended for electronic serial numbers, not for secure encryption > keys. Hi Ray, you are one of the very few I am little bit 'scared' to argue with, but from maxim: "Unique, factory-lasered and tested 64-bit registration number assures absolute traceability because no two parts are alike" this applies for the 1-wire 64 ROM code what is PRODUCT code + 48 bit serial + CRC normally most "Key" things use only this code as the key, what is TOTAL bullshit and nonsense as it way easier to copy a dallas memory button then nornal door-key, having a reader in your lap and placing your hand for a second would do the job. As soon as you have the 64 bits then its easy to rebuild the 'emulator' - I have not done that, but I know what it takes. surprisingly many companies are selling products that use this 64 bit rom code as security key. one example is Atmel FPLSIC dongle, but there are many many more. the suggestion in this thread was to use secure SHA-1 memory for the protection, not the rom id code. DS2432 includes several nonvalotile areas that are protected and provide somewhat higher degree of safety. Whatever is written into those areas can sure be anything. I have not checked the xilinx bitstream security application for design flows, it could be that the SHA-1 is not used or not used properly yielding the actualy protection to near void. some hard macros from that XAPP I think are not correct at least failed with ISE 7.1 so I assume that design has not been tested a very big extent. The random number generator at least will not work out of box (at least not on all supported fpga families). And ah well the actual protection level depends on many more aspects if this approuch is used to protect edif or ngc files the protection level would be lower than protection .bit files AnttiArticle: 93078
wtxwtx@gmail.com wrote: > Hi, > 1. I want to know how to deal with marginal data for mean value filter, > > the pixels that cannot get full 9 neighboring pixels in general. > A common practice is to "mirror" pixels into the area surrounding the actual image data. Thus if you imagine extending your data array by placing mirrors at the 4 edges you should see that the top (1st) row would repeat to the row above it, but the row above that would contain data from the second row etc. Of course for a 3 x 3 operation (I think you meant 8 neighboring pixels) you only need one extra row or column. > 2. What is the best algorithm for mean value filter? Where is the > related paper? > A mean filter is just an average. This looks just like a convolution where the coefficients are all the same. This isn't particularly good as a filter so you might want to explore with other values. Another filter often used is the median filter which takes the median rather than the mean of the 3 x 3 (or other size) group of pixels. This is often used to remove "speckles." > 3. what book is the best one describing under what conditions mean > value filter is useful? > There are a number of good resources for image processing. "Video Demystified" is one of my favorites. Also for general algorithms I've used "The Scientist and Engineer's Guide to Digital Signal Processing" by Steven W Smith, published at one time by Analog Devices. > Thank you. > > WengArticle: 93079
Frank wrote: > While I have only a 40MHz clock connected to a 10 bit ADC, nothing connected > to > the analog input sockets, the chip is Analog AD9218 (ADC chip) EVM board. On > the LA, sampled outputs are 0~16 for one channel, -32~0 for the other > channel (400 MHz > timing mode). Is my board faulty? > > According to my simulation in digital design, my sampled inputs (10 bits > each) can not > have noise higher than 1 LSB (flipping small number of bit 0 causes > demodulation error). > > Is the setup I have workable or croaked? I took a look at the data sheet For the noise question: 1. The inputs need a low inpedance source. Someone already noted trying to tie the inputs to ground. 2. The Sample and hold (as with all sample and holds) will mix any extraneous noise, regardless of the precautions taken in the silicon. 3. A 10 bit converter usually has somewhere of the order of 8.5 ENOB (Effective number of bits) 4. The output will definitely be flipping codes if the input is at the (current) threshold. I would not expect the samples to be varying up and down too far, but... The datasheet shows pretty superior performance, but you still have a limited differential input range of either 1 or 2V (depending on device). So 1 LSB equates to just under a millivolt for the 1V range. It's not hard to get a few millivolts of noise onto an analog signal. Signal shielding and low inpedance drive are two of the various tricks we have up our sleeves. Keep in mind (you say you are demodulating a signal) that the various errors on the A-D section can get you +/-18LSB (worst case ) offset error, up to 8% fullscale (for 1V, that's 80mV) gain error and differential nonlinearity (variances between the encoding levels) of up to 1LSB. This all in addition to the irreducible (well, at the Nyquist limit) +/-0.5LSB quantization error. Note that differential nonlinearity acts as a curvature on the conversion curve which we would like to be a perfectly straight line. For the immediate question, for an unterminated input in a noisy environment (and most things are noisy at the millivolt level), I don't think you are seeing anything really unexpected. It can be dealt with though. Cheers PeteSArticle: 93080
Frank wrote: > While I have only a 40MHz clock connected to a 10 bit ADC, nothing connected > to > the analog input sockets, the chip is Analog AD9218 (ADC chip) EVM board. On > the LA, sampled outputs are 0~16 for one channel, -32~0 for the other > channel (400 MHz > timing mode). Is my board faulty? > > According to my simulation in digital design, my sampled inputs (10 bits > each) can not > have noise higher than 1 LSB (flipping small number of bit 0 causes > demodulation error). > > Is the setup I have workable or croaked? 1) Turn on a an autoranging digital multimeter with the test leads dangling. You will probably see the reading bounce around from +/-5 to 10 mV. Now twist the leads and short the ends. You probably won't see more than 1 mV that way. 2) Put your finger on your sound system's input terminal with nothing else connected to it. Set the volume control to a normal level. Either procedure will demonstrate the need for thought and care with analog signals. I'm sure you knew that, but it's easy to overlook. Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 93081
On Tue, 13 Dec 2005 14:07:20 +0100, kl31n <"kl31n(get rid of this to write me back)"@hotmail.com> wrote: >I'm having some hard time to understand what's wrong with this Xilinx >floating-point core included in the last IP update for LogicCORE. > >My design requires me to acquire data from an ADC and then, after some >processing to do a division between a couple floating point numbers every >200ns. > >The performances of the core aren't big enough to use just one, so I >implemented a core which feeds several dividers(made with the Xilinx core) >and then I reserialize it all. > >The design works fine till I pass numbers with a period down to 260ns, >going for lower periods the results get weird: the mantissa is correct, the >exponent instead is always fixed to 00111111, whatever it's supposed to be >instead. > >If anybody can offer some insight or even suggest a way of debugging, it >would be much appreciated because at the moment I don't have any idea of >what could be wrong. > >Thanks in advace, > >kl31n Before thinking about debugging, have you done any timing verifications ? Look at your timing reports first. Even with the slowest divider (at 30 cycle latency) and device (at around 200MHz) it shouldn't take more than 150ns though. Are you aware that the divider has a relatively large latency (30 Max apparently) ? How did you configure your dividers, what's your reported latency ? Again read your timing reports and pay attention to how you're feeding the dividers.Article: 93082
We turned to serial CRC7 and implemented it using "for loop" as want
for 40 bits ... and it give result in same cycle ... although is an
inefficient approach (takes more hardware)
i feel your approach is better than us ... we will try it ...
Anyways thanks Anti ... will meet u soon with some other issues
Article: 93083ENOB is relative to the maximum signal level and isn't much help if a measurement of system noise is desired. I might tie the inputs of my A/D converter to ground through a resister that approximates the source impedance the converter would see in normal operation. This should give a better idea of what is expected. I would not leave the terminals open in any case. In article <1134483342.048722.116970@z14g2000cwz.googlegroups.com>, "PeteS" <ps@fleetwoodmobile.com> wrote: >Frank wrote: >> While I have only a 40MHz clock connected to a 10 bit ADC, nothing connected >> to >> the analog input sockets, the chip is Analog AD9218 (ADC chip) EVM board. On >> the LA, sampled outputs are 0~16 for one channel, -32~0 for the other >> channel (400 MHz >> timing mode). Is my board faulty? >> >> According to my simulation in digital design, my sampled inputs (10 bits >> each) can not >> have noise higher than 1 LSB (flipping small number of bit 0 causes >> demodulation error). >> >> Is the setup I have workable or croaked? > >I took a look at the data sheet > >For the noise question: > >1. The inputs need a low inpedance source. Someone already noted trying >to tie the inputs to ground. > >2. The Sample and hold (as with all sample and holds) will mix any >extraneous noise, regardless of the precautions taken in the silicon. > >3. A 10 bit converter usually has somewhere of the order of 8.5 ENOB >(Effective number of bits) > >4. The output will definitely be flipping codes if the input is at the >(current) threshold. > >I would not expect the samples to be varying up and down too far, >but... > >The datasheet shows pretty superior performance, but you still have a >limited differential input range of either 1 or 2V (depending on >device). So 1 LSB equates to just under a millivolt for the 1V range. >It's not hard to get a few millivolts of noise onto an analog signal. >Signal shielding and low inpedance drive are two of the various tricks >we have up our sleeves. > >Keep in mind (you say you are demodulating a signal) that the various >errors on the A-D section can get you +/-18LSB (worst case ) offset >error, up to 8% fullscale (for 1V, that's 80mV) gain error and >differential nonlinearity (variances between the encoding levels) of up >to 1LSB. This all in addition to the irreducible (well, at the Nyquist >limit) +/-0.5LSB quantization error. Note that differential >nonlinearity acts as a curvature on the conversion curve which we would >like to be a perfectly straight line. > >For the immediate question, for an unterminated input in a noisy >environment (and most things are noisy at the millivolt level), I don't >think you are seeing anything really unexpected. It can be dealt with >though. > >Cheers > >PeteS >Article: 93084
kl31n wrote:
> If anybody can offer some insight or even suggest a way of debugging
I would write a testbench
and run a sim.
-- Mike Treseler
Article: 93085In my bgn file (report file of the last step: genrate programming file) I got the followig warning: WARNING:PhysDesignRules:781 - PULLDOWN on an active net. PULLDOWN of comp s_o<0>/s_o<0> is set but the tri state is not configured. I have the following constaints in my ucf file: NET s_o<0> LOC = G5; #GPLED0 NET "s_o<*>" PULLDOWN; NET "s_o<*>" TIG; NET "s_o<*>" SLEW = SLOW; NET "s_o<*>" DRIVE = 2; Can anybody help? MehdiArticle: 93086
Binary wrote:
> I want to my chip to run as fast as possible but what is
> the max value, which determines it?
fmax = 1/(Tcq+Tgate+Troute+Tsetup)
for the slowest path between registers.
A post-route static timing analysis
will measure this for your design.
--Mike Treseler
Article: 93087"GaLaKtIkUsT" <taileb.mehdi@gmail.com> schrieb im Newsbeitrag news:1134403664.635669.155490@f14g2000cwb.googlegroups.com... > Binary format and secret! > Good for protecting designs against piracy but too many problems for > those who want to do dynamic reconf :-( > > Mehdi > there is some info about the format available :) and a utility http://xilant.com/component/option,com_remository/Itemid,53/func,fileinfo/id,6/ bit2frames can be used to find some bit locations, etc... supports spartan3 converts .BIT file to redable "frames dump" anttiArticle: 93088
Hi All Is there anyway to directly stash bits into Xilinx (Spartan in this case) LUTs ? I need to hand-build a very small part of my design. Any suggestions? Thanks. -jcArticle: 93089
You can do this in FPGA Editor. If you are working in Webpack I don't believe that tool is included. You can either tweek the design after p&r or alternative create a macro that you use over and over. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "John" <jdc-rootbeer@hotmail.com> wrote in message news:1134497157.471856.291020@o13g2000cwo.googlegroups.com... > Hi All > Is there anyway to directly stash bits into Xilinx (Spartan in this > case) LUTs ? I need to hand-build a very small part of my design. > Any suggestions? > Thanks. -jc >Article: 93090
"John" <jdc-rootbeer@hotmail.com> schrieb im Newsbeitrag news:1134497157.471856.291020@o13g2000cwo.googlegroups.com... > Hi All > Is there anyway to directly stash bits into Xilinx (Spartan in this > case) LUTs ? I need to hand-build a very small part of my design. > Any suggestions? > Thanks. -jc > http://www.rockylogic.com/freebies.html its for virtex but should also work for others anttiArticle: 93091
I need a choice between 2 solutions : first solution: I can use a Freq=48MHz to create a 32MHz (multi *2, and div 3). But the signal for this freq isn't locate at a clock PIN (old card, so I can't change the PINOUT). This signal is locate PIN number AA4 in a Virtex XCV300-FG456). I have some problems to use DLL and BUF. Is someone could help me (use DLL and/or BUF without dedicated clk pin) !!. second solution: I can use a Freq=32MHz to create a 48MHz (multi*3, and div 2). But it very difficult to have this multi *3 !. I need a clk with a good precision, and if possible with around 50/50 of duty cycle. THANKS LOT for your help. Any suggestion will appreciate. Regards. Benoit. "Austin Lesea" <austin@xilinx.com> a écrit dans le message news: dnl3hk$f6910@xco-news.xilinx.com... > So it is.... > > Looks like getting 48 MHz from 32 MHz is not going to be as easy as it > first appears! > > What kind of output duty cycle and max jitter is needed? > > Austin > > Symon wrote: > > > "Austin Lesea" <austin@xilinx.com> wrote in message > > news:dnku2g$f699@xco-news.xilinx.com... > > > >>HB, > >> > >>In Virtex, the DLL may be used for mutliply by 2. That gets you to 64 > >>MHz. Then a subsequent DLL may be used for divide by 1.5 to get 48 MHz. > >> > >>Or, you may use a /1.5 circuit made out of FF's and a LUT. > >> > >>http://www.xilinx.com/xcell/xl33/xl33_30.pdf > >> > >>Austin > >> > > > > Would be a great solution, except that, sadly, 64MHz divided by 1.5 is > > 42.667 MHz, or thereabouts. > > Cheers, Syms. > > > >Article: 93092
http://Microcontroller.com/Embedded.asp?did=142
I'm taking a fast short survey of Microchip users to help decide what future directions
development tools should take. The survey is confidential - I don't even ask for your
email address, O.K.?
It's only 11 short questions that take less than a minute. Unless you really want
to get opinionated ("Embedded Developers opinionated?!?? Nah!!!") in which case, go
ahead, "comment" to your heart's content...!
http://Microcontroller.com/Embedded.asp?did=142
I'm basically trying to figure out whose development tools are completely reliable, and
whose tools really suck. And it's your opportunity to say whatever you want to say -
really!
If you have problems or praise, for any toolkit, TELL ME NOW or forever hold your, uh,
peace...
Thanks for your support,
- Bill Giovino
Executive Editor
http://Microcontroller.com
"Stamping out Shoddy Tools since 1995"
Article: 93093Hello all, I'm designing a component for integration in Altera's SOPC builder, for which I have to set some frequency dependent constants (for timing generation). How can I pass the component's assigned frequency from the SOPC builder to the VHDL? I can do either with VHDL generic or some kind of dynamic source code modification using the build script. Thanks, AvishayArticle: 93094
Hi Gabor, Thank you for your response. 1. 'Mirror' operation is interesting. 2. I wrote wrong. The correct name should be median filter, not mean filter. 3. I have the book, but didn't find the median filter item in it. 4. Do you have an algorithm that is very efficient? Weng WengArticle: 93095
Bill Giovino wrote: <snip off-topic for comp.arch.fpga, and comp.realtime> > I'm basically trying to figure out whose development tools are completely reliable, and > whose tools really suck. And it's your opportunity to say whatever you want to say - > really! To what end ? Who is paying for this, and what do you propose to do with the results ? You have already trawled comp.arch.embedded on this - what was wrong with those replies ? -jgArticle: 93096
"Jim Granville" wrote... > Bill Giovino wrote: > > I'm basically trying to figure out whose development tools are completely reliable, and > > whose tools really suck. And it's your opportunity to say whatever you want to say - > > really! > > To what end ? Who is paying for this, and what do you propose to do > with the results ? I'm looking to expand the sample. The results will help us determine the focus of a brand new User Support section of Microcontroller.com that we'll be opening in February.Article: 93097
"HB" <bhb22l@yahoo.fr> wrote in message news:dnn44o$lu5$1@s1.news.oleane.net... >I need a choice between 2 solutions : > > first solution: > I can use a Freq=48MHz to create a 32MHz (multi *2, and div 3). > But the signal for this freq isn't locate at a clock PIN (old card, so I > can't change the PINOUT). > This signal is locate PIN number AA4 in a Virtex XCV300-FG456). > I have some problems to use DLL and BUF. > Is someone could help me (use DLL and/or BUF without dedicated clk pin) > !!. > Benoit, This is the way to go. You can use any pin as an input clock. IIRC you may need to instantiate an IBUF and the DLL/GBUF in your code. There must be examples of this in previous postings here and in Xilinx's documentation. Cheers, Syms.Article: 93098
Antti Lukats wrote: Antti, no reason to be scared of arguing with me. I'm not always right, you know! My experience with these 1 wire electronic serial numbers was with Dallas semiconductor parts almost 15 years ago. In that case, the company I was working for was able to get duplicates made by Dallas. Like you mentioned, these offer close to zero security. Any yo-yo with an ounce of electronics knowledge can obtain the code from it, and it doesn't take much more than that to make a circuit that will mimic the serial number. We did for testing in the lab using a PIC microcontroller. So even with Maxim, it isn't technically impossible to get a duplicate, it is just made procedurally inconvenient by a company policy,but that's it.Article: 93099
"Antti Lukats" <antti@openchip.org> wrote in message
news:dnn395$tgl$1@online.de...
>
> "John" <jdc-rootbeer@hotmail.com> schrieb im Newsbeitrag
> news:1134497157.471856.291020@o13g2000cwo.googlegroups.com...
>> Hi All
>> Is there anyway to directly stash bits into Xilinx (Spartan in this
>> case) LUTs ? I need to hand-build a very small part of my design.
>> Any suggestions?
>> Thanks. -jc
>>
> http://www.rockylogic.com/freebies.html
>
> its for virtex but should also work for others
>
> antti
Nice VHDL example. It's pretty simple to do the LUT instantiation in
Verilog as well. The INIT parameter just needs the right value which can be
provided through localparam values where I0=16'haaaa, I1=16'hcccc,
I2=16'hf0f0, and I3=16'hff00. The instantiation is pretty straightforward;
one example starts off:
LUT3 #( I0 & I1 | ~I0 & I2 )
MyLut3Name[3:0] ( .O(myOut), .I0( ...
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