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HB wrote: Gee, that sounds a lot like the GV associates board I used for the Radar project shown in the gallery page of my website (the one with the CPU fans on the FPGAs). In that case, there was a 48MHz clock for a USB interface chip that was also connected to the FPGA, but not through a clock pin and we had a separate clock oscillator that came through another pin (I think it was 66 MHz). If you aren't worried about the relative phase of the 32 and 48 Mhz clocks, you can bring the 48 Mhz clock in through the non-clock pin and use general routing resources to get it to a DLL. From there you can do the divide by 1.5 to get 32 MHz. I'd have to do some digging through the archives to find the clock module for that design, but the point is you don't necessarily have to bring the clock in on a clock pin if you aren't worried about clock skew.Article: 93101
Hi Ray, I thought you said you already had ISE 8.1? From the press release, http://www.xilinx.com/prs_rls/software/05114ise8_1i.htm Industry's Only Partial Reconfiguration Solution With the 8.1i release, Xilinx has added a new methodology to enhance the industry's first and only partial reconfiguration solution. Partial reconfiguration reduces system cost, size, device count, and power consumption, useful for a wide variety of applications, such as Software Defined Radio (SDR) and high performance computing. Designers can now dynamically load different hardware configurations into the same area of the FPGA while the rest of the device continues running. This real-time dimension to programmability builds upon field upgradeability and multi-boot approaches that have enabled many Xilinx customers to boost system reliability with real-time diagnostics, lower field service costs and extend the lifespan of existing products in the marketplace. I fully expect that ISE8.1 has a "comprehensive set of tools for working with partial reconfiguration" and encourage as many C.A.F. readers as possible to try it out. I'd appreciate it that if, by any chance, you should happen to find any slight problems, please report them to Xilinx ASAP so they're fixed by the time I come to try it. With apologies for my terrible cynicism, Syms. ;-) "Ray Andraka" <ray@andraka.com> wrote in message news:NgAnf.17577$Mi5.17387@dukeread07... > Javier Castillo wrote: > >> >> Is not so difficult, is question of patiente and experience and know >> very well what you are doing. >> >> Javier >> > Patience is an understatement. The tools for partial reconfiguration are > virtually non-existent. Without suitable tools, using dynamic partial > reconfiguration in a design is a lot of painstaking work, and with the > size of the devices available today is not economically justified in the > vast majority of applications. A comprehensive set of tools for working > with partial reconfiguration could easily change that, but I don't expect > to see the necessary extensions to the tools any time soon.Article: 93102
avishay wrote: > I'm designing a component for integration in Altera's SOPC builder, for > which I have to set some frequency dependent constants (for timing > generation). How can I pass the component's assigned frequency from the > SOPC builder to the VHDL? I can do either with VHDL generic or some > kind of dynamic source code modification using the build script. If you define a generic in the top level of your component, SOPC should allow the user to edit the value when they create an instance of the component. Regards, MarkArticle: 93103
Monica wrote: >Dear Mr.Alan, > >I have changed my logic such mpegData is considered as a register >instead of combitional logic and kept them in IOBs(through help).The >output is not only good but also fast.Thanks a lot for your suggestion. > > Ah, well, that explains the 7 ns lag. While mpegSync is prompt from the FF (register) the combinatorial logic on mpegData following the last register produced the delay. JonArticle: 93104
Not quite on topic - but I thought somebody here might know - Does anybody know where I can get hold of the SGMII spec (Used on SFP modules, esp. 10/100/1000 copper)? All I can find in the SFP/PHY datasheets that I've looked at so far is references to the data bytes being repeated 10 times (Which doesn't help much with autonegotiation). Thanks, JeremyArticle: 93105
Hi all! Does anybody knows why the Xilinx ISE Foundation 8.1i is already released but not the ISE WebPack 8.1i ? MehdiArticle: 93106
hi all has anyone got any documents or refferals for 'J Tag Protocol ' , for reconfigurable hardware. i would appreciate if any tutorials or realted links/documents can b passed on . thanks abhishekArticle: 93107
Hi! Excuse me for the following reflexion. I think that Microchip doen't work in FPGA fields (I used in the past some microcontrollers and memories from Microchip) so why posting in comp.lang.fpga ? I talking about that because you can find more audience posting to groups whose topic is related to the topic of you survey! MehdiArticle: 93108
"John Herman" <John_W_Herman@yahoo.com> wrote in message news:irDnf.6196$hI1.3714@tornado.socal.rr.com... > ENOB is relative to the maximum signal level and isn't much help if a > measurement of system noise is desired. > > I might tie the inputs of my A/D converter to ground through a resister that > approximates the source impedance the converter would see in normal operation. > This should give a better idea of what is expected. I would not leave the > terminals open in any case. > Yeah, it seems a good idea to terminate the ADC input with 50 Ohm resister, I will try that with one 50Ohm termination. my DAC output is said to terminate with a 50Ohm output resistance, while when I connect the output with a plain cable into oscilloscope with 50 Ohm termination, the oscilloscope showed amplitude of only 100mV when digital outputs are in full swing. When digital outputs are zeros, the oscilloscope shows a 50mV peak to peak random noise.Article: 93109
Symon wrote: > Hi Ray, > I thought you said you already had ISE 8.1? From the press release, > http://www.xilinx.com/prs_rls/software/05114ise8_1i.htm > I downloaded it last week. I haven't installed it yet, and probably won't until I get the current projects out the door. As far as the marketing fluff, well, it remains to be seen. Partial reconfiguration, especially while the clock is running is a can full of worms. I touch on some of the issues in my 1998 paper on a dynamically reconfigured video processor. I've tangled with that tough nut. I've been around the block enough times to know that ver 0.1 of a tool NEVER hits the mark even though it is ALWAYS touted as the last tool you'll ever need etc. If it does half of what it is being touted as doing, it will be a huge step in the right direction, but even if the tool is perfect I doubt it will make partial reconfiguration a reality in the vast majority of the applications out there. Moore's law is making it economically unjustified in most cases. The engineering time to successfully pull off partial reconfiguration is quite a bit more expensive than the delta cost to get into a bigger device. A lot of that is the current state of the tools for PR, but there is an equally big piece due to the adding the time dimension to the circuit architecture that makes managing the PR design considerably harder to do tools or not. Based on the static designs I have seen turned out by FPGA designers who ought to know better, I don't see freshly debuted tool taking up enough slack to make it suddenly easy. Heck, there are enough bugs in the tools for static designs to keep the hotline employed without introducing the complexity of a self-modifying design. OK, time to take off the cynical hat. Yes, partial reconfiguration does have merit, and there are some applications where it can pay off. However, anyone planning to do so should take a long hard honest look at the effort involved before signing up to a budget and schedule to make it happen.Article: 93110
wtxwtx@gmail.com wrote: > Hi Gabor, > Thank you for your response. > > 1. 'Mirror' operation is interesting. > > 2. I wrote wrong. The correct name should be median filter, not mean > filter. > > 3. I have the book, but didn't find the median filter item in it. > > 4. Do you have an algorithm that is very efficient? > > Weng > > Weng This is the most efficient way I could develop for true 3x3 Median http://www.xilinx.com/xcell/xl23/xl23_16.pdf 5x5 follows same structure but is MUCH larger. A 'pseudo' median can be done a bit cheaper by taking middle of each three pixels, and then taking middle of those three... You can use SRL16s for mirroring horizontally, need blockRAMs for vertical. JohnArticle: 93111
This wasn't my meaning. In the main SOPC builder screen, a clock is assigned to each component, and the frequency of each clock is entered at a separate table. I need access to this information. Thanks, AvishayArticle: 93112
GaLaKtIkUs™ schrieb:
> Hi all!
> Does anybody knows why the Xilinx ISE Foundation 8.1i is already
> released but not the ISE WebPack 8.1i ?
>
> Mehdi
>
Hi,
because it was always so... :-)
Paying custumers are served first.
But if 8.1 is already released the webpack will follow short after.
be patient
Eilert
Article: 93113"ABS" <abhishekbedi@gmail.com> schrieb im Newsbeitrag news:1134518668.567217.216410@o13g2000cwo.googlegroups.com... > hi all > > has anyone got any documents or refferals for 'J Tag Protocol ' , for > reconfigurable hardware. I bet almost anyone here has... but JTAG primary function is BOUNDARY SCAN and not hardware reconfiguration, even though lots (virtually all) current FPGA allow configuration over JTAG interface > i would appreciate if any tutorials or realted links/documents can b > passed on . > thanks > abhishek > it takes a few seconds to find those documents by googling for them, if you are too lazy for that there is no one who can help you. Antti PS I admire 'creative lazyness' but not people who are just lazy.Article: 93114
I'm a paying customer! I have now the BaseX 7.1i!!! I don't need the full ISE since I'm using an FX12 Virtex-4 B-) I'm patiently waiting.... Another question about ISE8.1i: are the dynamic reconf functions standard functions or only available as an option? MehdiArticle: 93115
"GaLaKtIkUsT" <taileb.mehdi@gmail.com> schrieb im Newsbeitrag news:1134544365.005699.241870@f14g2000cwb.googlegroups.com... > I'm a paying customer! > I have now the BaseX 7.1i!!! > I don't need the full ISE since I'm using an FX12 Virtex-4 B-) > I'm patiently waiting.... > Another question about ISE8.1i: are the dynamic reconf functions > standard functions or only available as an option? > > Mehdi > bad luck for you, BaseX is gone away from now, so you are downgraded to WebPack meaning you longer are an paying customer (unless you upgrade to 8.1 Foundation). 8.1 is available but through ESD or your FAE, but I bet the paying BaseX owners still have to wait. AnttiArticle: 93116
"Antti Lukats" <antti@openchip.org> writes: > 8.1 is available but through ESD or your FAE, but I bet the paying BaseX > owners still have to wait. Several people here have said that, but when I go to the ESD page, it isn't listed. I called Xilinx, and they said that 8.1i is NOT available for ESD yet. I'm confused. EricArticle: 93117
"Eric Smith" <eric@brouhaha.com> schrieb im Newsbeitrag news:qhoe3kcebm.fsf@ruckus.brouhaha.com... > "Antti Lukats" <antti@openchip.org> writes: >> 8.1 is available but through ESD or your FAE, but I bet the paying BaseX >> owners still have to wait. > > Several people here have said that, but when I go to the ESD page, it > isn't listed. I called Xilinx, and they said that 8.1i is NOT available > for ESD yet. I'm confused. > > Eric could be, but the FAEs have access that is 99.9% sure, but the confusion sure is there. Also the making the paid BaseX owners from now on proud own of 'paid' free WebPack, I bet there are some not so happy customers... AnttiArticle: 93118
GaLaKtIkUs™ wrote: > Another question about ISE8.1i: are the dynamic reconf functions > standard functions or only available as an option? Xilinx Virtex December newsletter says: ISE customers can obtain partial reconfiguration capability by contacting their local FAEs. dunno why...Article: 93119
"Frank" <Francis.invalid@hotmail.com> wrote in message news:439f771e$1@news.starhub.net.sg... > > "John Herman" <John_W_Herman@yahoo.com> wrote in message > news:irDnf.6196$hI1.3714@tornado.socal.rr.com... >> ENOB is relative to the maximum signal level and isn't much help if a >> measurement of system noise is desired. >> >> I might tie the inputs of my A/D converter to ground through a resister > that >> approximates the source impedance the converter would see in normal > operation. >> This should give a better idea of what is expected. I would not leave > the >> terminals open in any case. >> > > Yeah, it seems a good idea to terminate the ADC input with 50 Ohm > resister, > I will try that > with one 50Ohm termination. > > my DAC output is said to terminate with a 50Ohm output resistance, while > when I connect the output with a plain cable into oscilloscope with 50 Ohm > termination, the > oscilloscope showed amplitude of only 100mV when digital outputs are in > full swing. That doesn't sound very promising. You've set it up for 20mA peak output so your outputs in full swing should be varying between +/- 20 mA ? Through a 1:1 output transformer and into a 50 ohm termination I would have expected close to 2V peak to peak. >When digital outputs are zeros, the oscilloscope shows a 50mV peak to peak >random noise.Article: 93120
Just got the old PC from the storage of the lab which has ISE 4.2 installed. I only need the PC to program Virtex 6000 and xc18v04, do I need to upgrade to ISE 6 or above? Thank you.Article: 93121
I can confirm 8.1 availability 100%. I already have it installed on my machine. We had just purchased 7.1 like 3 months back, and we got an email last week which included a download link for a 1.5GB installable image (common to all supported OSes). It took me a while to successfull download the entire image, but as of two days back, I have had it running. Havent put it thru the paces yet, though, so I dunno if theres a significant improvement from the mess that 7.1 was. -AbgoyalArticle: 93122
Il Tue, 13 Dec 2005 16:40:06 GMT, mk ha scritto: > Before thinking about debugging, have you done any timing > verifications ? Look at your timing reports first. Even with the > slowest divider (at 30 cycle latency) and device (at around 200MHz) it > shouldn't take more than 150ns though. Are you aware that the divider > has a relatively large latency (30 Max apparently) ? How did you > configure your dividers, what's your reported latency ? Again read > your timing reports and pay attention to how you're feeding the > dividers. The timing report tells me that I can run my block at 157MHz and I'm running it at 100Mhz, so it has to be 330ns the latency(the core, being in basic mode to take advantage of the handshaking, has a 33 cycles latency). By parallelizing to n dividers I expected I could pretend to have a latency of (ceil(33 / n) * T), while I cannot get under 260ns and this with whatsoever the number of dividers. Thanks, kl31nArticle: 93123
Frank wrote: > Just got the old PC from the storage of the lab which has ISE 4.2 installed. > I only need the PC to program Virtex 6000 and xc18v04, do I need to upgrade > to ISE 6 or above? > > Thank you. These devices are supported in Foundation 4.1i which I believe was released at the same time as ISE 4.2, so I would assume you can use it. If you're not using any legacy features (support for older devices or Aldec-based schematics) though I would recommend updating.Article: 93124
> I would write a testbench > and run a sim. That's what I did, but I don't have access to Xilinx cores internals to really see what's going on and what I could do to fix the problem. The behavioural model always works like expected, the Post-Translate instead cannot work correctly with data entereing with a period smaller than 260n. Thanks, kl31n
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